ccm_config 1554 drivers/crypto/ccree/cc_aead.c u8 *b0 = req_ctx->ccm_config + CCM_B0_OFFSET; ccm_config 1555 drivers/crypto/ccree/cc_aead.c u8 *a0 = req_ctx->ccm_config + CCM_A0_OFFSET; ccm_config 1556 drivers/crypto/ccree/cc_aead.c u8 *ctr_count_0 = req_ctx->ccm_config + CCM_CTR_COUNT_0_OFFSET; ccm_config 1564 drivers/crypto/ccree/cc_aead.c memset(req_ctx->ccm_config, 0, AES_BLOCK_SIZE * 3); ccm_config 63 drivers/crypto/ccree/cc_aead.h u8 ccm_config[CCM_CONFIG_BUF_SIZE] ____cacheline_aligned; ccm_config 1049 drivers/crypto/ccree/cc_buffer_mgr.c void *addr = areq_ctx->ccm_config + CCM_CTR_COUNT_0_OFFSET; ccm_config 1063 drivers/crypto/ccree/cc_buffer_mgr.c rc = cc_set_aead_conf_buf(dev, areq_ctx, areq_ctx->ccm_config,