ccic0_lock 202 drivers/clk/mmp/clk-of-mmp2.c static DEFINE_SPINLOCK(ccic0_lock); ccic0_lock 221 drivers/clk/mmp/clk-of-mmp2.c {0, "ccic0_sphy_div", "ccic0_mix_clk", CLK_SET_RATE_PARENT, APMU_CCIC0, 10, 5, 0, &ccic0_lock}, ccic0_lock 236 drivers/clk/mmp/clk-of-mmp2.c {MMP2_CLK_CCIC_ARBITER, "ccic_arbiter", "vctcxo", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x1800, 0x1800, 0x0, 0, &ccic0_lock}, ccic0_lock 237 drivers/clk/mmp/clk-of-mmp2.c {MMP2_CLK_CCIC0, "ccic0_clk", "ccic0_mix_clk", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x1b, 0x1b, 0x0, 0, &ccic0_lock}, ccic0_lock 238 drivers/clk/mmp/clk-of-mmp2.c {MMP2_CLK_CCIC0_PHY, "ccic0_phy_clk", "ccic0_mix_clk", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x24, 0x24, 0x0, 0, &ccic0_lock}, ccic0_lock 239 drivers/clk/mmp/clk-of-mmp2.c {MMP2_CLK_CCIC0_SPHY, "ccic0_sphy_clk", "ccic0_sphy_div", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x300, 0x300, 0x0, 0, &ccic0_lock}, ccic0_lock 260 drivers/clk/mmp/clk-of-mmp2.c &ccic0_mix_config, &ccic0_lock); ccic0_lock 185 drivers/clk/mmp/clk-of-pxa168.c static DEFINE_SPINLOCK(ccic0_lock); ccic0_lock 193 drivers/clk/mmp/clk-of-pxa168.c {0, "ccic0_mux", ccic_parent_names, ARRAY_SIZE(ccic_parent_names), CLK_SET_RATE_PARENT, APMU_CCIC0, 6, 1, 0, &ccic0_lock}, ccic0_lock 194 drivers/clk/mmp/clk-of-pxa168.c {0, "ccic0_phy_mux", ccic_phy_parent_names, ARRAY_SIZE(ccic_phy_parent_names), CLK_SET_RATE_PARENT, APMU_CCIC0, 7, 1, 0, &ccic0_lock}, ccic0_lock 198 drivers/clk/mmp/clk-of-pxa168.c {0, "ccic0_sphy_div", "ccic0_mux", CLK_SET_RATE_PARENT, APMU_CCIC0, 10, 5, 0, &ccic0_lock}, ccic0_lock 209 drivers/clk/mmp/clk-of-pxa168.c {PXA168_CLK_CCIC0, "ccic0_clk", "ccic0_mux", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x1b, 0x1b, 0x0, 0, &ccic0_lock}, ccic0_lock 210 drivers/clk/mmp/clk-of-pxa168.c {PXA168_CLK_CCIC0_PHY, "ccic0_phy_clk", "ccic0_phy_mux", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x24, 0x24, 0x0, 0, &ccic0_lock}, ccic0_lock 211 drivers/clk/mmp/clk-of-pxa168.c {PXA168_CLK_CCIC0_SPHY, "ccic0_sphy_clk", "ccic0_sphy_div", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x300, 0x300, 0x0, 0, &ccic0_lock}, ccic0_lock 191 drivers/clk/mmp/clk-of-pxa910.c static DEFINE_SPINLOCK(ccic0_lock); ccic0_lock 199 drivers/clk/mmp/clk-of-pxa910.c {0, "ccic0_mux", ccic_parent_names, ARRAY_SIZE(ccic_parent_names), CLK_SET_RATE_PARENT, APMU_CCIC0, 6, 1, 0, &ccic0_lock}, ccic0_lock 200 drivers/clk/mmp/clk-of-pxa910.c {0, "ccic0_phy_mux", ccic_phy_parent_names, ARRAY_SIZE(ccic_phy_parent_names), CLK_SET_RATE_PARENT, APMU_CCIC0, 7, 1, 0, &ccic0_lock}, ccic0_lock 204 drivers/clk/mmp/clk-of-pxa910.c {0, "ccic0_sphy_div", "ccic0_mux", CLK_SET_RATE_PARENT, APMU_CCIC0, 10, 5, 0, &ccic0_lock}, ccic0_lock 215 drivers/clk/mmp/clk-of-pxa910.c {PXA910_CLK_CCIC0, "ccic0_clk", "ccic0_mux", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x1b, 0x1b, 0x0, 0, &ccic0_lock}, ccic0_lock 216 drivers/clk/mmp/clk-of-pxa910.c {PXA910_CLK_CCIC0_PHY, "ccic0_phy_clk", "ccic0_phy_mux", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x24, 0x24, 0x0, 0, &ccic0_lock}, ccic0_lock 217 drivers/clk/mmp/clk-of-pxa910.c {PXA910_CLK_CCIC0_SPHY, "ccic0_sphy_clk", "ccic0_sphy_div", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x300, 0x300, 0x0, 0, &ccic0_lock},