cchip              50 arch/alpha/kernel/sys_dp264.c 	register tsunami_cchip *cchip = TSUNAMI_cchip;
cchip              69 arch/alpha/kernel/sys_dp264.c 	dim0 = &cchip->dim0.csr;
cchip              70 arch/alpha/kernel/sys_dp264.c 	dim1 = &cchip->dim1.csr;
cchip              71 arch/alpha/kernel/sys_dp264.c 	dim2 = &cchip->dim2.csr;
cchip              72 arch/alpha/kernel/sys_dp264.c 	dim3 = &cchip->dim3.csr;
cchip              89 arch/alpha/kernel/sys_dp264.c 	if (bcpu == 0) dimB = &cchip->dim0.csr;
cchip              90 arch/alpha/kernel/sys_dp264.c 	else if (bcpu == 1) dimB = &cchip->dim1.csr;
cchip              91 arch/alpha/kernel/sys_dp264.c 	else if (bcpu == 2) dimB = &cchip->dim2.csr;
cchip              92 arch/alpha/kernel/sys_dp264.c 	else dimB = &cchip->dim3.csr;
cchip              63 arch/alpha/kernel/sys_titan.c 	register titan_cchip *cchip = TITAN_cchip;
cchip              84 arch/alpha/kernel/sys_titan.c 	dim0 = &cchip->dim0.csr;
cchip              85 arch/alpha/kernel/sys_titan.c 	dim1 = &cchip->dim1.csr;
cchip              86 arch/alpha/kernel/sys_titan.c 	dim2 = &cchip->dim2.csr;
cchip              87 arch/alpha/kernel/sys_titan.c 	dim3 = &cchip->dim3.csr;
cchip             104 arch/alpha/kernel/sys_titan.c 	dimB = &cchip->dim0.csr;
cchip             105 arch/alpha/kernel/sys_titan.c 	if (bcpu == 1) dimB = &cchip->dim1.csr;
cchip             106 arch/alpha/kernel/sys_titan.c 	else if (bcpu == 2) dimB = &cchip->dim2.csr;
cchip             107 arch/alpha/kernel/sys_titan.c 	else if (bcpu == 3) dimB = &cchip->dim3.csr;