cbpr               60 arch/arm64/kvm/vgic-sys-reg-v3.c 		vmcr.cbpr = (val & ICC_CTLR_EL1_CBPR_MASK) >> ICC_CTLR_EL1_CBPR_SHIFT;
cbpr               78 arch/arm64/kvm/vgic-sys-reg-v3.c 		val |= (vmcr.cbpr << ICC_CTLR_EL1_CBPR_SHIFT) & ICC_CTLR_EL1_CBPR_MASK;
cbpr              130 arch/arm64/kvm/vgic-sys-reg-v3.c 	if (!vmcr.cbpr) {
cbpr              278 virt/kvm/arm/vgic/vgic-mmio-v2.c 		val |= vmcr.cbpr << GIC_CPU_CTRL_CBPR_SHIFT;
cbpr              325 virt/kvm/arm/vgic/vgic-mmio-v2.c 		vmcr.cbpr = !!(val & GIC_CPU_CTRL_CBPR);
cbpr              233 virt/kvm/arm/vgic/vgic-v2.c 	vmcr |= (vmcrp->cbpr << GICH_VMCR_CBPR_SHIFT) &
cbpr              262 virt/kvm/arm/vgic/vgic-v2.c 	vmcrp->cbpr = (vmcr & GICH_VMCR_CBPR_MASK) >>
cbpr              224 virt/kvm/arm/vgic/vgic-v3.c 	vmcr |= (vmcrp->cbpr << ICH_VMCR_CBPR_SHIFT) & ICH_VMCR_CBPR_MASK;
cbpr              257 virt/kvm/arm/vgic/vgic-v3.c 	vmcrp->cbpr = (vmcr & ICH_VMCR_CBPR_MASK) >> ICH_VMCR_CBPR_SHIFT;
cbpr              141 virt/kvm/arm/vgic/vgic.h 	u32	cbpr;