cbar              499 drivers/iommu/arm-smmu.c 	bool stage1 = cfg->cbar != CBAR_TYPE_S2_TRANS;
cbar              558 drivers/iommu/arm-smmu.c 	stage1 = cfg->cbar != CBAR_TYPE_S2_TRANS;
cbar              574 drivers/iommu/arm-smmu.c 	reg = FIELD_PREP(CBAR_TYPE, cfg->cbar);
cbar              700 drivers/iommu/arm-smmu.c 		cfg->cbar = CBAR_TYPE_S1_TRANS_S2_BYPASS;
cbar              723 drivers/iommu/arm-smmu.c 		cfg->cbar = CBAR_TYPE_S2_TRANS;
cbar              295 drivers/iommu/arm-smmu.h 	enum arm_smmu_cbar_type		cbar;
cbar              104 drivers/pci/hotplug/ibmphp.h 	u32 cbar;
cbar             2194 drivers/vme/bridges/vme_tsi148.c 	u32 cbar, crat, vstat;
cbar             2216 drivers/vme/bridges/vme_tsi148.c 	cbar = ioread32be(bridge->base + TSI148_CBAR);
cbar             2217 drivers/vme/bridges/vme_tsi148.c 	cbar = (cbar & TSI148_CRCSR_CBAR_M)>>3;
cbar             2221 drivers/vme/bridges/vme_tsi148.c 	if (cbar != vstat) {
cbar             2222 drivers/vme/bridges/vme_tsi148.c 		cbar = vstat;
cbar             2224 drivers/vme/bridges/vme_tsi148.c 		iowrite32be(cbar<<3, bridge->base + TSI148_CBAR);
cbar             2226 drivers/vme/bridges/vme_tsi148.c 	dev_info(tsi148_bridge->parent, "CR/CSR Offset: %d\n", cbar);