AREA             1232 drivers/gpu/drm/exynos/exynos_drm_fimc.c 	{ IPP_SIZE_LIMIT(AREA, .h = { 16, 4224, 2 }, .v = { 16, 0, 2 }) },
AREA             1240 drivers/gpu/drm/exynos/exynos_drm_fimc.c 	{ IPP_SIZE_LIMIT(AREA, .h = { 16, 1920, 2 }, .v = { 16, 0, 2 }) },
AREA             1248 drivers/gpu/drm/exynos/exynos_drm_fimc.c 	{ IPP_SIZE_LIMIT(AREA, .h = { 128, 1920, 2 }, .v = { 128, 0, 2 }) },
AREA             1255 drivers/gpu/drm/exynos/exynos_drm_fimc.c 	{ IPP_SIZE_LIMIT(AREA, .h = { 128, 1366, 2 }, .v = { 128, 0, 2 }) },
AREA             1363 drivers/gpu/drm/exynos/exynos_drm_gsc.c 	{ IPP_SIZE_LIMIT(AREA, .h = { 16, 4800, 2 }, .v = { 8, 3344, 2 }) },
AREA             1371 drivers/gpu/drm/exynos/exynos_drm_gsc.c 	{ IPP_SIZE_LIMIT(AREA, .h = { 16, 4800, 2 }, .v = { 8, 3344, 2 }) },
AREA             1379 drivers/gpu/drm/exynos/exynos_drm_gsc.c 	{ IPP_SIZE_LIMIT(AREA, .h = { 16, 4800, 1 }, .v = { 8, 3344, 1 }) },
AREA              361 drivers/gpu/drm/exynos/exynos_drm_rotator.c 	{ IPP_SIZE_LIMIT(AREA, .h.align = 2, .v.align = 2) },
AREA              366 drivers/gpu/drm/exynos/exynos_drm_rotator.c 	{ IPP_SIZE_LIMIT(AREA, .h.align = 4, .v.align = 4) },
AREA              371 drivers/gpu/drm/exynos/exynos_drm_rotator.c 	{ IPP_SIZE_LIMIT(AREA, .h.align = 4, .v.align = 4) },
AREA              376 drivers/gpu/drm/exynos/exynos_drm_rotator.c 	{ IPP_SIZE_LIMIT(AREA, .h.align = 2, .v.align = 2) },
AREA              381 drivers/gpu/drm/exynos/exynos_drm_rotator.c 	{ IPP_SIZE_LIMIT(AREA, .h.align = 8, .v.align = 8) },
AREA              386 drivers/gpu/drm/exynos/exynos_drm_rotator.c 	{ IPP_SIZE_LIMIT(AREA, .h.align = 8, .v.align = 8) },
AREA              391 drivers/gpu/drm/exynos/exynos_drm_rotator.c 	{ IPP_SIZE_LIMIT(AREA, .h.align = 8, .v.align = 8) },
AREA              598 drivers/gpu/drm/exynos/exynos_drm_scaler.c 	{ IPP_SIZE_LIMIT(AREA, .h.align = 2, .v.align = 2) },
AREA              605 drivers/gpu/drm/exynos/exynos_drm_scaler.c 	{ IPP_SIZE_LIMIT(AREA, .h.align = 2, .v.align = 1) },
AREA              618 drivers/gpu/drm/exynos/exynos_drm_scaler.c 	{ IPP_SIZE_LIMIT(AREA, .h.align = 16, .v.align = 16) },