cached_irq_mask 24 arch/alpha/kernel/irq_i8259.c static unsigned int cached_irq_mask = 0xffff; cached_irq_mask 40 arch/alpha/kernel/irq_i8259.c i8259_update_irq_hw(d->irq, cached_irq_mask &= ~(1 << d->irq)); cached_irq_mask 47 arch/alpha/kernel/irq_i8259.c i8259_update_irq_hw(irq, cached_irq_mask |= 1 << irq); cached_irq_mask 22 arch/alpha/kernel/irq_pyxis.c static unsigned long cached_irq_mask; cached_irq_mask 35 arch/alpha/kernel/irq_pyxis.c pyxis_update_irq_hw(cached_irq_mask |= 1UL << (d->irq - 16)); cached_irq_mask 41 arch/alpha/kernel/irq_pyxis.c pyxis_update_irq_hw(cached_irq_mask &= ~(1UL << (d->irq - 16))); cached_irq_mask 48 arch/alpha/kernel/irq_pyxis.c unsigned long mask = cached_irq_mask &= ~bit; cached_irq_mask 75 arch/alpha/kernel/irq_pyxis.c pld &= cached_irq_mask; cached_irq_mask 37 arch/alpha/kernel/sys_alcor.c static unsigned long cached_irq_mask; cached_irq_mask 49 arch/alpha/kernel/sys_alcor.c alcor_update_irq_hw(cached_irq_mask |= 1UL << (d->irq - 16)); cached_irq_mask 55 arch/alpha/kernel/sys_alcor.c alcor_update_irq_hw(cached_irq_mask &= ~(1UL << (d->irq - 16))); cached_irq_mask 39 arch/alpha/kernel/sys_cabriolet.c static unsigned long cached_irq_mask = ~0UL; cached_irq_mask 51 arch/alpha/kernel/sys_cabriolet.c cabriolet_update_irq_hw(d->irq, cached_irq_mask &= ~(1UL << d->irq)); cached_irq_mask 57 arch/alpha/kernel/sys_cabriolet.c cabriolet_update_irq_hw(d->irq, cached_irq_mask |= 1UL << d->irq); cached_irq_mask 41 arch/alpha/kernel/sys_dp264.c static unsigned long cached_irq_mask; cached_irq_mask 104 arch/alpha/kernel/sys_dp264.c cached_irq_mask |= 1UL << d->irq; cached_irq_mask 105 arch/alpha/kernel/sys_dp264.c tsunami_update_irq_hw(cached_irq_mask); cached_irq_mask 113 arch/alpha/kernel/sys_dp264.c cached_irq_mask &= ~(1UL << d->irq); cached_irq_mask 114 arch/alpha/kernel/sys_dp264.c tsunami_update_irq_hw(cached_irq_mask); cached_irq_mask 122 arch/alpha/kernel/sys_dp264.c cached_irq_mask |= 1UL << (d->irq - 16); cached_irq_mask 123 arch/alpha/kernel/sys_dp264.c tsunami_update_irq_hw(cached_irq_mask); cached_irq_mask 131 arch/alpha/kernel/sys_dp264.c cached_irq_mask &= ~(1UL << (d->irq - 16)); cached_irq_mask 132 arch/alpha/kernel/sys_dp264.c tsunami_update_irq_hw(cached_irq_mask); cached_irq_mask 157 arch/alpha/kernel/sys_dp264.c tsunami_update_irq_hw(cached_irq_mask); cached_irq_mask 169 arch/alpha/kernel/sys_dp264.c tsunami_update_irq_hw(cached_irq_mask); cached_irq_mask 38 arch/alpha/kernel/sys_eb64p.c static unsigned int cached_irq_mask = -1; cached_irq_mask 49 arch/alpha/kernel/sys_eb64p.c eb64p_update_irq_hw(d->irq, cached_irq_mask &= ~(1 << d->irq)); cached_irq_mask 55 arch/alpha/kernel/sys_eb64p.c eb64p_update_irq_hw(d->irq, cached_irq_mask |= 1 << d->irq); cached_irq_mask 40 arch/alpha/kernel/sys_eiger.c static unsigned long cached_irq_mask[2] = { -1, -1 }; cached_irq_mask 57 arch/alpha/kernel/sys_eiger.c mask = (cached_irq_mask[irq >= 64] &= ~(1UL << (irq & 63))); cached_irq_mask 66 arch/alpha/kernel/sys_eiger.c mask = (cached_irq_mask[irq >= 64] |= 1UL << (irq & 63)); cached_irq_mask 38 arch/alpha/kernel/sys_mikasa.c static int cached_irq_mask; cached_irq_mask 49 arch/alpha/kernel/sys_mikasa.c mikasa_update_irq_hw(cached_irq_mask |= 1 << (d->irq - 16)); cached_irq_mask 55 arch/alpha/kernel/sys_mikasa.c mikasa_update_irq_hw(cached_irq_mask &= ~(1 << (d->irq - 16))); cached_irq_mask 38 arch/alpha/kernel/sys_noritake.c static int cached_irq_mask; cached_irq_mask 54 arch/alpha/kernel/sys_noritake.c noritake_update_irq_hw(d->irq, cached_irq_mask |= 1 << (d->irq - 16)); cached_irq_mask 60 arch/alpha/kernel/sys_noritake.c noritake_update_irq_hw(d->irq, cached_irq_mask &= ~(1 << (d->irq - 16))); cached_irq_mask 36 arch/alpha/kernel/sys_rx164.c static unsigned long cached_irq_mask; cached_irq_mask 52 arch/alpha/kernel/sys_rx164.c rx164_update_irq_hw(cached_irq_mask |= 1UL << (d->irq - 16)); cached_irq_mask 58 arch/alpha/kernel/sys_rx164.c rx164_update_irq_hw(cached_irq_mask &= ~(1UL << (d->irq - 16))); cached_irq_mask 35 arch/alpha/kernel/sys_takara.c static unsigned long cached_irq_mask[2] = { -1, -1 }; cached_irq_mask 52 arch/alpha/kernel/sys_takara.c mask = (cached_irq_mask[irq >= 64] &= ~(1UL << (irq & 63))); cached_irq_mask 61 arch/alpha/kernel/sys_takara.c mask = (cached_irq_mask[irq >= 64] |= 1UL << (irq & 63)); cached_irq_mask 33 arch/alpha/kernel/sys_wildfire.c static unsigned long cached_irq_mask[WILDFIRE_NR_IRQS/(sizeof(long)*8)]; cached_irq_mask 60 arch/alpha/kernel/sys_wildfire.c *enable0 = cached_irq_mask[qbbno * WILDFIRE_PCA_PER_QBB + pcano]; cached_irq_mask 115 arch/alpha/kernel/sys_wildfire.c set_bit(irq, &cached_irq_mask); cached_irq_mask 129 arch/alpha/kernel/sys_wildfire.c clear_bit(irq, &cached_irq_mask); cached_irq_mask 143 arch/alpha/kernel/sys_wildfire.c clear_bit(irq, &cached_irq_mask); cached_irq_mask 8 arch/x86/include/asm/i8259.h extern unsigned int cached_irq_mask; cached_irq_mask 11 arch/x86/include/asm/i8259.h #define cached_master_mask (__byte(0, cached_irq_mask)) cached_irq_mask 12 arch/x86/include/asm/i8259.h #define cached_slave_mask (__byte(1, cached_irq_mask)) cached_irq_mask 45 arch/x86/kernel/i8259.c unsigned int cached_irq_mask = 0xffff; cached_irq_mask 64 arch/x86/kernel/i8259.c cached_irq_mask |= mask; cached_irq_mask 83 arch/x86/kernel/i8259.c cached_irq_mask &= mask; cached_irq_mask 172 arch/x86/kernel/i8259.c if (cached_irq_mask & irqmask) cached_irq_mask 174 arch/x86/kernel/i8259.c cached_irq_mask |= irqmask; cached_irq_mask 63 drivers/irqchip/irq-i8259.c static unsigned int cached_irq_mask = 0xffff; cached_irq_mask 65 drivers/irqchip/irq-i8259.c #define cached_master_mask (cached_irq_mask) cached_irq_mask 66 drivers/irqchip/irq-i8259.c #define cached_slave_mask (cached_irq_mask >> 8) cached_irq_mask 75 drivers/irqchip/irq-i8259.c cached_irq_mask |= mask; cached_irq_mask 90 drivers/irqchip/irq-i8259.c cached_irq_mask &= mask; cached_irq_mask 156 drivers/irqchip/irq-i8259.c if (cached_irq_mask & irqmask) cached_irq_mask 158 drivers/irqchip/irq-i8259.c cached_irq_mask |= irqmask; cached_irq_mask 23 drivers/irqchip/irq-xtensa-mx.c static DEFINE_PER_CPU(unsigned int, cached_irq_mask); cached_irq_mask 62 drivers/irqchip/irq-xtensa-mx.c __this_cpu_write(cached_irq_mask, cached_irq_mask 82 drivers/irqchip/irq-xtensa-mx.c mask = __this_cpu_read(cached_irq_mask) & ~mask; cached_irq_mask 83 drivers/irqchip/irq-xtensa-mx.c __this_cpu_write(cached_irq_mask, mask); cached_irq_mask 100 drivers/irqchip/irq-xtensa-mx.c mask |= __this_cpu_read(cached_irq_mask); cached_irq_mask 101 drivers/irqchip/irq-xtensa-mx.c __this_cpu_write(cached_irq_mask, mask); cached_irq_mask 21 drivers/irqchip/irq-xtensa-pic.c unsigned int cached_irq_mask; cached_irq_mask 46 drivers/irqchip/irq-xtensa-pic.c cached_irq_mask &= ~(1 << d->hwirq); cached_irq_mask 47 drivers/irqchip/irq-xtensa-pic.c xtensa_set_sr(cached_irq_mask, intenable); cached_irq_mask 52 drivers/irqchip/irq-xtensa-pic.c cached_irq_mask |= 1 << d->hwirq; cached_irq_mask 53 drivers/irqchip/irq-xtensa-pic.c xtensa_set_sr(cached_irq_mask, intenable);