cache_levels       51 arch/arm/kvm/coproc.c static u32 cache_levels;
cache_levels      951 arch/arm/kvm/coproc.c         ctype = (cache_levels >> (level * 3)) & 7;
cache_levels     1425 arch/arm/kvm/coproc.c 	asm volatile("mrc p15, 1, %0, c0, c0, 1" : "=r" (cache_levels));
cache_levels     1427 arch/arm/kvm/coproc.c 		if (((cache_levels >> (i*3)) & 7) == 0)
cache_levels     1430 arch/arm/kvm/coproc.c 	cache_levels &= (1 << (i*3))-1;
cache_levels      156 arch/arm64/kvm/sys_regs.c static u32 cache_levels;
cache_levels     2477 arch/arm64/kvm/sys_regs.c 	ctype = (cache_levels >> (level * 3)) & 7;
cache_levels     2777 arch/arm64/kvm/sys_regs.c 	cache_levels = clidr.val;
cache_levels     2779 arch/arm64/kvm/sys_regs.c 		if (((cache_levels >> (i*3)) & 7) == 0)
cache_levels     2782 arch/arm64/kvm/sys_regs.c 	cache_levels &= (1 << (i*3))-1;
cache_levels      993 arch/ia64/include/asm/pal.h static inline long ia64_pal_cache_summary(unsigned long *cache_levels,
cache_levels      998 arch/ia64/include/asm/pal.h 	if (cache_levels)
cache_levels      999 arch/ia64/include/asm/pal.h 		*cache_levels = iprv.v0;