cache_irq_mask    848 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c 	uint32_t cache_irq_mask;
cache_irq_mask    863 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c 	cache_irq_mask = intr->cache_irq_mask[reg_idx];
cache_irq_mask    864 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c 	if (cache_irq_mask & irq->irq_mask) {
cache_irq_mask    869 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c 		cache_irq_mask |= irq->irq_mask;
cache_irq_mask    873 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c 		DPU_REG_WRITE(&intr->hw, reg->en_off, cache_irq_mask);
cache_irq_mask    878 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c 		intr->cache_irq_mask[reg_idx] = cache_irq_mask;
cache_irq_mask    883 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c 			irq->irq_mask, cache_irq_mask);
cache_irq_mask    894 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c 	uint32_t cache_irq_mask;
cache_irq_mask    908 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c 	cache_irq_mask = intr->cache_irq_mask[reg_idx];
cache_irq_mask    909 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c 	if ((cache_irq_mask & irq->irq_mask) == 0) {
cache_irq_mask    914 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c 		cache_irq_mask &= ~irq->irq_mask;
cache_irq_mask    916 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c 		DPU_REG_WRITE(&intr->hw, reg->en_off, cache_irq_mask);
cache_irq_mask    923 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c 		intr->cache_irq_mask[reg_idx] = cache_irq_mask;
cache_irq_mask    927 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c 			irq->irq_mask, cache_irq_mask);
cache_irq_mask   1103 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c 	intr->cache_irq_mask = kcalloc(ARRAY_SIZE(dpu_intr_set), sizeof(u32),
cache_irq_mask   1105 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c 	if (intr->cache_irq_mask == NULL) {
cache_irq_mask   1113 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c 		kfree(intr->cache_irq_mask);
cache_irq_mask   1126 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c 		kfree(intr->cache_irq_mask);
cache_irq_mask    186 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h 	u32 *cache_irq_mask;