c5                290 arch/arm/include/asm/assembler.h 	mcr	p15, 0, r0, c7, c5, 4
c5                 68 arch/arm/include/asm/cp15.h #define BPIALL				__ACCESS_CP15(c7, 0, c5, 6)
c5                 69 arch/arm/include/asm/cp15.h #define ICIALLU				__ACCESS_CP15(c7, 0, c5, 0)
c5                 47 arch/arm/include/asm/hardware/cp14.h #define RCP14_DBGDTRRXint()		MRC14(0, c0, c5, 0)
c5                 62 arch/arm/include/asm/hardware/cp14.h #define RCP14_DBGBVR5()			MRC14(0, c0, c5, 4)
c5                 78 arch/arm/include/asm/hardware/cp14.h #define RCP14_DBGBCR5()			MRC14(0, c0, c5, 5)
c5                 94 arch/arm/include/asm/hardware/cp14.h #define RCP14_DBGWVR5()			MRC14(0, c0, c5, 6)
c5                110 arch/arm/include/asm/hardware/cp14.h #define RCP14_DBGWCR5()			MRC14(0, c0, c5, 7)
c5                127 arch/arm/include/asm/hardware/cp14.h #define RCP14_DBGBXVR5()		MRC14(0, c1, c5, 1)
c5                142 arch/arm/include/asm/hardware/cp14.h #define RCP14_DBGPRSR()			MRC14(0, c1, c5, 4)
c5                152 arch/arm/include/asm/hardware/cp14.h #define WCP14_DBGDTRTXint(val)		MCR14(val, 0, c0, c5, 0)
c5                167 arch/arm/include/asm/hardware/cp14.h #define WCP14_DBGBVR5(val)		MCR14(val, 0, c0, c5, 4)
c5                183 arch/arm/include/asm/hardware/cp14.h #define WCP14_DBGBCR5(val)		MCR14(val, 0, c0, c5, 5)
c5                199 arch/arm/include/asm/hardware/cp14.h #define WCP14_DBGWVR5(val)		MCR14(val, 0, c0, c5, 6)
c5                215 arch/arm/include/asm/hardware/cp14.h #define WCP14_DBGWCR5(val)		MCR14(val, 0, c0, c5, 7)
c5                231 arch/arm/include/asm/hardware/cp14.h #define WCP14_DBGBXVR5(val)		MCR14(val, 0, c1, c5, 1)
c5                278 arch/arm/include/asm/hardware/cp14.h #define RCP14_ETMSCR()			MRC14(1, c0, c5, 0)
c5                294 arch/arm/include/asm/hardware/cp14.h #define RCP14_ETMACVR5()		MRC14(1, c0, c5, 1)
c5                310 arch/arm/include/asm/hardware/cp14.h #define RCP14_ETMACTR5()		MRC14(1, c0, c5, 2)
c5                342 arch/arm/include/asm/hardware/cp14.h #define RCP14_ETMCNTENR1()		MRC14(1, c0, c5, 5)
c5                358 arch/arm/include/asm/hardware/cp14.h #define RCP14_ETMSQ13EVR()		MRC14(1, c0, c5, 6)
c5                373 arch/arm/include/asm/hardware/cp14.h #define RCP14_ETMIMPSPEC5()		MRC14(1, c0, c5, 7)
c5                391 arch/arm/include/asm/hardware/cp14.h #define RCP14_ETMPDSR()			MRC14(1, c1, c5, 4)
c5                400 arch/arm/include/asm/hardware/cp14.h #define RCP14_ETMPIDR5()		MRC14(1, c7, c5, 7)
c5                431 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMACVR5(val)		MCR14(val, 1, c0, c5, 1)
c5                447 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMACTR5(val)		MCR14(val, 1, c0, c5, 2)
c5                479 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMCNTENR1(val)		MCR14(val, 1, c0, c5, 5)
c5                495 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMSQ13EVR(val)		MCR14(val, 1, c0, c5, 6)
c5                510 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMIMPSPEC5(val)		MCR14(val, 1, c0, c5, 7)
c5                527 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMPDSR(val)		MCR14(val, 1, c1, c5, 4)
c5                 50 arch/arm/include/asm/kvm_hyp.h #define DFSR		__ACCESS_CP15(c5, 0, c0, 0)
c5                 51 arch/arm/include/asm/kvm_hyp.h #define IFSR		__ACCESS_CP15(c5, 0, c0, 1)
c5                 52 arch/arm/include/asm/kvm_hyp.h #define ADFSR		__ACCESS_CP15(c5, 0, c1, 0)
c5                 53 arch/arm/include/asm/kvm_hyp.h #define AIFSR		__ACCESS_CP15(c5, 0, c1, 1)
c5                 54 arch/arm/include/asm/kvm_hyp.h #define HSR		__ACCESS_CP15(c5, 4, c2, 0)
c5                 62 arch/arm/include/asm/kvm_hyp.h #define ICIMVAU		__ACCESS_CP15(c7, 0, c5, 1)
c5                945 arch/arm/kernel/hw_breakpoint.c 		ARM_DBG_READ(c1, c5, 4, val);
c5                 75 drivers/gpu/drm/nouveau/nvkm/subdev/volt/gk20a.c 		DIV_ROUND_CLOSEST(coef->c5 * temp, t_scale);
c5                 32 drivers/gpu/drm/nouveau/nvkm/subdev/volt/gk20a.h 	int c5;
c5                110 drivers/gpu/drm/vc4/vc4_hvs.c #define VC4_LINEAR_PHASE_KERNEL(c0, c1, c2, c3, c4, c5, c6, c7, c8,	\
c5                113 drivers/gpu/drm/vc4/vc4_hvs.c 	 VC4_PPF_FILTER_WORD(c3, c4, c5),				\
c5                 35 tools/perf/arch/s390/include/dwarf-regs-table.h 	REG_DWARFNUM_NAME(c5, 37),