c4                 21 arch/arm/include/asm/arch_gicv3.h #define ICC_PMR				__ACCESS_CP15(c4, 0, c6, 0)
c4                 56 arch/arm/include/asm/hardware/cp14.h #define RCP14_DBGDRCR()			MRC14(0, c0, c4, 2)
c4                 61 arch/arm/include/asm/hardware/cp14.h #define RCP14_DBGBVR4()			MRC14(0, c0, c4, 4)
c4                 77 arch/arm/include/asm/hardware/cp14.h #define RCP14_DBGBCR4()			MRC14(0, c0, c4, 5)
c4                 93 arch/arm/include/asm/hardware/cp14.h #define RCP14_DBGWVR4()			MRC14(0, c0, c4, 6)
c4                109 arch/arm/include/asm/hardware/cp14.h #define RCP14_DBGWCR4()			MRC14(0, c0, c4, 7)
c4                126 arch/arm/include/asm/hardware/cp14.h #define RCP14_DBGBXVR4()		MRC14(0, c1, c4, 1)
c4                141 arch/arm/include/asm/hardware/cp14.h #define RCP14_DBGPRCR()			MRC14(0, c1, c4, 4)
c4                161 arch/arm/include/asm/hardware/cp14.h #define WCP14_DBGDRCR(val)		MCR14(val, 0, c0, c4, 2)
c4                166 arch/arm/include/asm/hardware/cp14.h #define WCP14_DBGBVR4(val)		MCR14(val, 0, c0, c4, 4)
c4                182 arch/arm/include/asm/hardware/cp14.h #define WCP14_DBGBCR4(val)		MCR14(val, 0, c0, c4, 5)
c4                198 arch/arm/include/asm/hardware/cp14.h #define WCP14_DBGWVR4(val)		MCR14(val, 0, c0, c4, 6)
c4                214 arch/arm/include/asm/hardware/cp14.h #define WCP14_DBGWCR4(val)		MCR14(val, 0, c0, c4, 7)
c4                230 arch/arm/include/asm/hardware/cp14.h #define WCP14_DBGBXVR4(val)		MCR14(val, 0, c1, c4, 1)
c4                245 arch/arm/include/asm/hardware/cp14.h #define WCP14_DBGPRCR(val)		MCR14(val, 0, c1, c4, 4)
c4                277 arch/arm/include/asm/hardware/cp14.h #define RCP14_ETMSR()			MRC14(1, c0, c4, 0)
c4                293 arch/arm/include/asm/hardware/cp14.h #define RCP14_ETMACVR4()		MRC14(1, c0, c4, 1)
c4                309 arch/arm/include/asm/hardware/cp14.h #define RCP14_ETMACTR4()		MRC14(1, c0, c4, 2)
c4                323 arch/arm/include/asm/hardware/cp14.h #define RCP14_ETMDCVR4()		MRC14(1, c0, c4, 3)
c4                331 arch/arm/include/asm/hardware/cp14.h #define RCP14_ETMDCMR4()		MRC14(1, c0, c4, 4)
c4                341 arch/arm/include/asm/hardware/cp14.h #define RCP14_ETMCNTENR0()		MRC14(1, c0, c4, 5)
c4                357 arch/arm/include/asm/hardware/cp14.h #define RCP14_ETMSQ32EVR()		MRC14(1, c0, c4, 6)
c4                372 arch/arm/include/asm/hardware/cp14.h #define RCP14_ETMIMPSPEC4()		MRC14(1, c0, c4, 7)
c4                390 arch/arm/include/asm/hardware/cp14.h #define RCP14_ETMPDCR()			MRC14(1, c1, c4, 4)
c4                399 arch/arm/include/asm/hardware/cp14.h #define RCP14_ETMPIDR4()		MRC14(1, c7, c4, 7)
c4                415 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMSR(val)		MCR14(val, 1, c0, c4, 0)
c4                430 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMACVR4(val)		MCR14(val, 1, c0, c4, 1)
c4                446 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMACTR4(val)		MCR14(val, 1, c0, c4, 2)
c4                460 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMDCVR4(val)		MCR14(val, 1, c0, c4, 3)
c4                468 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMDCMR4(val)		MCR14(val, 1, c0, c4, 4)
c4                478 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMCNTENR0(val)		MCR14(val, 1, c0, c4, 5)
c4                494 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMSQ32EVR(val)		MCR14(val, 1, c0, c4, 6)
c4                509 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMIMPSPEC4(val)		MCR14(val, 1, c0, c4, 7)
c4                526 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMPDCR(val)		MCR14(val, 1, c1, c4, 4)
c4                 74 drivers/gpu/drm/nouveau/nvkm/subdev/volt/gk20a.c 	mv = DIV_ROUND_CLOSEST(coef->c3 * speedo, s_scale) + coef->c4 +
c4                 31 drivers/gpu/drm/nouveau/nvkm/subdev/volt/gk20a.h 	int c4;
c4                499 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c 	REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C4_MSB, csc_coeff.c4 >> 8, 6, 0);
c4                500 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c 	REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C4_LSB, csc_coeff.c4, 7, 0);
c4                281 drivers/gpu/drm/omapdrm/dss/hdmi5_core.h 	u16 c1, c2, c3, c4;
c4                110 drivers/gpu/drm/vc4/vc4_hvs.c #define VC4_LINEAR_PHASE_KERNEL(c0, c1, c2, c3, c4, c5, c6, c7, c8,	\
c4                113 drivers/gpu/drm/vc4/vc4_hvs.c 	 VC4_PPF_FILTER_WORD(c3, c4, c5),				\
c4                210 drivers/scsi/device_handler/scsi_dh_rdac.c 		struct c4_inquiry c4;
c4                441 drivers/scsi/device_handler/scsi_dh_rdac.c 	struct c4_inquiry *inqp = &h->inq.c4;
c4                491 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c 	REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C4_MSB, csc_coeff.c4 >> 8, 6, 0);
c4                492 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c 	REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C4_LSB, csc_coeff.c4, 7, 0);
c4                281 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.h 	u16 c1, c2, c3, c4;
c4                 27 include/uapi/linux/android/binder.h #define B_PACK_CHARS(c1, c2, c3, c4) \
c4                 28 include/uapi/linux/android/binder.h 	((((c1)<<24)) | (((c2)<<16)) | (((c3)<<8)) | (c4))
c4                 34 tools/perf/arch/s390/include/dwarf-regs-table.h 	REG_DWARFNUM_NAME(c4, 36),