c13 51 arch/arm/include/asm/arch_gicv3.h #define __LR8(x) __ACCESS_CP15(c12, 4, c13, x) c13 70 arch/arm/include/asm/hardware/cp14.h #define RCP14_DBGBVR13() MRC14(0, c0, c13, 4) c13 86 arch/arm/include/asm/hardware/cp14.h #define RCP14_DBGBCR13() MRC14(0, c0, c13, 5) c13 102 arch/arm/include/asm/hardware/cp14.h #define RCP14_DBGWVR13() MRC14(0, c0, c13, 6) c13 118 arch/arm/include/asm/hardware/cp14.h #define RCP14_DBGWCR13() MRC14(0, c0, c13, 7) c13 135 arch/arm/include/asm/hardware/cp14.h #define RCP14_DBGBXVR13() MRC14(0, c1, c13, 1) c13 175 arch/arm/include/asm/hardware/cp14.h #define WCP14_DBGBVR13(val) MCR14(val, 0, c0, c13, 4) c13 191 arch/arm/include/asm/hardware/cp14.h #define WCP14_DBGBCR13(val) MCR14(val, 0, c0, c13, 5) c13 207 arch/arm/include/asm/hardware/cp14.h #define WCP14_DBGWVR13(val) MCR14(val, 0, c0, c13, 6) c13 223 arch/arm/include/asm/hardware/cp14.h #define WCP14_DBGWCR13(val) MCR14(val, 0, c0, c13, 7) c13 239 arch/arm/include/asm/hardware/cp14.h #define WCP14_DBGBXVR13(val) MCR14(val, 0, c1, c13, 1) c13 286 arch/arm/include/asm/hardware/cp14.h #define RCP14_ETMVDCR1() MRC14(1, c0, c13, 0) c13 302 arch/arm/include/asm/hardware/cp14.h #define RCP14_ETMACVR13() MRC14(1, c0, c13, 1) c13 318 arch/arm/include/asm/hardware/cp14.h #define RCP14_ETMACTR13() MRC14(1, c0, c13, 2) c13 350 arch/arm/include/asm/hardware/cp14.h #define RCP14_ETMCNTVR1() MRC14(1, c0, c13, 5) c13 365 arch/arm/include/asm/hardware/cp14.h #define RCP14_ETMCIDCVR1() MRC14(1, c0, c13, 6) c13 381 arch/arm/include/asm/hardware/cp14.h #define RCP14_ETMEIBCR() MRC14(1, c0, c13, 7) c13 395 arch/arm/include/asm/hardware/cp14.h #define RCP14_ETMLSR() MRC14(1, c7, c13, 6) c13 408 arch/arm/include/asm/hardware/cp14.h #define RCP14_ETMCIDR1() MRC14(1, c7, c13, 7) c13 423 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMVDCR1(val) MCR14(val, 1, c0, c13, 0) c13 439 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMACVR13(val) MCR14(val, 1, c0, c13, 1) c13 455 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMACTR13(val) MCR14(val, 1, c0, c13, 2) c13 487 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMCNTVR1(val) MCR14(val, 1, c0, c13, 5) c13 502 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMCIDCVR1(val) MCR14(val, 1, c0, c13, 6) c13 517 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMEIBCR(val) MCR14(val, 1, c0, c13, 7) c13 72 arch/arm/include/asm/kvm_hyp.h #define CID __ACCESS_CP15(c13, 0, c0, 1) c13 73 arch/arm/include/asm/kvm_hyp.h #define TID_URW __ACCESS_CP15(c13, 0, c0, 2) c13 74 arch/arm/include/asm/kvm_hyp.h #define TID_URO __ACCESS_CP15(c13, 0, c0, 3) c13 75 arch/arm/include/asm/kvm_hyp.h #define TID_PRIV __ACCESS_CP15(c13, 0, c0, 4) c13 76 arch/arm/include/asm/kvm_hyp.h #define HTPIDR __ACCESS_CP15(c13, 4, c0, 2) c13 14 arch/arm/include/asm/tls.h mrc p15, 0, \tmp2, c13, c0, 2 @ get the user r/w register c13 15 arch/arm/include/asm/tls.h mcr p15, 0, \tp, c13, c0, 3 @ set TLS register c13 16 arch/arm/include/asm/tls.h mcr p15, 0, \tpuser, c13, c0, 2 @ and the user r/w register c13 26 arch/arm/include/asm/tls.h mrcne p15, 0, \tmp2, c13, c0, 2 @ get the user r/w register c13 27 arch/arm/include/asm/tls.h mcrne p15, 0, \tp, c13, c0, 3 @ yes, set TLS register c13 28 arch/arm/include/asm/tls.h mcrne p15, 0, \tpuser, c13, c0, 2 @ set user r/w register c13 400 arch/arm64/include/asm/assembler.h sys 3, c7, c13, 1, \kaddr // dc cvadp c13 111 drivers/gpu/drm/vc4/vc4_hvs.c c9, c10, c11, c12, c13, c14, c15) \ c13 116 drivers/gpu/drm/vc4/vc4_hvs.c VC4_PPF_FILTER_WORD(c12, c13, c14), \ c13 1834 drivers/staging/media/ipu3/include/intel-ipu3.h __u32 c13:2; c13 43 tools/perf/arch/s390/include/dwarf-regs-table.h REG_DWARFNUM_NAME(c13, 45),