c12 17 arch/arm/include/asm/arch_gicv3.h #define ICC_EOIR1 __ACCESS_CP15(c12, 0, c12, 1) c12 18 arch/arm/include/asm/arch_gicv3.h #define ICC_DIR __ACCESS_CP15(c12, 0, c11, 1) c12 19 arch/arm/include/asm/arch_gicv3.h #define ICC_IAR1 __ACCESS_CP15(c12, 0, c12, 0) c12 20 arch/arm/include/asm/arch_gicv3.h #define ICC_SGI1R __ACCESS_CP15_64(0, c12) c12 22 arch/arm/include/asm/arch_gicv3.h #define ICC_CTLR __ACCESS_CP15(c12, 0, c12, 4) c12 23 arch/arm/include/asm/arch_gicv3.h #define ICC_SRE __ACCESS_CP15(c12, 0, c12, 5) c12 24 arch/arm/include/asm/arch_gicv3.h #define ICC_IGRPEN1 __ACCESS_CP15(c12, 0, c12, 7) c12 25 arch/arm/include/asm/arch_gicv3.h #define ICC_BPR1 __ACCESS_CP15(c12, 0, c12, 3) c12 26 arch/arm/include/asm/arch_gicv3.h #define ICC_RPR __ACCESS_CP15(c12, 0, c11, 3) c12 28 arch/arm/include/asm/arch_gicv3.h #define __ICC_AP0Rx(x) __ACCESS_CP15(c12, 0, c8, 4 | x) c12 34 arch/arm/include/asm/arch_gicv3.h #define __ICC_AP1Rx(x) __ACCESS_CP15(c12, 0, c9, x) c12 40 arch/arm/include/asm/arch_gicv3.h #define ICC_HSRE __ACCESS_CP15(c12, 4, c9, 5) c12 42 arch/arm/include/asm/arch_gicv3.h #define ICH_VSEIR __ACCESS_CP15(c12, 4, c9, 4) c12 43 arch/arm/include/asm/arch_gicv3.h #define ICH_HCR __ACCESS_CP15(c12, 4, c11, 0) c12 44 arch/arm/include/asm/arch_gicv3.h #define ICH_VTR __ACCESS_CP15(c12, 4, c11, 1) c12 45 arch/arm/include/asm/arch_gicv3.h #define ICH_MISR __ACCESS_CP15(c12, 4, c11, 2) c12 46 arch/arm/include/asm/arch_gicv3.h #define ICH_EISR __ACCESS_CP15(c12, 4, c11, 3) c12 47 arch/arm/include/asm/arch_gicv3.h #define ICH_ELRSR __ACCESS_CP15(c12, 4, c11, 5) c12 48 arch/arm/include/asm/arch_gicv3.h #define ICH_VMCR __ACCESS_CP15(c12, 4, c11, 7) c12 50 arch/arm/include/asm/arch_gicv3.h #define __LR0(x) __ACCESS_CP15(c12, 4, c12, x) c12 51 arch/arm/include/asm/arch_gicv3.h #define __LR8(x) __ACCESS_CP15(c12, 4, c13, x) c12 71 arch/arm/include/asm/arch_gicv3.h #define __LRC0(x) __ACCESS_CP15(c12, 4, c14, x) c12 72 arch/arm/include/asm/arch_gicv3.h #define __LRC8(x) __ACCESS_CP15(c12, 4, c15, x) c12 91 arch/arm/include/asm/arch_gicv3.h #define __ICH_AP0Rx(x) __ACCESS_CP15(c12, 4, c8, x) c12 97 arch/arm/include/asm/arch_gicv3.h #define __ICH_AP1Rx(x) __ACCESS_CP15(c12, 4, c9, x) c12 69 arch/arm/include/asm/hardware/cp14.h #define RCP14_DBGBVR12() MRC14(0, c0, c12, 4) c12 85 arch/arm/include/asm/hardware/cp14.h #define RCP14_DBGBCR12() MRC14(0, c0, c12, 5) c12 101 arch/arm/include/asm/hardware/cp14.h #define RCP14_DBGWVR12() MRC14(0, c0, c12, 6) c12 117 arch/arm/include/asm/hardware/cp14.h #define RCP14_DBGWCR12() MRC14(0, c0, c12, 7) c12 134 arch/arm/include/asm/hardware/cp14.h #define RCP14_DBGBXVR12() MRC14(0, c1, c12, 1) c12 174 arch/arm/include/asm/hardware/cp14.h #define WCP14_DBGBVR12(val) MCR14(val, 0, c0, c12, 4) c12 190 arch/arm/include/asm/hardware/cp14.h #define WCP14_DBGBCR12(val) MCR14(val, 0, c0, c12, 5) c12 206 arch/arm/include/asm/hardware/cp14.h #define WCP14_DBGWVR12(val) MCR14(val, 0, c0, c12, 6) c12 222 arch/arm/include/asm/hardware/cp14.h #define WCP14_DBGWCR12(val) MCR14(val, 0, c0, c12, 7) c12 238 arch/arm/include/asm/hardware/cp14.h #define WCP14_DBGBXVR12(val) MCR14(val, 0, c1, c12, 1) c12 285 arch/arm/include/asm/hardware/cp14.h #define RCP14_ETMVDEVR() MRC14(1, c0, c12, 0) c12 301 arch/arm/include/asm/hardware/cp14.h #define RCP14_ETMACVR12() MRC14(1, c0, c12, 1) c12 317 arch/arm/include/asm/hardware/cp14.h #define RCP14_ETMACTR12() MRC14(1, c0, c12, 2) c12 327 arch/arm/include/asm/hardware/cp14.h #define RCP14_ETMDCVR12() MRC14(1, c0, c12, 3) c12 335 arch/arm/include/asm/hardware/cp14.h #define RCP14_ETMDCMR12() MRC14(1, c0, c12, 4) c12 349 arch/arm/include/asm/hardware/cp14.h #define RCP14_ETMCNTVR0() MRC14(1, c0, c12, 5) c12 364 arch/arm/include/asm/hardware/cp14.h #define RCP14_ETMCIDCVR0() MRC14(1, c0, c12, 6) c12 380 arch/arm/include/asm/hardware/cp14.h #define RCP14_ETMTESSEICR() MRC14(1, c0, c12, 7) c12 407 arch/arm/include/asm/hardware/cp14.h #define RCP14_ETMCIDR0() MRC14(1, c7, c12, 7) c12 422 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMVDEVR(val) MCR14(val, 1, c0, c12, 0) c12 438 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMACVR12(val) MCR14(val, 1, c0, c12, 1) c12 454 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMACTR12(val) MCR14(val, 1, c0, c12, 2) c12 464 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMDCVR12(val) MCR14(val, 1, c0, c12, 3) c12 472 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMDCMR12(val) MCR14(val, 1, c0, c12, 4) c12 486 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMCNTVR0(val) MCR14(val, 1, c0, c12, 5) c12 501 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMCIDCVR0(val) MCR14(val, 1, c0, c12, 6) c12 516 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMTESSEICR(val) MCR14(val, 1, c0, c12, 7) c12 532 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMLAR(val) MCR14(val, 1, c7, c12, 6) c12 71 arch/arm/include/asm/kvm_hyp.h #define VBAR __ACCESS_CP15(c12, 0, c0, 0) c12 397 arch/arm64/include/asm/assembler.h sys 3, c7, c12, 1, \kaddr // dc cvap c12 111 drivers/gpu/drm/vc4/vc4_hvs.c c9, c10, c11, c12, c13, c14, c15) \ c12 116 drivers/gpu/drm/vc4/vc4_hvs.c VC4_PPF_FILTER_WORD(c12, c13, c14), \ c12 29 drivers/iio/pressure/mpl115.c s16 c12; c12 68 drivers/iio/pressure/mpl115.c a1 = data->b1 + ((data->c12 * tadc) >> 11); c12 187 drivers/iio/pressure/mpl115.c data->c12 = ret; c12 1583 drivers/staging/media/ipu3/include/intel-ipu3.h __u32 c12:9; c12 1833 drivers/staging/media/ipu3/include/intel-ipu3.h __u32 c12:2; c12 42 tools/perf/arch/s390/include/dwarf-regs-table.h REG_DWARFNUM_NAME(c12, 44),