c10 306 arch/arm/include/asm/assembler.h ALT_SMP(mcr p15, 0, r0, c7, c10, 5) @ dmb c10 51 arch/arm/include/asm/hardware/cp14.h #define RCP14_DBGDSCCR() MRC14(0, c0, c10, 0) c10 67 arch/arm/include/asm/hardware/cp14.h #define RCP14_DBGBVR10() MRC14(0, c0, c10, 4) c10 83 arch/arm/include/asm/hardware/cp14.h #define RCP14_DBGBCR10() MRC14(0, c0, c10, 5) c10 99 arch/arm/include/asm/hardware/cp14.h #define RCP14_DBGWVR10() MRC14(0, c0, c10, 6) c10 115 arch/arm/include/asm/hardware/cp14.h #define RCP14_DBGWCR10() MRC14(0, c0, c10, 7) c10 132 arch/arm/include/asm/hardware/cp14.h #define RCP14_DBGBXVR10() MRC14(0, c1, c10, 1) c10 156 arch/arm/include/asm/hardware/cp14.h #define WCP14_DBGDSCCR(val) MCR14(val, 0, c0, c10, 0) c10 172 arch/arm/include/asm/hardware/cp14.h #define WCP14_DBGBVR10(val) MCR14(val, 0, c0, c10, 4) c10 188 arch/arm/include/asm/hardware/cp14.h #define WCP14_DBGBCR10(val) MCR14(val, 0, c0, c10, 5) c10 204 arch/arm/include/asm/hardware/cp14.h #define WCP14_DBGWVR10(val) MCR14(val, 0, c0, c10, 6) c10 220 arch/arm/include/asm/hardware/cp14.h #define WCP14_DBGWCR10(val) MCR14(val, 0, c0, c10, 7) c10 236 arch/arm/include/asm/hardware/cp14.h #define WCP14_DBGBXVR10(val) MCR14(val, 0, c1, c10, 1) c10 283 arch/arm/include/asm/hardware/cp14.h #define RCP14_ETMFFRR() MRC14(1, c0, c10, 0) c10 299 arch/arm/include/asm/hardware/cp14.h #define RCP14_ETMACVR10() MRC14(1, c0, c10, 1) c10 315 arch/arm/include/asm/hardware/cp14.h #define RCP14_ETMACTR10() MRC14(1, c0, c10, 2) c10 326 arch/arm/include/asm/hardware/cp14.h #define RCP14_ETMDCVR10() MRC14(1, c0, c10, 3) c10 334 arch/arm/include/asm/hardware/cp14.h #define RCP14_ETMDCMR10() MRC14(1, c0, c10, 4) c10 347 arch/arm/include/asm/hardware/cp14.h #define RCP14_ETMCNTRLDEVR2() MRC14(1, c0, c10, 5) c10 362 arch/arm/include/asm/hardware/cp14.h #define RCP14_ETMEXTOUTEVR2() MRC14(1, c0, c10, 6) c10 378 arch/arm/include/asm/hardware/cp14.h #define RCP14_ETMCCER() MRC14(1, c0, c10, 7) c10 405 arch/arm/include/asm/hardware/cp14.h #define RCP14_ETMPIDR2() MRC14(1, c7, c10, 7) c10 420 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMFFRR(val) MCR14(val, 1, c0, c10, 0) c10 436 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMACVR10(val) MCR14(val, 1, c0, c10, 1) c10 452 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMACTR10(val) MCR14(val, 1, c0, c10, 2) c10 463 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMDCVR10(val) MCR14(val, 1, c0, c10, 3) c10 471 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMDCMR10(val) MCR14(val, 1, c0, c10, 4) c10 484 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMCNTRLDEVR2(val) MCR14(val, 1, c0, c10, 5) c10 499 arch/arm/include/asm/hardware/cp14.h #define WCP14_ETMEXTOUTEVR2(val) MCR14(val, 1, c0, c10, 6) c10 67 arch/arm/include/asm/kvm_hyp.h #define PRRR __ACCESS_CP15(c10, 0, c2, 0) c10 68 arch/arm/include/asm/kvm_hyp.h #define NMRR __ACCESS_CP15(c10, 0, c2, 1) c10 69 arch/arm/include/asm/kvm_hyp.h #define AMAIR0 __ACCESS_CP15(c10, 0, c3, 0) c10 70 arch/arm/include/asm/kvm_hyp.h #define AMAIR1 __ACCESS_CP15(c10, 0, c3, 1) c10 244 arch/x86/events/intel/cstate.c PMU_EVENT_ATTR_STRING(c10-residency, attr_cstate_pkg_c10, "event=0x06"); c10 111 drivers/gpu/drm/vc4/vc4_hvs.c c9, c10, c11, c12, c13, c14, c15) \ c10 115 drivers/gpu/drm/vc4/vc4_hvs.c VC4_PPF_FILTER_WORD(c9, c10, c11), \ c10 89 drivers/iio/pressure/dps310.c s32 c00, c10, c20, c30, c01, c11, c21; c10 115 drivers/iio/pressure/dps310.c u32 c00, c10, c20, c30, c01, c11, c21; c10 141 drivers/iio/pressure/dps310.c c10 = ((coef[5] & GENMASK(3, 0)) << 16) | (coef[6] << 8) | coef[7]; c10 142 drivers/iio/pressure/dps310.c data->c10 = sign_extend32(c10, 19); c10 506 drivers/iio/pressure/dps310.c nums[1] = p * (s64)data->c10; c10 1831 drivers/staging/media/ipu3/include/intel-ipu3.h __u32 c10:2; c10 40 tools/perf/arch/s390/include/dwarf-regs-table.h REG_DWARFNUM_NAME(c10, 42),