bws                55 drivers/clk/ti/clk-dra7-atl.c 	u32 bws;		/* Baseband Word Select Mux */
bws               274 drivers/clk/ti/clk-dra7-atl.c 						   &cdesc->bws);
bws               280 drivers/clk/ti/clk-dra7-atl.c 					  cdesc->bws);
bws               904 drivers/gpu/drm/gma500/cdv_intel_dp.c 	static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
bws               916 drivers/gpu/drm/gma500/cdv_intel_dp.c 			int link_avail = cdv_intel_dp_max_data_rate(cdv_intel_dp_link_clock(bws[clock]), lane_count);
bws               919 drivers/gpu/drm/gma500/cdv_intel_dp.c 				intel_dp->link_bw = bws[clock];
bws               933 drivers/gpu/drm/gma500/cdv_intel_dp.c 		intel_dp->link_bw = bws[max_clock];