bw_params 414 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c void build_watermark_ranges(struct clk_bw_params *bw_params, struct pp_smu_wm_range_sets *ranges) bw_params 422 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c if (!bw_params->wm_table.entries[i].valid) bw_params 425 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c ranges->reader_wm_sets[num_valid_sets].wm_inst = bw_params->wm_table.entries[i].wm_inst; bw_params 426 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c ranges->reader_wm_sets[num_valid_sets].wm_type = bw_params->wm_table.entries[i].wm_type;; bw_params 437 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c ranges->reader_wm_sets[num_valid_sets].min_fill_clk_mhz = bw_params->clk_table.entries[i - 1].fclk_mhz + 1; bw_params 439 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c ranges->reader_wm_sets[num_valid_sets].max_fill_clk_mhz = bw_params->clk_table.entries[i].fclk_mhz; bw_params 471 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c void clk_mgr_helper_populate_bw_params(struct clk_bw_params *bw_params, struct dpm_clocks *clock_table, struct hw_asic_id *asic_id) bw_params 481 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c bw_params->clk_table.entries[i].dcfclk_mhz = clock_table->DcfClocks[i].Freq; bw_params 482 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c bw_params->clk_table.entries[i].fclk_mhz = clock_table->FClocks[i].Freq; bw_params 483 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c bw_params->clk_table.entries[i].memclk_mhz = clock_table->MemClocks[i].Freq; bw_params 484 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c bw_params->clk_table.entries[i].socclk_mhz = clock_table->SocClocks[i].Freq; bw_params 485 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c bw_params->clk_table.entries[i].voltage = clock_table->FClocks[i].Vol; bw_params 487 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c bw_params->clk_table.num_entries = i; bw_params 489 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c bw_params->vram_type = asic_id->vram_type; bw_params 490 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c bw_params->num_channels = asic_id->vram_width / DDR4_DRAM_WIDTH; bw_params 493 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c bw_params->wm_table.entries[i].wm_inst = i; bw_params 496 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c bw_params->wm_table.entries[i].valid = false; bw_params 500 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c bw_params->wm_table.entries[i].wm_type = WM_TYPE_PSTATE_CHG; bw_params 501 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c bw_params->wm_table.entries[i].valid = true; bw_params 504 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c if (bw_params->vram_type == LpDdr4MemType) { bw_params 508 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c bw_params->wm_table.entries[WM_D].pstate_latency_us = LPDDR_MEM_RETRAIN_LATENCY; bw_params 509 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c bw_params->wm_table.entries[WM_D].wm_inst = WM_D; bw_params 510 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c bw_params->wm_table.entries[WM_D].wm_type = WM_TYPE_RETRAINING; bw_params 511 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c bw_params->wm_table.entries[WM_D].valid = true; bw_params 570 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c clk_mgr->base.bw_params = &rn_bw_params; bw_params 574 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c clk_mgr_helper_populate_bw_params(clk_mgr->base.bw_params, &clock_table, &ctx->asic_id); bw_params 585 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c build_watermark_ranges(clk_mgr->base.bw_params, &ranges); bw_params 700 drivers/gpu/drm/amd/display/dc/core/dc.c dc->res_pool->funcs->update_bw_bounding_box(dc, dc->clk_mgr->bw_params); bw_params 989 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c struct clk_bw_params *bw_params = dc->clk_mgr->bw_params; bw_params 991 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c ASSERT(bw_params); bw_params 1032 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c vlevel_max = bw_params->clk_table.num_entries - 1; bw_params 1036 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c table_entry = &bw_params->wm_table.entries[WM_D]; bw_params 1044 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c table_entry = &bw_params->wm_table.entries[WM_C]; bw_params 1049 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c table_entry = &bw_params->wm_table.entries[WM_B]; bw_params 1055 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c table_entry = &bw_params->wm_table.entries[WM_A]; bw_params 1274 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c static void update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) bw_params 1277 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c struct clk_limit_table *clk_table = &bw_params->clk_table; bw_params 1282 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c dcn2_1_soc.num_chans = bw_params->num_channels; bw_params 151 drivers/gpu/drm/amd/display/dc/inc/core_types.h struct clk_bw_params *bw_params); bw_params 191 drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h struct clk_bw_params *bw_params; bw_params 411 drivers/media/dvb-frontends/rtl2832.c static u8 bw_params[3][32] = { bw_params 477 drivers/media/dvb-frontends/rtl2832.c for (j = 0; j < sizeof(bw_params[0]); j++) { bw_params 479 drivers/media/dvb-frontends/rtl2832.c 0x11c + j, &bw_params[i][j], 1); bw_params 36 drivers/media/tuners/tda18212.c static const u8 bw_params[][3] = { bw_params 115 drivers/media/tuners/tda18212.c ret = regmap_write(dev->regmap, 0x23, bw_params[i][2]); bw_params 123 drivers/media/tuners/tda18212.c ret = regmap_write(dev->regmap, 0x0f, bw_params[i][0]); bw_params 128 drivers/media/tuners/tda18212.c buf[1] = bw_params[i][1]; bw_params 592 drivers/net/ethernet/broadcom/bnx2x/bnx2x_dcb.c ets_params.cos[i].params.bw_params.bw = bw_params 906 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c if (!ets_params->cos[cos_idx].params.bw_params.bw) { bw_params 912 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c ets_params->cos[cos_idx].params.bw_params.bw bw_params 916 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c ets_params->cos[cos_idx].params.bw_params.bw; bw_params 1185 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c ets_params->cos[cos_entry].params.bw_params.bw, bw_params 506 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.h struct bnx2x_ets_bw_params bw_params;