bstatus           164 drivers/crypto/cavium/cpt/cpt_hw_types.h 		u64 bstatus:30;
bstatus           166 drivers/crypto/cavium/cpt/cpt_hw_types.h 		u64 bstatus:30;
bstatus           226 drivers/crypto/cavium/cpt/cpt_hw_types.h 		u64 bstatus:48;
bstatus           228 drivers/crypto/cavium/cpt/cpt_hw_types.h 		u64 bstatus:48;
bstatus           436 drivers/crypto/cavium/zip/zip_regs.h 		u64 bstatus                     : 53;
bstatus           438 drivers/crypto/cavium/zip/zip_regs.h 		u64 bstatus                     : 53;
bstatus           465 drivers/crypto/cavium/zip/zip_regs.h 		u64 bstatus                     : 9;
bstatus           467 drivers/crypto/cavium/zip/zip_regs.h 		u64 bstatus                     : 9;
bstatus           281 drivers/gpu/drm/i915/display/intel_display_types.h 			    u8 *bstatus);
bstatus          5667 drivers/gpu/drm/i915/display/intel_dp.c 				      u8 *bstatus)
bstatus          5676 drivers/gpu/drm/i915/display/intel_dp.c 			       bstatus, DRM_HDCP_BSTATUS_LEN);
bstatus          5734 drivers/gpu/drm/i915/display/intel_dp.c 	u8 bstatus;
bstatus          5736 drivers/gpu/drm/i915/display/intel_dp.c 			       &bstatus, 1);
bstatus          5741 drivers/gpu/drm/i915/display/intel_dp.c 	*ksv_ready = bstatus & DP_BSTATUS_READY;
bstatus          5799 drivers/gpu/drm/i915/display/intel_dp.c 	u8 bstatus;
bstatus          5802 drivers/gpu/drm/i915/display/intel_dp.c 			       &bstatus, 1);
bstatus          5808 drivers/gpu/drm/i915/display/intel_dp.c 	return !(bstatus & (DP_BSTATUS_LINK_FAILURE | DP_BSTATUS_REAUTH_REQ));
bstatus           280 drivers/gpu/drm/i915/display/intel_hdcp.c 				u8 *ksv_fifo, u8 num_downstream, u8 *bstatus)
bstatus           361 drivers/gpu/drm/i915/display/intel_hdcp.c 					   bstatus[0] << 8 | bstatus[1]);
bstatus           383 drivers/gpu/drm/i915/display/intel_hdcp.c 		sha_text |= bstatus[0] << 16 | bstatus[1] << 8;
bstatus           408 drivers/gpu/drm/i915/display/intel_hdcp.c 		sha_text |= bstatus[0] << 24 | bstatus[1] << 16;
bstatus           425 drivers/gpu/drm/i915/display/intel_hdcp.c 		sha_text |= bstatus[0] << 24;
bstatus           433 drivers/gpu/drm/i915/display/intel_hdcp.c 		ret = intel_write_sha_text(dev_priv, bstatus[1]);
bstatus           498 drivers/gpu/drm/i915/display/intel_hdcp.c 	u8 bstatus[2], num_downstream, *ksv_fifo;
bstatus           507 drivers/gpu/drm/i915/display/intel_hdcp.c 	ret = shim->read_bstatus(intel_dig_port, bstatus);
bstatus           511 drivers/gpu/drm/i915/display/intel_hdcp.c 	if (DRM_HDCP_MAX_DEVICE_EXCEEDED(bstatus[0]) ||
bstatus           512 drivers/gpu/drm/i915/display/intel_hdcp.c 	    DRM_HDCP_MAX_CASCADE_EXCEEDED(bstatus[1])) {
bstatus           524 drivers/gpu/drm/i915/display/intel_hdcp.c 	num_downstream = DRM_HDCP_NUM_DOWNSTREAM(bstatus[0]);
bstatus           553 drivers/gpu/drm/i915/display/intel_hdcp.c 						  bstatus);
bstatus          1345 drivers/gpu/drm/i915/display/intel_hdmi.c 				 u8 *bstatus)
bstatus          1349 drivers/gpu/drm/i915/display/intel_hdmi.c 				   bstatus, DRM_HDCP_BSTATUS_LEN);
bstatus           870 drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c 	u16 bstatus;
bstatus           879 drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c 	*pbstatus = bstatus = (buf[1] << 8) | buf[0];
bstatus           882 drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c 	down_stream_devices = bstatus & 0x7F;
bstatus           883 drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c 	repeater_cascade_depth = (bstatus >> 8) & 0x7;
bstatus           884 drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c 	max_devs_exceeded = (bstatus & BIT(7)) ? true : false;
bstatus           885 drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c 	max_cascade_exceeded = (bstatus & BIT(11)) ? true : false;
bstatus           937 drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c 	u16 bstatus;
bstatus           967 drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c 	rc = msm_hdmi_hdcp_recv_check_bstatus(hdcp_ctrl, &bstatus);
bstatus           975 drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c 	data = bcaps | (bstatus << 8);