bridge_base        16 arch/arm/plat-orion/include/plat/time.h void orion_time_init(void __iomem *bridge_base, u32 bridge_timer1_clr_mask,
bridge_base        49 arch/arm/plat-orion/time.c static void __iomem *bridge_base;
bridge_base        87 arch/arm/plat-orion/time.c 	writel(bridge_timer1_clr_mask, bridge_base + BRIDGE_CAUSE_OFF);
bridge_base        89 arch/arm/plat-orion/time.c 	u = readl(bridge_base + BRIDGE_MASK_OFF);
bridge_base        91 arch/arm/plat-orion/time.c 	writel(u, bridge_base + BRIDGE_MASK_OFF);
bridge_base       122 arch/arm/plat-orion/time.c 	u = readl(bridge_base + BRIDGE_MASK_OFF);
bridge_base       123 arch/arm/plat-orion/time.c 	writel(u & ~BRIDGE_INT_TIMER1, bridge_base + BRIDGE_MASK_OFF);
bridge_base       126 arch/arm/plat-orion/time.c 	writel(bridge_timer1_clr_mask, bridge_base + BRIDGE_CAUSE_OFF);
bridge_base       145 arch/arm/plat-orion/time.c 	u = readl(bridge_base + BRIDGE_MASK_OFF);
bridge_base       146 arch/arm/plat-orion/time.c 	writel(u | BRIDGE_INT_TIMER1, bridge_base + BRIDGE_MASK_OFF);
bridge_base       174 arch/arm/plat-orion/time.c 	writel(bridge_timer1_clr_mask, bridge_base + BRIDGE_CAUSE_OFF);
bridge_base       210 arch/arm/plat-orion/time.c 	bridge_base = _bridge_base;
bridge_base       229 arch/arm/plat-orion/time.c 	u = readl(bridge_base + BRIDGE_MASK_OFF);
bridge_base       230 arch/arm/plat-orion/time.c 	writel(u & ~BRIDGE_INT_TIMER0, bridge_base + BRIDGE_MASK_OFF);
bridge_base        74 arch/mips/pci/pci-mt7620.c static void __iomem *bridge_base;
bridge_base        81 arch/mips/pci/pci-mt7620.c 	iowrite32(val, bridge_base + reg);
bridge_base        86 arch/mips/pci/pci-mt7620.c 	return ioread32(bridge_base + reg);
bridge_base       294 arch/mips/pci/pci-mt7620.c 	bridge_base = devm_ioremap_resource(&pdev->dev, bridge_res);
bridge_base       295 arch/mips/pci/pci-mt7620.c 	if (IS_ERR(bridge_base))
bridge_base       296 arch/mips/pci/pci-mt7620.c 		return PTR_ERR(bridge_base);
bridge_base       983 drivers/soc/mediatek/mtk-pmic-wrap.c 	void __iomem *bridge_base;
bridge_base      1482 drivers/soc/mediatek/mtk-pmic-wrap.c 	writel(0x7f, wrp->bridge_base + PWRAP_MT8135_BRIDGE_IORD_ARB_EN);
bridge_base      1483 drivers/soc/mediatek/mtk-pmic-wrap.c 	writel(0x1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_WACS3_EN);
bridge_base      1484 drivers/soc/mediatek/mtk-pmic-wrap.c 	writel(0x1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_WACS4_EN);
bridge_base      1485 drivers/soc/mediatek/mtk-pmic-wrap.c 	writel(0x1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_WDT_UNIT);
bridge_base      1486 drivers/soc/mediatek/mtk-pmic-wrap.c 	writel(0xffff, wrp->bridge_base + PWRAP_MT8135_BRIDGE_WDT_SRC_EN);
bridge_base      1487 drivers/soc/mediatek/mtk-pmic-wrap.c 	writel(0x1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_TIMER_EN);
bridge_base      1488 drivers/soc/mediatek/mtk-pmic-wrap.c 	writel(0x7ff, wrp->bridge_base + PWRAP_MT8135_BRIDGE_INT_EN);
bridge_base      1634 drivers/soc/mediatek/mtk-pmic-wrap.c 		writel(1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_INIT_DONE3);
bridge_base      1635 drivers/soc/mediatek/mtk-pmic-wrap.c 		writel(1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_INIT_DONE4);
bridge_base      1937 drivers/soc/mediatek/mtk-pmic-wrap.c 		wrp->bridge_base = devm_ioremap_resource(wrp->dev, res);
bridge_base      1938 drivers/soc/mediatek/mtk-pmic-wrap.c 		if (IS_ERR(wrp->bridge_base))
bridge_base      1939 drivers/soc/mediatek/mtk-pmic-wrap.c 			return PTR_ERR(wrp->bridge_base);