boxes             111 arch/x86/events/intel/uncore.c 	return dieid < max_dies ? pmu->boxes[dieid] : NULL;
boxes             881 arch/x86/events/intel/uncore.c 		kfree(pmu->boxes[die]);
boxes             882 arch/x86/events/intel/uncore.c 	kfree(pmu->boxes);
boxes             924 arch/x86/events/intel/uncore.c 		pmus[i].boxes	= kzalloc(size, GFP_KERNEL);
boxes             925 arch/x86/events/intel/uncore.c 		if (!pmus[i].boxes)
boxes             961 arch/x86/events/intel/uncore.c 		kfree(pmus[i].boxes);
boxes            1041 arch/x86/events/intel/uncore.c 	if (WARN_ON_ONCE(pmu->boxes[die] != NULL))
boxes            1061 arch/x86/events/intel/uncore.c 	pmu->boxes[die] = box;
boxes            1069 arch/x86/events/intel/uncore.c 		pmu->boxes[die] = NULL;
boxes            1103 arch/x86/events/intel/uncore.c 	pmu->boxes[box->dieid] = NULL;
boxes            1166 arch/x86/events/intel/uncore.c 		box = pmu->boxes[die];
boxes            1205 arch/x86/events/intel/uncore.c 			box = pmu->boxes[id];
boxes            1254 arch/x86/events/intel/uncore.c 			if (pmu->boxes[die])
boxes            1267 arch/x86/events/intel/uncore.c 		box->pmu->boxes[die] = box;
boxes            1295 arch/x86/events/intel/uncore.c 			box = pmu->boxes[id];
boxes             104 arch/x86/events/intel/uncore.h 	struct intel_uncore_box		**boxes;
boxes             599 drivers/gpu/drm/i810/i810_dma.c 	struct drm_clip_rect *pbox = sarea_priv->boxes;
boxes             672 drivers/gpu/drm/i810/i810_dma.c 	struct drm_clip_rect *pbox = sarea_priv->boxes;
boxes             719 drivers/gpu/drm/i810/i810_dma.c 	struct drm_clip_rect *box = sarea_priv->boxes;
boxes             485 drivers/gpu/drm/mga/mga_state.c 	struct drm_clip_rect *pbox = sarea_priv->boxes;
boxes             573 drivers/gpu/drm/mga/mga_state.c 	struct drm_clip_rect *pbox = sarea_priv->boxes;
boxes             641 drivers/gpu/drm/mga/mga_state.c 						   &sarea_priv->boxes[i]);
boxes             688 drivers/gpu/drm/mga/mga_state.c 						   &sarea_priv->boxes[i]);
boxes             771 drivers/gpu/drm/mga/mga_state.c 	struct drm_clip_rect *pbox = sarea_priv->boxes;
boxes              47 drivers/gpu/drm/r128/r128_state.c 				 struct drm_clip_rect *boxes, int count)
boxes              57 drivers/gpu/drm/r128/r128_state.c 		OUT_RING(boxes[0].x1);
boxes              58 drivers/gpu/drm/r128/r128_state.c 		OUT_RING(boxes[0].x2 - 1);
boxes              59 drivers/gpu/drm/r128/r128_state.c 		OUT_RING(boxes[0].y1);
boxes              60 drivers/gpu/drm/r128/r128_state.c 		OUT_RING(boxes[0].y2 - 1);
boxes              66 drivers/gpu/drm/r128/r128_state.c 		OUT_RING(boxes[1].x1);
boxes              67 drivers/gpu/drm/r128/r128_state.c 		OUT_RING(boxes[1].x2 - 1);
boxes              68 drivers/gpu/drm/r128/r128_state.c 		OUT_RING(boxes[1].y1);
boxes              69 drivers/gpu/drm/r128/r128_state.c 		OUT_RING(boxes[1].y2 - 1);
boxes              75 drivers/gpu/drm/r128/r128_state.c 		OUT_RING(boxes[2].x1);
boxes              76 drivers/gpu/drm/r128/r128_state.c 		OUT_RING(boxes[2].x2 - 1);
boxes              77 drivers/gpu/drm/r128/r128_state.c 		OUT_RING(boxes[2].y1);
boxes              78 drivers/gpu/drm/r128/r128_state.c 		OUT_RING(boxes[2].y2 - 1);
boxes             364 drivers/gpu/drm/r128/r128_state.c 	struct drm_clip_rect *pbox = sarea_priv->boxes;
boxes             469 drivers/gpu/drm/r128/r128_state.c 	struct drm_clip_rect *pbox = sarea_priv->boxes;
boxes             597 drivers/gpu/drm/r128/r128_state.c 						     &sarea_priv->boxes[i],
boxes             746 drivers/gpu/drm/r128/r128_state.c 						     &sarea_priv->boxes[i],
boxes             806 drivers/gpu/drm/savage/savage_state.c 				 const struct drm_clip_rect *boxes)
boxes             835 drivers/gpu/drm/savage/savage_state.c 		x = boxes[i].x1, y = boxes[i].y1;
boxes             836 drivers/gpu/drm/savage/savage_state.c 		w = boxes[i].x2 - boxes[i].x1;
boxes             837 drivers/gpu/drm/savage/savage_state.c 		h = boxes[i].y2 - boxes[i].y1;
boxes             875 drivers/gpu/drm/savage/savage_state.c 				unsigned int nbox, const struct drm_clip_rect *boxes)
boxes             893 drivers/gpu/drm/savage/savage_state.c 		DMA_WRITE(BCI_X_Y(boxes[i].x1, boxes[i].y1));
boxes             894 drivers/gpu/drm/savage/savage_state.c 		DMA_WRITE(BCI_X_Y(boxes[i].x1, boxes[i].y1));
boxes             895 drivers/gpu/drm/savage/savage_state.c 		DMA_WRITE(BCI_W_H(boxes[i].x2 - boxes[i].x1,
boxes             896 drivers/gpu/drm/savage/savage_state.c 				  boxes[i].y2 - boxes[i].y1));
boxes             910 drivers/gpu/drm/savage/savage_state.c 				const struct drm_clip_rect *boxes)
boxes             917 drivers/gpu/drm/savage/savage_state.c 		dev_priv->emit_clip_rect(dev_priv, &boxes[i]);
boxes             163 include/uapi/drm/i810_drm.h 	struct drm_clip_rect boxes[I810_NR_SAREA_CLIPRECTS];
boxes             190 include/uapi/drm/mga_drm.h 	struct drm_clip_rect boxes[MGA_NR_SAREA_CLIPRECTS];
boxes             162 include/uapi/drm/r128_drm.h 	struct drm_clip_rect boxes[R128_NR_SAREA_CLIPRECTS];
boxes             447 include/uapi/drm/radeon_drm.h 	struct drm_clip_rect boxes[RADEON_NR_SAREA_CLIPRECTS];
boxes             667 include/uapi/drm/radeon_drm.h 	struct drm_clip_rect __user *boxes;
boxes             188 include/uapi/drm/via_drm.h 	struct drm_clip_rect boxes[VIA_NR_SAREA_CLIPRECTS];