bot_mpcc_id       305 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 				i, s.opp_id, s.dpp_id, s.bot_mpcc_id,
bot_mpcc_id       401 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c 				i, s.opp_id, s.dpp_id, s.bot_mpcc_id,
bot_mpcc_id       396 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c 	int bot_mpcc_id;
bot_mpcc_id       417 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c 					bot_mpcc_id = bot_sel;
bot_mpcc_id       418 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c 					REG_GET(MPCC_OPP_ID[bot_mpcc_id],  MPCC_OPP_ID,  &opp_id);
bot_mpcc_id       419 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c 					REG_GET(MPCC_TOP_SEL[bot_mpcc_id], MPCC_TOP_SEL, &top_sel);
bot_mpcc_id       421 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c 						struct mpcc *mpcc_bottom = mpc1_get_mpcc(mpc, bot_mpcc_id);
bot_mpcc_id       440 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c 	REG_GET(MPCC_BOT_SEL[mpcc_inst], MPCC_BOT_SEL, &s->bot_mpcc_id);
bot_mpcc_id       138 drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h 	uint32_t bot_mpcc_id;