bootcr            160 arch/mips/ar7/clock.c 	u32 *bootcr, u32 bus_clock)
bootcr            171 arch/mips/ar7/clock.c 	switch ((*bootcr & (BOOT_PLL_SOURCE_MASK << shift)) >> shift) {
bootcr            186 arch/mips/ar7/clock.c 	if (*bootcr & BOOT_PLL_BYPASS)
bootcr            206 arch/mips/ar7/clock.c 	u32 *bootcr, u32 frequency)
bootcr            211 arch/mips/ar7/clock.c 	switch ((*bootcr & (BOOT_PLL_SOURCE_MASK << shift)) >> shift) {
bootcr            239 arch/mips/ar7/clock.c 	u32 *bootcr = (u32 *)ioremap_nocache(AR7_REGS_DCL, 4);
bootcr            245 arch/mips/ar7/clock.c 		&clocks->bus, bootcr, AR7_AFE_CLOCK);
bootcr            247 arch/mips/ar7/clock.c 	if (*bootcr & BOOT_PLL_ASYNC_MODE)
bootcr            249 arch/mips/ar7/clock.c 			&clocks->cpu, bootcr, AR7_AFE_CLOCK);
bootcr            255 arch/mips/ar7/clock.c 			bootcr, dsp_clk.rate);
bootcr            258 arch/mips/ar7/clock.c 	iounmap(bootcr);
bootcr            295 arch/mips/ar7/clock.c static int tnetd7200_get_clock_base(int clock_id, u32 *bootcr)
bootcr            297 arch/mips/ar7/clock.c 	if (*bootcr & BOOT_PLL_ASYNC_MODE)
bootcr            307 arch/mips/ar7/clock.c 		if (*bootcr & BOOT_PLL_2TO1_MODE)
bootcr            323 arch/mips/ar7/clock.c 	u32 *bootcr = (u32 *)ioremap_nocache(AR7_REGS_DCL, 4);
bootcr            331 arch/mips/ar7/clock.c 	cpu_base = tnetd7200_get_clock_base(TNETD7200_CLOCK_ID_CPU, bootcr);
bootcr            332 arch/mips/ar7/clock.c 	dsp_base = tnetd7200_get_clock_base(TNETD7200_CLOCK_ID_DSP, bootcr);
bootcr            334 arch/mips/ar7/clock.c 	if (*bootcr & BOOT_PLL_ASYNC_MODE) {
bootcr            356 arch/mips/ar7/clock.c 		if (*bootcr & BOOT_PLL_2TO1_MODE) {
bootcr            401 arch/mips/ar7/clock.c 	iounmap(bootcr);
bootcr            640 arch/mips/ar7/platform.c 	void __iomem *bootcr;
bootcr            705 arch/mips/ar7/platform.c 	bootcr = ioremap_nocache(AR7_REGS_DCL, 4);
bootcr            706 arch/mips/ar7/platform.c 	val = readl(bootcr);
bootcr            707 arch/mips/ar7/platform.c 	iounmap(bootcr);