boot_state       6108 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	struct  si_ps *boot_state = si_get_ps(amdgpu_boot_state);
boot_state       6119 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	si_convert_mc_reg_table_entry_to_smc(adev, &boot_state->performance_levels[0],
boot_state        162 drivers/gpu/drm/msm/adreno/a6xx_gmu.h int a6xx_hfi_start(struct a6xx_gmu *gmu, int boot_state);
boot_state        174 drivers/gpu/drm/msm/adreno/a6xx_hfi.c static int a6xx_hfi_send_gmu_init(struct a6xx_gmu *gmu, int boot_state)
boot_state        180 drivers/gpu/drm/msm/adreno/a6xx_hfi.c 	msg.boot_state = boot_state;
boot_state        274 drivers/gpu/drm/msm/adreno/a6xx_hfi.c int a6xx_hfi_start(struct a6xx_gmu *gmu, int boot_state)
boot_state        278 drivers/gpu/drm/msm/adreno/a6xx_hfi.c 	ret = a6xx_hfi_send_gmu_init(gmu, boot_state);
boot_state         80 drivers/gpu/drm/msm/adreno/a6xx_hfi.h 	u32 boot_state;
boot_state       2589 drivers/gpu/drm/radeon/ci_dpm.c 	struct ci_ps *boot_state = ci_get_ps(radeon_boot_state);
boot_state       2595 drivers/gpu/drm/radeon/ci_dpm.c 		    boot_state->performance_levels[0].sclk) {
boot_state       2603 drivers/gpu/drm/radeon/ci_dpm.c 		    boot_state->performance_levels[0].mclk) {
boot_state       5636 drivers/gpu/drm/radeon/ci_dpm.c 				    struct ci_vbios_boot_state *boot_state)
boot_state       5649 drivers/gpu/drm/radeon/ci_dpm.c 		boot_state->mvdd_bootup_value = le16_to_cpu(firmware_info->usBootUpMVDDCVoltage);
boot_state       5650 drivers/gpu/drm/radeon/ci_dpm.c 		boot_state->vddc_bootup_value = le16_to_cpu(firmware_info->usBootUpVDDCVoltage);
boot_state       5651 drivers/gpu/drm/radeon/ci_dpm.c 		boot_state->vddci_bootup_value = le16_to_cpu(firmware_info->usBootUpVDDCIVoltage);
boot_state       5652 drivers/gpu/drm/radeon/ci_dpm.c 		boot_state->pcie_gen_bootup_value = ci_get_current_pcie_speed(rdev);
boot_state       5653 drivers/gpu/drm/radeon/ci_dpm.c 		boot_state->pcie_lane_bootup_value = ci_get_current_pcie_lane_number(rdev);
boot_state       5654 drivers/gpu/drm/radeon/ci_dpm.c 		boot_state->sclk_bootup_value = le32_to_cpu(firmware_info->ulDefaultEngineClock);
boot_state       5655 drivers/gpu/drm/radeon/ci_dpm.c 		boot_state->mclk_bootup_value = le32_to_cpu(firmware_info->ulDefaultMemoryClock);
boot_state       1120 drivers/gpu/drm/radeon/cypress_dpm.c 	struct rv7xx_ps *boot_state = rv770_get_ps(radeon_boot_state);
boot_state       1128 drivers/gpu/drm/radeon/cypress_dpm.c 	radeon_atom_set_ac_timing(rdev, boot_state->low.mclk);
boot_state       1147 drivers/gpu/drm/radeon/cypress_dpm.c 						       boot_state->low.mclk);
boot_state       1181 drivers/gpu/drm/radeon/cypress_dpm.c 	struct rv7xx_ps *boot_state = rv770_get_ps(radeon_boot_state);
boot_state       1205 drivers/gpu/drm/radeon/cypress_dpm.c 						       boot_state->low.mclk);
boot_state       1669 drivers/gpu/drm/radeon/cypress_dpm.c 	struct rv7xx_ps *boot_state = rv770_get_ps(radeon_boot_state);
boot_state       1678 drivers/gpu/drm/radeon/cypress_dpm.c 						  &boot_state->low,
boot_state       2998 drivers/gpu/drm/radeon/ni_dpm.c 	struct ni_ps *boot_state = ni_get_ps(radeon_boot_state);
boot_state       3007 drivers/gpu/drm/radeon/ni_dpm.c 	ni_convert_mc_reg_table_entry_to_smc(rdev, &boot_state->performance_levels[0],
boot_state       1165 drivers/gpu/drm/radeon/rv770_dpm.c 	struct rv7xx_ps *boot_state = rv770_get_ps(radeon_boot_state);
boot_state       1171 drivers/gpu/drm/radeon/rv770_dpm.c 	pi->boot_sclk = boot_state->low.sclk;
boot_state       5654 drivers/gpu/drm/radeon/si_dpm.c 	struct ni_ps *boot_state = ni_get_ps(radeon_boot_state);
boot_state       5665 drivers/gpu/drm/radeon/si_dpm.c 	si_convert_mc_reg_table_entry_to_smc(rdev, &boot_state->performance_levels[0],