bndcsr 191 arch/x86/include/asm/fpu/types.h struct mpx_bndcsr bndcsr; bndcsr 48 arch/x86/include/asm/trace/mpx.h TP_PROTO(const struct mpx_bndcsr *bndcsr), bndcsr 49 arch/x86/include/asm/trace/mpx.h TP_ARGS(bndcsr), bndcsr 58 arch/x86/include/asm/trace/mpx.h __entry->bndcfgu = (u64)bndcsr->bndcfgu; bndcsr 59 arch/x86/include/asm/trace/mpx.h __entry->bndstatus = (u64)bndcsr->bndstatus; bndcsr 121 arch/x86/include/asm/trace/mpx.h void trace_bounds_exception_mpx(const struct mpx_bndcsr *bndcsr) bndcsr 433 arch/x86/kernel/traps.c const struct mpx_bndcsr *bndcsr; bndcsr 455 arch/x86/kernel/traps.c bndcsr = get_xsave_field_ptr(XFEATURE_BNDCSR); bndcsr 456 arch/x86/kernel/traps.c if (!bndcsr) bndcsr 459 arch/x86/kernel/traps.c trace_bounds_exception_mpx(bndcsr); bndcsr 465 arch/x86/kernel/traps.c switch (bndcsr->bndstatus & MPX_BNDSTA_ERROR_CODE) { bndcsr 184 arch/x86/mm/mpx.c const struct mpx_bndcsr *bndcsr; bndcsr 193 arch/x86/mm/mpx.c bndcsr = get_xsave_field_ptr(XFEATURE_BNDCSR); bndcsr 194 arch/x86/mm/mpx.c if (!bndcsr) bndcsr 201 arch/x86/mm/mpx.c if (!(bndcsr->bndcfgu & MPX_BNDCFG_ENABLE_FLAG)) bndcsr 209 arch/x86/mm/mpx.c (bndcsr->bndcfgu & MPX_BNDCFG_ADDR_MASK); bndcsr 376 arch/x86/mm/mpx.c const struct mpx_bndcsr *bndcsr; bndcsr 379 arch/x86/mm/mpx.c bndcsr = get_xsave_field_ptr(XFEATURE_BNDCSR); bndcsr 380 arch/x86/mm/mpx.c if (!bndcsr) bndcsr 385 arch/x86/mm/mpx.c bd_base = bndcsr->bndcfgu & MPX_BNDCFG_ADDR_MASK; bndcsr 390 arch/x86/mm/mpx.c bd_entry = bndcsr->bndstatus & MPX_BNDSTA_ADDR_MASK;