blend_op 67 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c uint32_t blend_op; blend_op 71 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c blend_op = DPU_BLEND_FG_ALPHA_FG_CONST | blend_op 76 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c blend_op = DPU_BLEND_FG_ALPHA_FG_PIXEL | blend_op 82 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c 0xFF, 0, blend_op); blend_op 86 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c format->alpha_enable, blend_op); blend_op 100 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c u32 stage, u32 fg_alpha, u32 bg_alpha, u32 blend_op) blend_op 115 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c DPU_REG_WRITE(c, LM_BLEND0_OP + stage_off, blend_op); blend_op 119 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c u32 stage, u32 fg_alpha, u32 bg_alpha, u32 blend_op) blend_op 133 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c DPU_REG_WRITE(c, LM_BLEND0_OP + stage_off, blend_op); blend_op 43 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h uint32_t fg_alpha, uint32_t bg_alpha, uint32_t blend_op); blend_op 225 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c uint32_t blend_op, fg_alpha, bg_alpha, ctl_blend_flags = 0; blend_op 293 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c blend_op = MDP5_LM_BLEND_OP_MODE_FG_ALPHA(FG_CONST) | blend_op 306 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c blend_op = MDP5_LM_BLEND_OP_MODE_FG_ALPHA(FG_CONST) | blend_op 310 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c blend_op |= blend_op 314 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c blend_op |= MDP5_LM_BLEND_OP_MODE_BG_INV_ALPHA; blend_op 317 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c blend_op = MDP5_LM_BLEND_OP_MODE_FG_ALPHA(FG_PIXEL) | blend_op 321 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c blend_op |= blend_op 327 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c blend_op |= MDP5_LM_BLEND_OP_MODE_BG_INV_ALPHA; blend_op 332 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c blender(i)), blend_op); blend_op 339 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c blender(i)), blend_op);