blend_cfg         222 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c 	op_mode |= (scaler3_cfg->blend_cfg & 1) << 31;
blend_cfg         120 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h 	u32 blend_cfg;
blend_cfg         280 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h 	uint32_t blend_cfg;
blend_cfg         497 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	scale_cfg->blend_cfg = 1;
blend_cfg         253 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c 	u32 blend_cfg;
blend_cfg         269 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c 	blend_cfg = ctl_read(ctl, REG_MDP5_CTL_LAYER_REG(ctl->id, mixer->lm));
blend_cfg         272 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c 		blend_cfg |=  MDP5_CTL_LAYER_REG_CURSOR_OUT;
blend_cfg         274 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c 		blend_cfg &= ~MDP5_CTL_LAYER_REG_CURSOR_OUT;
blend_cfg         276 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c 	ctl_write(ctl, REG_MDP5_CTL_LAYER_REG(ctl->id, mixer->lm), blend_cfg);
blend_cfg         355 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c 	u32 blend_cfg = 0, blend_ext_cfg = 0;
blend_cfg         363 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c 		blend_cfg |= MDP5_CTL_LAYER_REG_BORDER_COLOR;
blend_cfg         371 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c 		blend_cfg |=
blend_cfg         389 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c 		blend_cfg |=  MDP5_CTL_LAYER_REG_CURSOR_OUT;
blend_cfg         391 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c 	ctl_write(ctl, REG_MDP5_CTL_LAYER_REG(ctl->id, mixer->lm), blend_cfg);
blend_cfg         407 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c 		blend_cfg, blend_ext_cfg);