blc_pwm_ctl 115 drivers/gpu/drm/gma500/cdv_device.c u32 blc_pwm_ctl; blc_pwm_ctl 134 drivers/gpu/drm/gma500/cdv_device.c blc_pwm_ctl = REG_READ(BLC_PWM_CTL) & ~BACKLIGHT_DUTY_CYCLE_MASK; blc_pwm_ctl 135 drivers/gpu/drm/gma500/cdv_device.c REG_WRITE(BLC_PWM_CTL, (blc_pwm_ctl | blc_pwm_ctl 166 drivers/gpu/drm/gma500/cdv_intel_lvds.c u32 blc_pwm_ctl; blc_pwm_ctl 169 drivers/gpu/drm/gma500/cdv_intel_lvds.c blc_pwm_ctl = blc_pwm_ctl 172 drivers/gpu/drm/gma500/cdv_intel_lvds.c (blc_pwm_ctl | blc_pwm_ctl 176 drivers/gpu/drm/gma500/cdv_intel_lvds.c blc_pwm_ctl = dev_priv->regs.saveBLC_PWM_CTL & blc_pwm_ctl 178 drivers/gpu/drm/gma500/cdv_intel_lvds.c dev_priv->regs.saveBLC_PWM_CTL = (blc_pwm_ctl | blc_pwm_ctl 59 drivers/gpu/drm/gma500/oaktrail_device.c u32 blc_pwm_ctl; blc_pwm_ctl 69 drivers/gpu/drm/gma500/oaktrail_device.c blc_pwm_ctl = level * max_pwm_blc / 100; blc_pwm_ctl 74 drivers/gpu/drm/gma500/oaktrail_device.c blc_pwm_ctl = blc_pwm_ctl * dev_priv->blc_adj1; blc_pwm_ctl 75 drivers/gpu/drm/gma500/oaktrail_device.c blc_pwm_ctl = blc_pwm_ctl / 100; blc_pwm_ctl 80 drivers/gpu/drm/gma500/oaktrail_device.c blc_pwm_ctl = blc_pwm_ctl * dev_priv->blc_adj2; blc_pwm_ctl 81 drivers/gpu/drm/gma500/oaktrail_device.c blc_pwm_ctl = blc_pwm_ctl / 100; blc_pwm_ctl 85 drivers/gpu/drm/gma500/oaktrail_device.c REG_WRITE(BLC_PWM_CTL, (max_pwm_blc << 16) | blc_pwm_ctl); blc_pwm_ctl 185 drivers/gpu/drm/gma500/psb_intel_lvds.c u32 blc_pwm_ctl; blc_pwm_ctl 188 drivers/gpu/drm/gma500/psb_intel_lvds.c blc_pwm_ctl = REG_READ(BLC_PWM_CTL); blc_pwm_ctl 189 drivers/gpu/drm/gma500/psb_intel_lvds.c blc_pwm_ctl &= ~BACKLIGHT_DUTY_CYCLE_MASK; blc_pwm_ctl 191 drivers/gpu/drm/gma500/psb_intel_lvds.c (blc_pwm_ctl | blc_pwm_ctl 193 drivers/gpu/drm/gma500/psb_intel_lvds.c dev_priv->regs.saveBLC_PWM_CTL = (blc_pwm_ctl | blc_pwm_ctl 197 drivers/gpu/drm/gma500/psb_intel_lvds.c blc_pwm_ctl = dev_priv->regs.saveBLC_PWM_CTL & blc_pwm_ctl 199 drivers/gpu/drm/gma500/psb_intel_lvds.c dev_priv->regs.saveBLC_PWM_CTL = (blc_pwm_ctl |