bl_desc           626 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c 	struct acr_r352_flcn_bl_desc *bl_desc = _bl_desc;
bl_desc           632 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c 	bl_desc->ctx_dma = FALCON_DMAIDX_VIRT;
bl_desc           633 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c 	bl_desc->code_dma_base = lower_32_bits(addr_code);
bl_desc           634 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c 	bl_desc->non_sec_code_off = hdr->non_sec_code_off;
bl_desc           635 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c 	bl_desc->non_sec_code_size = hdr->non_sec_code_size;
bl_desc           636 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c 	bl_desc->sec_code_off = hsf_load_header_app_off(hdr, 0);
bl_desc           637 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c 	bl_desc->sec_code_size = hsf_load_header_app_size(hdr, 0);
bl_desc           638 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c 	bl_desc->code_entry_point = 0;
bl_desc           639 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c 	bl_desc->data_dma_base = lower_32_bits(addr_data);
bl_desc           640 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c 	bl_desc->data_size = hdr->data_size;
bl_desc           791 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c 	u8 *bl_desc;
bl_desc           793 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c 	bl_desc = kzalloc(bl_desc_size, GFP_KERNEL);
bl_desc           794 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c 	if (!bl_desc)
bl_desc           806 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c 		kfree(bl_desc);
bl_desc           827 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c 	acr->func->generate_hs_bl_desc(load_hdr, bl_desc, offset);
bl_desc           832 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c 	nvkm_falcon_load_dmem(falcon, bl_desc, hsbl_desc->dmem_load_off,
bl_desc           835 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c 	kfree(bl_desc);
bl_desc            56 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r361.c 	struct acr_r361_flcn_bl_desc *bl_desc = _bl_desc;
bl_desc            58 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r361.c 	bl_desc->ctx_dma = FALCON_DMAIDX_VIRT;
bl_desc            59 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r361.c 	bl_desc->code_dma_base = u64_to_flcn64(offset);
bl_desc            60 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r361.c 	bl_desc->non_sec_code_off = hdr->non_sec_code_off;
bl_desc            61 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r361.c 	bl_desc->non_sec_code_size = hdr->non_sec_code_size;
bl_desc            62 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r361.c 	bl_desc->sec_code_off = hsf_load_header_app_off(hdr, 0);
bl_desc            63 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r361.c 	bl_desc->sec_code_size = hsf_load_header_app_size(hdr, 0);
bl_desc            64 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r361.c 	bl_desc->code_entry_point = 0;
bl_desc            65 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r361.c 	bl_desc->data_dma_base = u64_to_flcn64(offset + hdr->data_dma_base);
bl_desc            66 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r361.c 	bl_desc->data_size = hdr->data_size;
bl_desc           134 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r370.c 	struct acr_r370_flcn_bl_desc *bl_desc = _bl_desc;
bl_desc           136 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r370.c 	bl_desc->ctx_dma = FALCON_DMAIDX_VIRT;
bl_desc           137 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r370.c 	bl_desc->non_sec_code_off = hdr->non_sec_code_off;
bl_desc           138 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r370.c 	bl_desc->non_sec_code_size = hdr->non_sec_code_size;
bl_desc           139 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r370.c 	bl_desc->sec_code_off = hsf_load_header_app_off(hdr, 0);
bl_desc           140 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r370.c 	bl_desc->sec_code_size = hsf_load_header_app_size(hdr, 0);
bl_desc           141 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r370.c 	bl_desc->code_entry_point = 0;
bl_desc           142 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r370.c 	bl_desc->code_dma_base = u64_to_flcn64(offset);
bl_desc           143 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r370.c 	bl_desc->data_dma_base = u64_to_flcn64(offset + hdr->data_dma_base);
bl_desc           144 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r370.c 	bl_desc->data_size = hdr->data_size;
bl_desc            46 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/ls_ucode_gr.c 	struct fw_bl_desc *bl_desc = (void *)bl->data + bin_hdr->header_offset;
bl_desc            52 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/ls_ucode_gr.c 	desc->bootloader_size = ALIGN(bl_desc->code_size, sizeof(u32));
bl_desc            53 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/ls_ucode_gr.c 	desc->bootloader_imem_offset = bl_desc->start_tag * 256;
bl_desc            54 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/ls_ucode_gr.c 	desc->bootloader_entry_point = bl_desc->start_tag * 256;
bl_desc            70 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/ls_ucode_gr.c 	desc->image_size = ALIGN(bl_desc->code_size, BL_DESC_BLK_SIZE) +
bl_desc            78 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/ls_ucode_gr.c 	       bl_desc->code_size);
bl_desc           309 lib/zlib_deflate/deftree.c     s->bl_desc.dyn_tree = s->bl_tree;
bl_desc           310 lib/zlib_deflate/deftree.c     s->bl_desc.stat_desc = &static_bl_desc;
bl_desc           735 lib/zlib_deflate/deftree.c     build_tree(s, (tree_desc *)(&(s->bl_desc)));
bl_desc           174 lib/zlib_deflate/defutil.h     struct tree_desc_s bl_desc;              /* desc. for bit length tree */