bist               45 arch/mips/include/asm/octeon/cvmx-ciu3-defs.h 	uint64_t bist                         : 9;
bist               47 arch/mips/include/asm/octeon/cvmx-ciu3-defs.h 	uint64_t bist                         : 9;
bist               86 arch/mips/include/asm/octeon/cvmx-dpi-defs.h 		uint64_t bist:47;
bist               88 arch/mips/include/asm/octeon/cvmx-dpi-defs.h 		uint64_t bist:47;
bist               95 arch/mips/include/asm/octeon/cvmx-dpi-defs.h 		uint64_t bist:45;
bist               97 arch/mips/include/asm/octeon/cvmx-dpi-defs.h 		uint64_t bist:45;
bist              104 arch/mips/include/asm/octeon/cvmx-dpi-defs.h 		uint64_t bist:37;
bist              106 arch/mips/include/asm/octeon/cvmx-dpi-defs.h 		uint64_t bist:37;
bist              189 arch/mips/include/asm/octeon/cvmx-pip-defs.h 		uint64_t bist:22;
bist              191 arch/mips/include/asm/octeon/cvmx-pip-defs.h 		uint64_t bist:22;
bist              198 arch/mips/include/asm/octeon/cvmx-pip-defs.h 		uint64_t bist:18;
bist              200 arch/mips/include/asm/octeon/cvmx-pip-defs.h 		uint64_t bist:18;
bist              207 arch/mips/include/asm/octeon/cvmx-pip-defs.h 		uint64_t bist:17;
bist              209 arch/mips/include/asm/octeon/cvmx-pip-defs.h 		uint64_t bist:17;
bist              216 arch/mips/include/asm/octeon/cvmx-pip-defs.h 		uint64_t bist:20;
bist              218 arch/mips/include/asm/octeon/cvmx-pip-defs.h 		uint64_t bist:20;
bist              346 arch/mips/txx9/generic/pci.c 	unsigned char bist;
bist              349 arch/mips/txx9/generic/pci.c 	if (pci_read_config_byte(dev, PCI_BIST, &bist) == PCIBIOS_SUCCESSFUL &&
bist              350 arch/mips/txx9/generic/pci.c 	    (bist & PCI_BIST_CAPABLE)) {
bist              357 arch/mips/txx9/generic/pci.c 			pci_read_config_byte(dev, PCI_BIST, &bist);
bist              360 arch/mips/txx9/generic/pci.c 		} while (bist & PCI_BIST_START);
bist              361 arch/mips/txx9/generic/pci.c 		if (bist & (PCI_BIST_CODE_MASK | PCI_BIST_START))
bist              362 arch/mips/txx9/generic/pci.c 			pr_cont("failed. (0x%x)\n", bist);
bist              431 drivers/crypto/cavium/cpt/cptpf_main.c 	u64 bist;
bist              439 drivers/crypto/cavium/cpt/cptpf_main.c 	bist = (u64)cpt_check_bist_status(cpt);
bist              440 drivers/crypto/cavium/cpt/cptpf_main.c 	if (bist) {
bist              441 drivers/crypto/cavium/cpt/cptpf_main.c 		dev_err(dev, "RAM BIST failed with code 0x%llx", bist);
bist              445 drivers/crypto/cavium/cpt/cptpf_main.c 	bist = cpt_check_exe_bist_status(cpt);
bist              446 drivers/crypto/cavium/cpt/cptpf_main.c 	if (bist) {
bist              447 drivers/crypto/cavium/cpt/cptpf_main.c 		dev_err(dev, "Engine BIST failed with code 0x%llx", bist);
bist             6014 drivers/net/ethernet/neterion/s2io.c 	u8 bist = 0;
bist             6017 drivers/net/ethernet/neterion/s2io.c 	pci_read_config_byte(sp->pdev, PCI_BIST, &bist);
bist             6018 drivers/net/ethernet/neterion/s2io.c 	bist |= PCI_BIST_START;
bist             6019 drivers/net/ethernet/neterion/s2io.c 	pci_write_config_word(sp->pdev, PCI_BIST, bist);
bist             6022 drivers/net/ethernet/neterion/s2io.c 		pci_read_config_byte(sp->pdev, PCI_BIST, &bist);
bist             6023 drivers/net/ethernet/neterion/s2io.c 		if (!(bist & PCI_BIST_START)) {
bist             6024 drivers/net/ethernet/neterion/s2io.c 			*data = (bist & PCI_BIST_CODE_MASK);
bist               17 drivers/net/wireless/broadcom/brcm80211/include/chipcommon.h 	u32 bist;
bist               17 drivers/pci/pci-bridge-emul.h 	u8 bist;
bist               19 include/video/gbe.h 	volatile uint32_t bist;         /* internal bist status [1] */