CONFIG_RAMBASE    214 arch/m68k/coldfire/pci.c 	__raw_writel(CONFIG_RAMBASE, PCIBAR1);
CONFIG_RAMBASE    215 arch/m68k/coldfire/pci.c 	__raw_writel(CONFIG_RAMBASE | PCITBATR1_E, PCITBATR1);
CONFIG_RAMBASE     89 arch/m68k/include/asm/m52xxacr.h #define ACR0_MODE	((CONFIG_RAMBASE & 0xff000000) + \
CONFIG_RAMBASE     96 arch/m68k/include/asm/m53xxacr.h #define ACR0_MODE	((CONFIG_RAMBASE & 0xff000000) + \
CONFIG_RAMBASE    101 arch/m68k/include/asm/m54xxacr.h #define ACR1_MODE	(ACR_BA(CONFIG_RAMBASE)+ACR_ADMSK(CONFIG_RAMSIZE)+ \
CONFIG_RAMBASE    104 arch/m68k/include/asm/m54xxacr.h #define ACR1_MODE	(ACR_BA(CONFIG_RAMBASE)+ACR_ADMSK(CONFIG_RAMSIZE)+ \
CONFIG_RAMBASE    108 arch/m68k/include/asm/m54xxacr.h #define ACR3_MODE	(ACR_BA(CONFIG_RAMBASE)+ACR_ADMSK(CONFIG_RAMSIZE)+ \
CONFIG_RAMBASE      4 arch/m68k/include/asm/page_offset.h #if defined(CONFIG_RAMBASE)
CONFIG_RAMBASE      5 arch/m68k/include/asm/page_offset.h #define PAGE_OFFSET_RAW		CONFIG_RAMBASE