bcr 170 arch/arc/kernel/setup.c struct bcr_generic bcr; bcr 241 arch/arc/kernel/setup.c READ_BCR(ARC_REG_SMART_BCR, bcr); bcr 242 arch/arc/kernel/setup.c cpu->extn.smart = bcr.ver ? 1 : 0; bcr 244 arch/arc/kernel/setup.c READ_BCR(ARC_REG_RTT_BCR, bcr); bcr 245 arch/arc/kernel/setup.c cpu->extn.rtt = bcr.ver ? 1 : 0; bcr 255 arch/arc/kernel/setup.c struct bcr_generic bcr = *(struct bcr_generic *)&isa; bcr 256 arch/arc/kernel/setup.c cpu->isa.atomic = bcr.info & 1; bcr 94 arch/arm64/include/asm/hw_breakpoint.h #define AARCH64_DBG_REG_NAME_BCR bcr bcr 32 arch/powerpc/include/asm/mpc5121.h u32 bcr; /* Bread Crumb Register */ bcr 81 drivers/dma/fsldma.c FSL_DMA_OUT(chan, &chan->regs->bcr, val, 32); bcr 86 drivers/dma/fsldma.c return FSL_DMA_IN(chan, &chan->regs->bcr, 32); bcr 113 drivers/dma/fsldma.h u32 bcr; /* 0x20 - Byte Count Register */ bcr 862 drivers/gpu/drm/omapdrm/dss/dispc.c int ry, rcb, rcr, gy, gcb, gcr, by, bcb, bcr; bcr 880 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_write_reg(dispc, DISPC_OVL_CONV_COEF(plane, 3), CVAL(ct->bcr, ct->by)); bcr 261 drivers/i2c/busses/i2c-synquacer.c unsigned char bsr, bcr; bcr 269 drivers/i2c/busses/i2c-synquacer.c bcr = readb(i2c->base + SYNQUACER_I2C_REG_BCR); bcr 270 drivers/i2c/busses/i2c-synquacer.c dev_dbg(i2c->dev, "bsr:0x%02x, bcr:0x%02x\n", bsr, bcr); bcr 273 drivers/i2c/busses/i2c-synquacer.c !(bcr & SYNQUACER_I2C_BCR_MSS)) { bcr 280 drivers/i2c/busses/i2c-synquacer.c writeb(bcr | SYNQUACER_I2C_BCR_SCC, bcr 283 drivers/i2c/busses/i2c-synquacer.c if (bcr & SYNQUACER_I2C_BCR_MSS) { bcr 289 drivers/i2c/busses/i2c-synquacer.c writeb(bcr | SYNQUACER_I2C_BCR_MSS | bcr 298 drivers/i2c/busses/i2c-synquacer.c bcr = readb(i2c->base + SYNQUACER_I2C_REG_BCR); bcr 299 drivers/i2c/busses/i2c-synquacer.c dev_dbg(i2c->dev, "bsr:0x%02x, bcr:0x%02x\n", bsr, bcr); bcr 302 drivers/i2c/busses/i2c-synquacer.c !(bcr & SYNQUACER_I2C_BCR_MSS)) { bcr 362 drivers/i2c/busses/i2c-synquacer.c unsigned char bsr, bcr; bcr 365 drivers/i2c/busses/i2c-synquacer.c bcr = readb(i2c->base + SYNQUACER_I2C_REG_BCR); bcr 367 drivers/i2c/busses/i2c-synquacer.c dev_dbg(i2c->dev, "bsr:0x%02x, bcr:0x%02x\n", bsr, bcr); bcr 369 drivers/i2c/busses/i2c-synquacer.c if (bcr & SYNQUACER_I2C_BCR_BER) { bcr 375 drivers/i2c/busses/i2c-synquacer.c !(bcr & SYNQUACER_I2C_BCR_MSS)) { bcr 141 drivers/i3c/master.c ret = sprintf(buf, "%x\n", desc->info.bcr); bcr 146 drivers/i3c/master.c static DEVICE_ATTR_RO(bcr); bcr 897 drivers/i3c/master.c if (I3C_BCR_DEVICE_ROLE(i3cdev->info.bcr) == bcr 916 drivers/i3c/master.c defslvs->master.bcr = master->this->info.bcr; bcr 933 drivers/i3c/master.c desc->bcr = i3cdev->info.bcr; bcr 1002 drivers/i3c/master.c if (!(info->bcr & I3C_BCR_IBI_PAYLOAD)) bcr 1018 drivers/i3c/master.c if (info->bcr & I3C_BCR_IBI_PAYLOAD) bcr 1171 drivers/i3c/master.c info->bcr = getbcr->bcr; bcr 1231 drivers/i3c/master.c if (dev->info.bcr & I3C_BCR_MAX_DATA_SPEED_LIM) { bcr 1237 drivers/i3c/master.c if (dev->info.bcr & I3C_BCR_IBI_PAYLOAD) bcr 1243 drivers/i3c/master.c if (dev->info.bcr & I3C_BCR_HDR_CAP) { bcr 1545 drivers/i3c/master.c if (I3C_BCR_DEVICE_ROLE(info->bcr) == I3C_BCR_I3C_MASTER && bcr 297 drivers/i3c/master/i3c-master-cdns.c #define DEV_ID_RR2_BCR(bcr) ((bcr) << 8) bcr 1049 drivers/i3c/master/i3c-master-cdns.c info->bcr = rr >> 8; bcr 1253 drivers/i3c/master/i3c-master-cdns.c if (info.bcr & I3C_BCR_HDR_CAP) bcr 1413 drivers/i3c/master/i3c-master-cdns.c sircfg = SIR_MAP_DEV_ROLE(dev->info.bcr >> 6) | bcr 1418 drivers/i3c/master/i3c-master-cdns.c if (dev->info.bcr & I3C_BCR_MAX_DATA_SPEED_LIM) bcr 1091 drivers/mfd/lpc_ich.c u32 spi_base, rcba, bcr; bcr 1115 drivers/mfd/lpc_ich.c pci_read_config_dword(dev, BCR, &bcr); bcr 1116 drivers/mfd/lpc_ich.c info->writeable = !!(bcr & BCR_WPD); bcr 1137 drivers/mfd/lpc_ich.c pci_bus_read_config_dword(bus, spi, BCR, &bcr); bcr 1138 drivers/mfd/lpc_ich.c info->writeable = !!(bcr & BCR_WPD); bcr 28 drivers/mtd/spi-nor/intel-spi-pci.c u32 bcr; bcr 41 drivers/mtd/spi-nor/intel-spi-pci.c pci_read_config_dword(pdev, BCR, &bcr); bcr 42 drivers/mtd/spi-nor/intel-spi-pci.c if (!(bcr & BCR_WPD)) { bcr 43 drivers/mtd/spi-nor/intel-spi-pci.c bcr |= BCR_WPD; bcr 44 drivers/mtd/spi-nor/intel-spi-pci.c pci_write_config_dword(pdev, BCR, bcr); bcr 45 drivers/mtd/spi-nor/intel-spi-pci.c pci_read_config_dword(pdev, BCR, &bcr); bcr 47 drivers/mtd/spi-nor/intel-spi-pci.c info->writeable = !!(bcr & BCR_WPD); bcr 74 drivers/net/can/cc770/cc770_isa.c static u8 bcr[MAXDEV] = {[0 ... (MAXDEV - 1)] = 0xff}; bcr 99 drivers/net/can/cc770/cc770_isa.c module_param_array(bcr, byte, NULL, 0444); bcr 100 drivers/net/can/cc770/cc770_isa.c MODULE_PARM_DESC(bcr, "Bus configuration register (default=0x40 [CBY])"); bcr 246 drivers/net/can/cc770/cc770_isa.c if (bcr[idx] != 0xff) bcr 247 drivers/net/can/cc770/cc770_isa.c priv->bus_config = bcr[idx]; bcr 248 drivers/net/can/cc770/cc770_isa.c else if (bcr[0] != 0xff) bcr 249 drivers/net/can/cc770/cc770_isa.c priv->bus_config = bcr[0]; bcr 153 drivers/net/can/cc770/cc770_platform.c priv->bus_config = pdata->bcr; bcr 65 drivers/net/can/rcar/rcar_can.c u8 bcr[3]; /* Bit Configuration Register */ bcr 431 drivers/net/can/rcar/rcar_can.c u32 bcr; bcr 433 drivers/net/can/rcar/rcar_can.c bcr = RCAR_CAN_BCR_TSEG1(bt->phase_seg1 + bt->prop_seg - 1) | bcr 440 drivers/net/can/rcar/rcar_can.c writel((bcr << 8) | priv->clock_select, &priv->regs->bcr); bcr 239 drivers/video/fbdev/omap2/omapfb/dss/dispc.c int ry, rcr, rcb, gy, gcr, gcb, by, bcr, bcb; bcr 697 drivers/video/fbdev/omap2/omapfb/dss/dispc.c dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 3), CVAL(ct->bcr, ct->by)); bcr 31 include/linux/can/platform/cc770.h u8 bcr; /* Bus Configuration Register */ bcr 116 include/linux/i3c/ccc.h u8 bcr; bcr 188 include/linux/i3c/ccc.h u8 bcr; bcr 86 include/linux/i3c/device.h #define I3C_BCR_DEVICE_ROLE(bcr) ((bcr) & GENMASK(7, 6)) bcr 120 include/linux/i3c/device.h u8 bcr; bcr 91 include/soc/arc/mcip.h #define mcip_idu_bcr_to_nr_irqs(bcr) (4 * (1 << (bcr).cirqnum)) bcr 475 sound/soc/fsl/fsl_dma.c out_be32(&dma_channel->bcr, 0); bcr 788 sound/soc/fsl/fsl_dma.c out_be32(&dma_channel->bcr, 0); bcr 20 sound/soc/fsl/fsl_dma.h __be32 bcr; /* Byte count register */