bases 77 arch/x86/boot/early_serial_console.c static const int bases[] = { 0x3f8, 0x2f8 }; bases 86 arch/x86/boot/early_serial_console.c port = bases[idx]; bases 165 arch/x86/kernel/early_printk.c static const int __initconst bases[] = { 0x3f8, 0x2f8 }; bases 172 arch/x86/kernel/early_printk.c early_serial_base = bases[port]; bases 65 drivers/clk/ux500/u8500_of_clk.c u32 bases[CLKRST_MAX]; bases 68 drivers/clk/ux500/u8500_of_clk.c for (i = 0; i < ARRAY_SIZE(bases); i++) { bases 75 drivers/clk/ux500/u8500_of_clk.c bases[i] = r.start; bases 253 drivers/clk/ux500/u8500_of_clk.c clk = clk_reg_prcc_pclk("p1_pclk0", "per1clk", bases[CLKRST1_INDEX], bases 257 drivers/clk/ux500/u8500_of_clk.c clk = clk_reg_prcc_pclk("p1_pclk1", "per1clk", bases[CLKRST1_INDEX], bases 261 drivers/clk/ux500/u8500_of_clk.c clk = clk_reg_prcc_pclk("p1_pclk2", "per1clk", bases[CLKRST1_INDEX], bases 265 drivers/clk/ux500/u8500_of_clk.c clk = clk_reg_prcc_pclk("p1_pclk3", "per1clk", bases[CLKRST1_INDEX], bases 269 drivers/clk/ux500/u8500_of_clk.c clk = clk_reg_prcc_pclk("p1_pclk4", "per1clk", bases[CLKRST1_INDEX], bases 273 drivers/clk/ux500/u8500_of_clk.c clk = clk_reg_prcc_pclk("p1_pclk5", "per1clk", bases[CLKRST1_INDEX], bases 277 drivers/clk/ux500/u8500_of_clk.c clk = clk_reg_prcc_pclk("p1_pclk6", "per1clk", bases[CLKRST1_INDEX], bases 281 drivers/clk/ux500/u8500_of_clk.c clk = clk_reg_prcc_pclk("p1_pclk7", "per1clk", bases[CLKRST1_INDEX], bases 285 drivers/clk/ux500/u8500_of_clk.c clk = clk_reg_prcc_pclk("p1_pclk8", "per1clk", bases[CLKRST1_INDEX], bases 289 drivers/clk/ux500/u8500_of_clk.c clk = clk_reg_prcc_pclk("p1_pclk9", "per1clk", bases[CLKRST1_INDEX], bases 293 drivers/clk/ux500/u8500_of_clk.c clk = clk_reg_prcc_pclk("p1_pclk10", "per1clk", bases[CLKRST1_INDEX], bases 297 drivers/clk/ux500/u8500_of_clk.c clk = clk_reg_prcc_pclk("p1_pclk11", "per1clk", bases[CLKRST1_INDEX], bases 301 drivers/clk/ux500/u8500_of_clk.c clk = clk_reg_prcc_pclk("p2_pclk0", "per2clk", bases[CLKRST2_INDEX], bases 305 drivers/clk/ux500/u8500_of_clk.c clk = clk_reg_prcc_pclk("p2_pclk1", "per2clk", bases[CLKRST2_INDEX], bases 309 drivers/clk/ux500/u8500_of_clk.c clk = clk_reg_prcc_pclk("p2_pclk2", "per2clk", bases[CLKRST2_INDEX], bases 313 drivers/clk/ux500/u8500_of_clk.c clk = clk_reg_prcc_pclk("p2_pclk3", "per2clk", bases[CLKRST2_INDEX], bases 317 drivers/clk/ux500/u8500_of_clk.c clk = clk_reg_prcc_pclk("p2_pclk4", "per2clk", bases[CLKRST2_INDEX], bases 321 drivers/clk/ux500/u8500_of_clk.c clk = clk_reg_prcc_pclk("p2_pclk5", "per2clk", bases[CLKRST2_INDEX], bases 325 drivers/clk/ux500/u8500_of_clk.c clk = clk_reg_prcc_pclk("p2_pclk6", "per2clk", bases[CLKRST2_INDEX], bases 329 drivers/clk/ux500/u8500_of_clk.c clk = clk_reg_prcc_pclk("p2_pclk7", "per2clk", bases[CLKRST2_INDEX], bases 333 drivers/clk/ux500/u8500_of_clk.c clk = clk_reg_prcc_pclk("p2_pclk8", "per2clk", bases[CLKRST2_INDEX], bases 337 drivers/clk/ux500/u8500_of_clk.c clk = clk_reg_prcc_pclk("p2_pclk9", "per2clk", bases[CLKRST2_INDEX], bases 341 drivers/clk/ux500/u8500_of_clk.c clk = clk_reg_prcc_pclk("p2_pclk10", "per2clk", bases[CLKRST2_INDEX], bases 345 drivers/clk/ux500/u8500_of_clk.c clk = clk_reg_prcc_pclk("p2_pclk11", "per2clk", bases[CLKRST2_INDEX], bases 349 drivers/clk/ux500/u8500_of_clk.c clk = clk_reg_prcc_pclk("p2_pclk12", "per2clk", bases[CLKRST2_INDEX], bases 353 drivers/clk/ux500/u8500_of_clk.c clk = clk_reg_prcc_pclk("p3_pclk0", "per3clk", bases[CLKRST3_INDEX], bases 357 drivers/clk/ux500/u8500_of_clk.c clk = clk_reg_prcc_pclk("p3_pclk1", "per3clk", bases[CLKRST3_INDEX], bases 361 drivers/clk/ux500/u8500_of_clk.c clk = clk_reg_prcc_pclk("p3_pclk2", "per3clk", bases[CLKRST3_INDEX], bases 365 drivers/clk/ux500/u8500_of_clk.c clk = clk_reg_prcc_pclk("p3_pclk3", "per3clk", bases[CLKRST3_INDEX], bases 369 drivers/clk/ux500/u8500_of_clk.c clk = clk_reg_prcc_pclk("p3_pclk4", "per3clk", bases[CLKRST3_INDEX], bases 373 drivers/clk/ux500/u8500_of_clk.c clk = clk_reg_prcc_pclk("p3_pclk5", "per3clk", bases[CLKRST3_INDEX], bases 377 drivers/clk/ux500/u8500_of_clk.c clk = clk_reg_prcc_pclk("p3_pclk6", "per3clk", bases[CLKRST3_INDEX], bases 381 drivers/clk/ux500/u8500_of_clk.c clk = clk_reg_prcc_pclk("p3_pclk7", "per3clk", bases[CLKRST3_INDEX], bases 385 drivers/clk/ux500/u8500_of_clk.c clk = clk_reg_prcc_pclk("p3_pclk8", "per3clk", bases[CLKRST3_INDEX], bases 389 drivers/clk/ux500/u8500_of_clk.c clk = clk_reg_prcc_pclk("p5_pclk0", "per5clk", bases[CLKRST5_INDEX], bases 393 drivers/clk/ux500/u8500_of_clk.c clk = clk_reg_prcc_pclk("p5_pclk1", "per5clk", bases[CLKRST5_INDEX], bases 397 drivers/clk/ux500/u8500_of_clk.c clk = clk_reg_prcc_pclk("p6_pclk0", "per6clk", bases[CLKRST6_INDEX], bases 401 drivers/clk/ux500/u8500_of_clk.c clk = clk_reg_prcc_pclk("p6_pclk1", "per6clk", bases[CLKRST6_INDEX], bases 405 drivers/clk/ux500/u8500_of_clk.c clk = clk_reg_prcc_pclk("p6_pclk2", "per6clk", bases[CLKRST6_INDEX], bases 409 drivers/clk/ux500/u8500_of_clk.c clk = clk_reg_prcc_pclk("p6_pclk3", "per6clk", bases[CLKRST6_INDEX], bases 413 drivers/clk/ux500/u8500_of_clk.c clk = clk_reg_prcc_pclk("p6_pclk4", "per6clk", bases[CLKRST6_INDEX], bases 417 drivers/clk/ux500/u8500_of_clk.c clk = clk_reg_prcc_pclk("p6_pclk5", "per6clk", bases[CLKRST6_INDEX], bases 421 drivers/clk/ux500/u8500_of_clk.c clk = clk_reg_prcc_pclk("p6_pclk6", "per6clk", bases[CLKRST6_INDEX], bases 425 drivers/clk/ux500/u8500_of_clk.c clk = clk_reg_prcc_pclk("p6_pclk7", "per6clk", bases[CLKRST6_INDEX], bases 439 drivers/clk/ux500/u8500_of_clk.c bases[CLKRST1_INDEX], BIT(0), CLK_SET_RATE_GATE); bases 443 drivers/clk/ux500/u8500_of_clk.c bases[CLKRST1_INDEX], BIT(1), CLK_SET_RATE_GATE); bases 447 drivers/clk/ux500/u8500_of_clk.c bases[CLKRST1_INDEX], BIT(2), CLK_SET_RATE_GATE); bases 451 drivers/clk/ux500/u8500_of_clk.c bases[CLKRST1_INDEX], BIT(3), CLK_SET_RATE_GATE); bases 455 drivers/clk/ux500/u8500_of_clk.c bases[CLKRST1_INDEX], BIT(4), CLK_SET_RATE_GATE); bases 459 drivers/clk/ux500/u8500_of_clk.c bases[CLKRST1_INDEX], BIT(5), CLK_SET_RATE_GATE); bases 463 drivers/clk/ux500/u8500_of_clk.c bases[CLKRST1_INDEX], BIT(6), CLK_SET_RATE_GATE); bases 467 drivers/clk/ux500/u8500_of_clk.c bases[CLKRST1_INDEX], BIT(8), CLK_SET_RATE_GATE); bases 471 drivers/clk/ux500/u8500_of_clk.c bases[CLKRST1_INDEX], BIT(9), CLK_SET_RATE_GATE); bases 475 drivers/clk/ux500/u8500_of_clk.c bases[CLKRST1_INDEX], BIT(10), CLK_SET_RATE_GATE); bases 480 drivers/clk/ux500/u8500_of_clk.c bases[CLKRST2_INDEX], BIT(0), CLK_SET_RATE_GATE); bases 484 drivers/clk/ux500/u8500_of_clk.c bases[CLKRST2_INDEX], BIT(2), CLK_SET_RATE_GATE); bases 488 drivers/clk/ux500/u8500_of_clk.c bases[CLKRST2_INDEX], BIT(3), CLK_SET_RATE_GATE); bases 492 drivers/clk/ux500/u8500_of_clk.c bases[CLKRST2_INDEX], BIT(4), CLK_SET_RATE_GATE); bases 496 drivers/clk/ux500/u8500_of_clk.c bases[CLKRST2_INDEX], BIT(5), CLK_SET_RATE_GATE); bases 501 drivers/clk/ux500/u8500_of_clk.c bases[CLKRST2_INDEX], BIT(6), bases 506 drivers/clk/ux500/u8500_of_clk.c bases[CLKRST2_INDEX], BIT(7), bases 512 drivers/clk/ux500/u8500_of_clk.c bases[CLKRST3_INDEX], BIT(1), CLK_SET_RATE_GATE); bases 516 drivers/clk/ux500/u8500_of_clk.c bases[CLKRST3_INDEX], BIT(2), CLK_SET_RATE_GATE); bases 520 drivers/clk/ux500/u8500_of_clk.c bases[CLKRST3_INDEX], BIT(3), CLK_SET_RATE_GATE); bases 524 drivers/clk/ux500/u8500_of_clk.c bases[CLKRST3_INDEX], BIT(4), CLK_SET_RATE_GATE); bases 528 drivers/clk/ux500/u8500_of_clk.c bases[CLKRST3_INDEX], BIT(5), CLK_SET_RATE_GATE); bases 532 drivers/clk/ux500/u8500_of_clk.c bases[CLKRST3_INDEX], BIT(6), CLK_SET_RATE_GATE); bases 536 drivers/clk/ux500/u8500_of_clk.c bases[CLKRST3_INDEX], BIT(7), CLK_SET_RATE_GATE); bases 541 drivers/clk/ux500/u8500_of_clk.c bases[CLKRST6_INDEX], BIT(0), CLK_SET_RATE_GATE); bases 154 drivers/gpu/drm/exynos/exynos_drm_scaler.c static unsigned int bases[] = { bases 162 drivers/gpu/drm/exynos/exynos_drm_scaler.c scaler_write(src_buf->dma_addr[i], bases[i]); bases 217 drivers/gpu/drm/exynos/exynos_drm_scaler.c static unsigned int bases[] = { bases 225 drivers/gpu/drm/exynos/exynos_drm_scaler.c scaler_write(dst_buf->dma_addr[i], bases[i]); bases 225 drivers/gpu/drm/i915/gt/intel_engine_cs.c const struct engine_mmio_base *bases) bases 230 drivers/gpu/drm/i915/gt/intel_engine_cs.c if (INTEL_GEN(i915) >= bases[i].gen) bases 234 drivers/gpu/drm/i915/gt/intel_engine_cs.c GEM_BUG_ON(!bases[i].base); bases 236 drivers/gpu/drm/i915/gt/intel_engine_cs.c return bases[i].base; bases 33 drivers/gpu/drm/nouveau/dispnv50/base.c } bases[] = { bases 46 drivers/gpu/drm/nouveau/dispnv50/base.c cid = nvif_mclass(&disp->disp->object, bases); bases 52 drivers/gpu/drm/nouveau/dispnv50/base.c return bases[cid].new(drm, head, bases[cid].oclass, pwndw); bases 111 drivers/gpu/host1x/dev.h struct host1x_syncpt_base *bases; bases 25 drivers/gpu/host1x/syncpt.c struct host1x_syncpt_base *bases = host->bases; bases 29 drivers/gpu/host1x/syncpt.c if (!bases[i].requested) bases 35 drivers/gpu/host1x/syncpt.c bases[i].requested = true; bases 36 drivers/gpu/host1x/syncpt.c return &bases[i]; bases 367 drivers/gpu/host1x/syncpt.c struct host1x_syncpt_base *bases; bases 376 drivers/gpu/host1x/syncpt.c bases = devm_kcalloc(host->dev, host->info->nb_bases, sizeof(*bases), bases 378 drivers/gpu/host1x/syncpt.c if (!bases) bases 394 drivers/gpu/host1x/syncpt.c bases[i].id = i; bases 398 drivers/gpu/host1x/syncpt.c host->bases = bases; bases 101 drivers/iommu/rockchip-iommu.c void __iomem **bases; bases 290 drivers/iommu/rockchip-iommu.c writel(command, iommu->bases[i] + RK_MMU_COMMAND); bases 310 drivers/iommu/rockchip-iommu.c rk_iommu_write(iommu->bases[i], RK_MMU_ZAP_ONE_LINE, iova); bases 320 drivers/iommu/rockchip-iommu.c active &= !!(rk_iommu_read(iommu->bases[i], RK_MMU_STATUS) & bases 332 drivers/iommu/rockchip-iommu.c enable &= !!(rk_iommu_read(iommu->bases[i], RK_MMU_STATUS) & bases 344 drivers/iommu/rockchip-iommu.c done &= rk_iommu_read(iommu->bases[i], RK_MMU_DTE_ADDR) == 0; bases 369 drivers/iommu/rockchip-iommu.c rk_iommu_read(iommu->bases[i], RK_MMU_STATUS)); bases 390 drivers/iommu/rockchip-iommu.c rk_iommu_read(iommu->bases[i], RK_MMU_STATUS)); bases 411 drivers/iommu/rockchip-iommu.c rk_iommu_read(iommu->bases[i], RK_MMU_STATUS)); bases 432 drivers/iommu/rockchip-iommu.c rk_iommu_read(iommu->bases[i], RK_MMU_STATUS)); bases 451 drivers/iommu/rockchip-iommu.c rk_iommu_write(iommu->bases[i], RK_MMU_DTE_ADDR, DTE_ADDR_DUMMY); bases 453 drivers/iommu/rockchip-iommu.c dte_addr = rk_iommu_read(iommu->bases[i], RK_MMU_DTE_ADDR); bases 475 drivers/iommu/rockchip-iommu.c void __iomem *base = iommu->bases[index]; bases 537 drivers/iommu/rockchip-iommu.c int_status = rk_iommu_read(iommu->bases[i], RK_MMU_INT_STATUS); bases 542 drivers/iommu/rockchip-iommu.c iova = rk_iommu_read(iommu->bases[i], RK_MMU_PAGE_FAULT_ADDR); bases 547 drivers/iommu/rockchip-iommu.c status = rk_iommu_read(iommu->bases[i], RK_MMU_STATUS); bases 568 drivers/iommu/rockchip-iommu.c rk_iommu_base_command(iommu->bases[i], RK_MMU_CMD_ZAP_CACHE); bases 569 drivers/iommu/rockchip-iommu.c rk_iommu_base_command(iommu->bases[i], RK_MMU_CMD_PAGE_FAULT_DONE); bases 579 drivers/iommu/rockchip-iommu.c rk_iommu_write(iommu->bases[i], RK_MMU_INT_CLEAR, int_status); bases 854 drivers/iommu/rockchip-iommu.c rk_iommu_write(iommu->bases[i], RK_MMU_INT_MASK, 0); bases 855 drivers/iommu/rockchip-iommu.c rk_iommu_write(iommu->bases[i], RK_MMU_DTE_ADDR, 0); bases 881 drivers/iommu/rockchip-iommu.c rk_iommu_write(iommu->bases[i], RK_MMU_DTE_ADDR, bases 883 drivers/iommu/rockchip-iommu.c rk_iommu_base_command(iommu->bases[i], RK_MMU_CMD_ZAP_CACHE); bases 884 drivers/iommu/rockchip-iommu.c rk_iommu_write(iommu->bases[i], RK_MMU_INT_MASK, RK_MMU_IRQ_MASK); bases 1153 drivers/iommu/rockchip-iommu.c iommu->bases = devm_kcalloc(dev, num_res, sizeof(*iommu->bases), bases 1155 drivers/iommu/rockchip-iommu.c if (!iommu->bases) bases 1162 drivers/iommu/rockchip-iommu.c iommu->bases[i] = devm_ioremap_resource(&pdev->dev, res); bases 1163 drivers/iommu/rockchip-iommu.c if (IS_ERR(iommu->bases[i])) bases 1168 drivers/iommu/rockchip-iommu.c return PTR_ERR(iommu->bases[0]); bases 82 drivers/net/wireless/broadcom/b43/pio.c static const u16 bases[] = { bases 105 drivers/net/wireless/broadcom/b43/pio.c B43_WARN_ON(index >= ARRAY_SIZE(bases)); bases 106 drivers/net/wireless/broadcom/b43/pio.c return bases[index]; bases 123 include/linux/posix-timers.h struct posix_cputimer_base bases[CPUCLOCK_MAX]; bases 131 include/linux/posix-timers.h pct->bases[0].nextevt = U64_MAX; bases 132 include/linux/posix-timers.h pct->bases[1].nextevt = U64_MAX; bases 133 include/linux/posix-timers.h pct->bases[2].nextevt = U64_MAX; bases 141 include/linux/posix-timers.h pct->bases[CPUCLOCK_SCHED].nextevt = runtime; bases 157 include/linux/posix-timers.h .bases = INIT_CPU_TIMERBASES(s.posix_cputimers.bases), \ bases 27 kernel/time/posix-cpu-timers.c pct->bases[CPUCLOCK_PROF].nextevt = cpu_limit * NSEC_PER_SEC; bases 157 kernel/time/posix-cpu-timers.c return !(~pct->bases[CPUCLOCK_PROF].nextevt | bases 158 kernel/time/posix-cpu-timers.c ~pct->bases[CPUCLOCK_VIRT].nextevt | bases 159 kernel/time/posix-cpu-timers.c ~pct->bases[CPUCLOCK_SCHED].nextevt); bases 464 kernel/time/posix-cpu-timers.c cleanup_timerqueue(&pct->bases[CPUCLOCK_PROF].tqhead); bases 465 kernel/time/posix-cpu-timers.c cleanup_timerqueue(&pct->bases[CPUCLOCK_VIRT].tqhead); bases 466 kernel/time/posix-cpu-timers.c cleanup_timerqueue(&pct->bases[CPUCLOCK_SCHED].tqhead); bases 496 kernel/time/posix-cpu-timers.c base = p->posix_cputimers.bases + clkidx; bases 498 kernel/time/posix-cpu-timers.c base = p->signal->posix_cputimers.bases + clkidx; bases 790 kernel/time/posix-cpu-timers.c struct posix_cputimer_base *base = pct->bases; bases 936 kernel/time/posix-cpu-timers.c &pct->bases[CPUCLOCK_PROF].nextevt, bases 939 kernel/time/posix-cpu-timers.c &pct->bases[CPUCLOCK_VIRT].nextevt, bases 962 kernel/time/posix-cpu-timers.c if (softns < pct->bases[CPUCLOCK_PROF].nextevt) bases 963 kernel/time/posix-cpu-timers.c pct->bases[CPUCLOCK_PROF].nextevt = softns; bases 1046 kernel/time/posix-cpu-timers.c if (samples[i] >= pct->bases[i].nextevt) bases 1186 kernel/time/posix-cpu-timers.c nextevt = &tsk->signal->posix_cputimers.bases[clkid].nextevt; bases 249 sound/pci/hda/hda_proc.c static const char * const bases[7] = { bases 266 sound/pci/hda/hda_proc.c return bases[cfg & 0x0f]; bases 2390 sound/soc/codecs/wm_adsp.c __be32 bases[] = { xm_base, xm_base, ym_base, ym_base }; bases 2392 sound/soc/codecs/wm_adsp.c return wm_adsp_create_regions(dsp, id, ARRAY_SIZE(types), types, bases);