base_offset 186 arch/ia64/mm/discontig.c unsigned long base_offset; base_offset 201 arch/ia64/mm/discontig.c base_offset = (void *)__per_cpu_start - base; base_offset 244 arch/ia64/mm/discontig.c gi->base_offset = __per_cpu_offset[cpu] + base_offset; base_offset 1063 arch/x86/lib/insn-eval.c int *base_offset, long *eff_addr) base_offset 1084 arch/x86/lib/insn-eval.c *base_offset = get_reg_offset(insn, regs, REG_TYPE_BASE); base_offset 1092 arch/x86/lib/insn-eval.c if (*base_offset == -EDOM) base_offset 1094 arch/x86/lib/insn-eval.c else if (*base_offset < 0) base_offset 1097 arch/x86/lib/insn-eval.c base = regs_get_register(regs, *base_offset); base_offset 338 drivers/acpi/acpica/acutils.h u32 count, u32 display, u32 base_offset); base_offset 34 drivers/acpi/acpica/utbuffer.c void acpi_ut_dump_buffer(u8 *buffer, u32 count, u32 display, u32 base_offset) base_offset 56 drivers/acpi/acpica/utbuffer.c acpi_os_printf("%8.4X: ", (base_offset + i)); base_offset 200 drivers/acpi/acpica/utbuffer.c u8 *buffer, u32 count, u32 display, u32 base_offset) base_offset 222 drivers/acpi/acpica/utbuffer.c fprintf(file, "%8.4X: ", (base_offset + i)); base_offset 2392 drivers/acpi/nfit/core.c return mmio->base_offset + line_offset + table_offset + sub_line_offset; base_offset 2442 drivers/acpi/nfit/core.c u64 base_offset; base_offset 2445 drivers/acpi/nfit/core.c base_offset = nfit_blk->bdw_offset + dpa % L1_CACHE_BYTES base_offset 2455 drivers/acpi/nfit/core.c offset = to_interleave_offset(base_offset + copied, base_offset 2460 drivers/acpi/nfit/core.c offset = base_offset + nfit_blk->bdw_offset; base_offset 2586 drivers/acpi/nfit/core.c mmio->base_offset = nfit_mem->memdev_bdw->region_offset; base_offset 2609 drivers/acpi/nfit/core.c mmio->base_offset = nfit_mem->memdev_dcr->region_offset; base_offset 269 drivers/acpi/nfit/nfit.h u64 base_offset; base_offset 484 drivers/bus/fsl-mc/dprc.c region_desc->base_offset = le64_to_cpu(rsp_params->base_offset); base_offset 497 drivers/bus/fsl-mc/fsl-mc-bus.c region_desc.base_offset; base_offset 500 drivers/bus/fsl-mc/fsl-mc-bus.c region_desc.base_offset, base_offset 506 drivers/bus/fsl-mc/fsl-mc-bus.c region_desc.base_offset, base_offset 205 drivers/bus/fsl-mc/fsl-mc-private.h __le64 base_offset; base_offset 371 drivers/bus/fsl-mc/fsl-mc-private.h u32 base_offset; base_offset 99 drivers/counter/104-quad-8.c const int base_offset = priv->base + 2 * chan->channel; base_offset 113 drivers/counter/104-quad-8.c flags = inb(base_offset + 1); base_offset 124 drivers/counter/104-quad-8.c base_offset + 1); base_offset 127 drivers/counter/104-quad-8.c *val |= (unsigned int)inb(base_offset) << (8 * i); base_offset 148 drivers/counter/104-quad-8.c const int base_offset = priv->base + 2 * chan->channel; base_offset 164 drivers/counter/104-quad-8.c outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, base_offset + 1); base_offset 168 drivers/counter/104-quad-8.c outb(val >> (8 * i), base_offset); base_offset 171 drivers/counter/104-quad-8.c outb(QUAD8_CTR_RLD | QUAD8_RLD_PRESET_CNTR, base_offset + 1); base_offset 174 drivers/counter/104-quad-8.c outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, base_offset + 1); base_offset 179 drivers/counter/104-quad-8.c outb(val >> (8 * i), base_offset); base_offset 182 drivers/counter/104-quad-8.c outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_FLAGS, base_offset + 1); base_offset 184 drivers/counter/104-quad-8.c outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_E, base_offset + 1); base_offset 201 drivers/counter/104-quad-8.c outb(QUAD8_CTR_IOR | ior_cfg, base_offset + 1); base_offset 260 drivers/counter/104-quad-8.c const int base_offset = priv->base + 2 * chan->channel; base_offset 278 drivers/counter/104-quad-8.c outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, base_offset + 1); base_offset 282 drivers/counter/104-quad-8.c outb(preset >> (8 * i), base_offset); base_offset 303 drivers/counter/104-quad-8.c const int base_offset = priv->base + 2 * chan->channel + 1; base_offset 323 drivers/counter/104-quad-8.c outb(QUAD8_CTR_IOR | ior_cfg, base_offset); base_offset 339 drivers/counter/104-quad-8.c const int base_offset = priv->base + 2 * chan->channel + 1; base_offset 341 drivers/counter/104-quad-8.c return !!(inb(base_offset) & QUAD8_FLAG_E); base_offset 359 drivers/counter/104-quad-8.c const int base_offset = priv->base + 2 * chan->channel + 1; base_offset 361 drivers/counter/104-quad-8.c return !!(inb(base_offset) & QUAD8_FLAG_UD); base_offset 382 drivers/counter/104-quad-8.c const int base_offset = priv->base + 2 * chan->channel + 1; base_offset 393 drivers/counter/104-quad-8.c outb(QUAD8_CTR_CMR | mode_cfg, base_offset); base_offset 424 drivers/counter/104-quad-8.c const int base_offset = priv->base + 2 * chan->channel + 1; base_offset 440 drivers/counter/104-quad-8.c outb(QUAD8_CTR_IDR | idr_cfg, base_offset); base_offset 471 drivers/counter/104-quad-8.c const int base_offset = priv->base + 2 * chan->channel + 1; base_offset 492 drivers/counter/104-quad-8.c outb(QUAD8_CTR_CMR | mode_cfg, base_offset); base_offset 523 drivers/counter/104-quad-8.c const int base_offset = priv->base + 2 * chan->channel + 1; base_offset 533 drivers/counter/104-quad-8.c outb(QUAD8_CTR_IDR | idr_cfg, base_offset); base_offset 641 drivers/counter/104-quad-8.c const int base_offset = priv->base + 2 * count->id; base_offset 648 drivers/counter/104-quad-8.c flags = inb(base_offset + 1); base_offset 659 drivers/counter/104-quad-8.c base_offset + 1); base_offset 662 drivers/counter/104-quad-8.c position |= (unsigned long)inb(base_offset) << (8 * i); base_offset 675 drivers/counter/104-quad-8.c const int base_offset = priv->base + 2 * count->id; base_offset 692 drivers/counter/104-quad-8.c outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, base_offset + 1); base_offset 696 drivers/counter/104-quad-8.c outb(position >> (8 * i), base_offset); base_offset 699 drivers/counter/104-quad-8.c outb(QUAD8_CTR_RLD | QUAD8_RLD_PRESET_CNTR, base_offset + 1); base_offset 702 drivers/counter/104-quad-8.c outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, base_offset + 1); base_offset 707 drivers/counter/104-quad-8.c outb(position >> (8 * i), base_offset); base_offset 710 drivers/counter/104-quad-8.c outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_FLAGS, base_offset + 1); base_offset 712 drivers/counter/104-quad-8.c outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_E, base_offset + 1); base_offset 769 drivers/counter/104-quad-8.c const int base_offset = priv->base + 2 * id + 1; base_offset 788 drivers/counter/104-quad-8.c outb(QUAD8_CTR_IDR | idr_cfg, base_offset); base_offset 810 drivers/counter/104-quad-8.c outb(QUAD8_CTR_CMR | mode_cfg, base_offset); base_offset 930 drivers/counter/104-quad-8.c const int base_offset = priv->base + 2 * channel_id + 1; base_offset 940 drivers/counter/104-quad-8.c outb(QUAD8_CTR_IDR | idr_cfg, base_offset); base_offset 970 drivers/counter/104-quad-8.c const int base_offset = priv->base + 2 * channel_id + 1; base_offset 986 drivers/counter/104-quad-8.c outb(QUAD8_CTR_IDR | idr_cfg, base_offset); base_offset 1036 drivers/counter/104-quad-8.c const int base_offset = priv->base + 2 * count->id + 1; base_offset 1066 drivers/counter/104-quad-8.c outb(QUAD8_CTR_CMR | mode_cfg, base_offset); base_offset 1102 drivers/counter/104-quad-8.c const int base_offset = priv->base + 2 * count->id; base_offset 1118 drivers/counter/104-quad-8.c outb(QUAD8_CTR_IOR | ior_cfg, base_offset + 1); base_offset 1129 drivers/counter/104-quad-8.c const int base_offset = priv->base + 2 * count->id + 1; base_offset 1131 drivers/counter/104-quad-8.c *noise_error = !!(inb(base_offset) & QUAD8_FLAG_E); base_offset 1153 drivers/counter/104-quad-8.c const unsigned int base_offset = quad8iio->base + 2 * id; base_offset 1159 drivers/counter/104-quad-8.c outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, base_offset + 1); base_offset 1163 drivers/counter/104-quad-8.c outb(preset >> (8 * i), base_offset); base_offset 1253 drivers/counter/104-quad-8.c const int base_offset = priv->base + 2 * count->id + 1; base_offset 1272 drivers/counter/104-quad-8.c outb(QUAD8_CTR_IOR | ior_cfg, base_offset); base_offset 1412 drivers/counter/104-quad-8.c unsigned int base_offset; base_offset 1453 drivers/counter/104-quad-8.c base_offset = base[id] + 2 * i; base_offset 1455 drivers/counter/104-quad-8.c outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, base_offset + 1); base_offset 1458 drivers/counter/104-quad-8.c outb(0x00, base_offset); base_offset 1460 drivers/counter/104-quad-8.c outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_FLAGS, base_offset + 1); base_offset 1462 drivers/counter/104-quad-8.c outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_E, base_offset + 1); base_offset 1464 drivers/counter/104-quad-8.c outb(QUAD8_CTR_CMR, base_offset + 1); base_offset 1466 drivers/counter/104-quad-8.c outb(QUAD8_CTR_IOR, base_offset + 1); base_offset 1468 drivers/counter/104-quad-8.c outb(QUAD8_CTR_IDR, base_offset + 1); base_offset 110 drivers/dma/qcom/bam_dma.c u32 base_offset; base_offset 413 drivers/dma/qcom/bam_dma.c return bdev->regs + r.base_offset + base_offset 69 drivers/gpio/gpio-104-idi-48.c unsigned base_offset; base_offset 74 drivers/gpio/gpio-104-idi-48.c base_offset = register_offset[i / 8]; base_offset 77 drivers/gpio/gpio-104-idi-48.c return !!(inb(idi48gpio->base + base_offset) & mask); base_offset 63 drivers/gpu/drm/i915/display/intel_dsi_vbt.c #define VLV_GPIO_PCONF0(base_offset) (base_offset) base_offset 64 drivers/gpu/drm/i915/display/intel_dsi_vbt.c #define VLV_GPIO_PAD_VAL(base_offset) ((base_offset) + 8) base_offset 67 drivers/gpu/drm/i915/display/intel_dsi_vbt.c u16 base_offset; base_offset 246 drivers/gpu/drm/i915/display/intel_dsi_vbt.c pconf0 = VLV_GPIO_PCONF0(map->base_offset); base_offset 247 drivers/gpu/drm/i915/display/intel_dsi_vbt.c padval = VLV_GPIO_PAD_VAL(map->base_offset); base_offset 355 drivers/gpu/drm/radeon/r600_cs.c u64 base_offset, base_align; base_offset 380 drivers/gpu/drm/radeon/r600_cs.c base_offset = track->cb_color_bo_mc[i] + track->cb_color_bo_offset[i]; base_offset 423 drivers/gpu/drm/radeon/r600_cs.c if (!IS_ALIGNED(base_offset, base_align)) { base_offset 425 drivers/gpu/drm/radeon/r600_cs.c base_offset, base_align, array_mode); base_offset 524 drivers/gpu/drm/radeon/r600_cs.c u64 base_offset, base_align; base_offset 575 drivers/gpu/drm/radeon/r600_cs.c base_offset = track->db_bo_mc + track->db_offset; base_offset 614 drivers/gpu/drm/radeon/r600_cs.c if (!IS_ALIGNED(base_offset, base_align)) { base_offset 616 drivers/gpu/drm/radeon/r600_cs.c base_offset, base_align, array_mode); base_offset 1472 drivers/gpu/drm/radeon/r600_cs.c u64 base_offset, base_offset 1491 drivers/gpu/drm/radeon/r600_cs.c base_offset <<= 8; base_offset 1569 drivers/gpu/drm/radeon/r600_cs.c if (!IS_ALIGNED(base_offset, base_align)) { base_offset 1571 drivers/gpu/drm/radeon/r600_cs.c __func__, __LINE__, base_offset, base_align, G_038000_TILE_MODE(word0)); base_offset 1955 drivers/gpu/drm/radeon/r600_cs.c u32 size, offset, base_offset, mip_offset; base_offset 1965 drivers/gpu/drm/radeon/r600_cs.c base_offset = (u32)((reloc->gpu_offset >> 8) & 0xffffffff); base_offset 1983 drivers/gpu/drm/radeon/r600_cs.c base_offset + radeon_get_ib_value(p, idx+1+(i*7)+2), base_offset 1988 drivers/gpu/drm/radeon/r600_cs.c ib[idx+1+(i*7)+2] += base_offset; base_offset 29 drivers/net/dsa/bcm_sf2_cfp.c u32 base_offset; base_offset 58 drivers/net/dsa/bcm_sf2_cfp.c .base_offset = CORE_UDF_0_A_0_8_PORT_0 + UDF_SLICE_OFFSET, base_offset 88 drivers/net/dsa/bcm_sf2_cfp.c .base_offset = CORE_UDF_0_B_0_8_PORT_0, base_offset 112 drivers/net/dsa/bcm_sf2_cfp.c .base_offset = CORE_UDF_0_D_0_11_PORT_0, base_offset 159 drivers/net/dsa/bcm_sf2_cfp.c u32 offset = layout->udfs[slice_num].base_offset; base_offset 945 drivers/net/ethernet/brocade/bna/bnad_ethtool.c u32 *base_offset) base_offset 979 drivers/net/ethernet/brocade/bna/bnad_ethtool.c *base_offset = flash_attr->part[i].part_off; base_offset 1000 drivers/net/ethernet/brocade/bna/bnad_ethtool.c u32 flash_part = 0, base_offset = 0; base_offset 1009 drivers/net/ethernet/brocade/bna/bnad_ethtool.c eeprom->offset, &base_offset); base_offset 1020 drivers/net/ethernet/brocade/bna/bnad_ethtool.c eeprom->offset - base_offset, base_offset 1040 drivers/net/ethernet/brocade/bna/bnad_ethtool.c u32 flash_part = 0, base_offset = 0; base_offset 1051 drivers/net/ethernet/brocade/bna/bnad_ethtool.c eeprom->offset, &base_offset); base_offset 1062 drivers/net/ethernet/brocade/bna/bnad_ethtool.c eeprom->offset - base_offset, base_offset 173 drivers/net/ethernet/intel/ice/ice_flex_type.h __le16 base_offset; base_offset 776 drivers/net/ethernet/seeq/ether3.c ec->irqaddr = priv(dev)->base + data->base_offset; base_offset 779 drivers/net/ethernet/seeq/ether3.c priv(dev)->seeq = priv(dev)->base + data->base_offset; base_offset 860 drivers/net/ethernet/seeq/ether3.c .base_offset = 0, base_offset 865 drivers/net/ethernet/seeq/ether3.c .base_offset = 0x800, base_offset 171 drivers/net/ethernet/seeq/ether3.h unsigned long base_offset; base_offset 549 drivers/nubus/nubus.c u32 base_offset; base_offset 551 drivers/nubus/nubus.c nubus_get_rsrc_mem(&base_offset, &ent, 4); base_offset 552 drivers/nubus/nubus.c pr_debug(" memory offset: 0x%08x\n", base_offset); base_offset 178 drivers/pci/hotplug/shpchp.h volatile u32 base_offset; base_offset 195 drivers/pci/hotplug/shpchp.h BASE_OFFSET = offsetof(struct ctrl_reg, base_offset), base_offset 279 drivers/scsi/aic7xxx/aic79xx_osm_pci.c u_long base_offset; base_offset 290 drivers/scsi/aic7xxx/aic79xx_osm_pci.c base_offset = start - base_page; base_offset 296 drivers/scsi/aic7xxx/aic79xx_osm_pci.c *maddr = ioremap_nocache(base_page, base_offset + 512); base_offset 301 drivers/scsi/aic7xxx/aic79xx_osm_pci.c *maddr += base_offset; base_offset 64 drivers/scsi/fdomain_isa.c int base_offset; base_offset 110 drivers/scsi/fdomain_isa.c if (sig->base_offset) base_offset 111 drivers/scsi/fdomain_isa.c base = readb(p + sig->base_offset) + base_offset 112 drivers/scsi/fdomain_isa.c (readb(p + sig->base_offset + 1) << 8); base_offset 100 drivers/thunderbolt/tb_regs.h u32 base_offset:8; /* base_offset 357 drivers/xen/xen-pciback/conf_space.c unsigned int base_offset) base_offset 372 drivers/xen/xen-pciback/conf_space.c cfg_entry->base_offset = base_offset; base_offset 64 drivers/xen/xen-pciback/conf_space.h unsigned int base_offset; base_offset 70 drivers/xen/xen-pciback/conf_space.h #define OFFSET(cfg_entry) ((cfg_entry)->base_offset+(cfg_entry)->field->offset) base_offset 1357 drivers/xen/xen-pciback/pci_stub.c cfg_entry->base_offset + base_offset 74 include/dt-bindings/pinctrl/omap.h #define OMAP_PADCONF_OFFSET(offset, base_offset) ((offset) - (base_offset)) base_offset 70 include/linux/percpu.h unsigned long base_offset; /* base address offset */ base_offset 10 include/net/netfilter/nf_tables_offload.h u32 base_offset; base_offset 70 include/net/netfilter/nf_tables_offload.h (__reg)->base_offset = \ base_offset 2350 mm/percpu.c group_offsets[group] = gi->base_offset; base_offset 2363 mm/percpu.c unit_off[cpu] = gi->base_offset + i * ai->unit_size; base_offset 2651 mm/percpu.c gi->base_offset = unit * ai->unit_size; base_offset 2787 mm/percpu.c ai->groups[group].base_offset = areas[group] - base; base_offset 132 net/netfilter/nft_cmp.c flow->match.dissector.offset[reg->key] = reg->base_offset; base_offset 74 scripts/dtc/include-prefixes/dt-bindings/pinctrl/omap.h #define OMAP_PADCONF_OFFSET(offset, base_offset) ((offset) - (base_offset)) base_offset 60 sound/firewire/dice/dice-extension.c u32 base_offset, unsigned int stream_count, base_offset 71 sound/firewire/dice/dice-extension.c entry_offset = base_offset + i * EXT_APP_STREAM_ENTRY_SIZE; base_offset 86 sound/firewire/dice/dice-extension.c u32 base_offset; base_offset 110 sound/firewire/dice/dice-extension.c base_offset = 0x2000 * mode + 0x1000; base_offset 113 sound/firewire/dice/dice-extension.c base_offset + EXT_APP_STREAM_TX_NUMBER, base_offset 118 sound/firewire/dice/dice-extension.c base_offset += EXT_APP_STREAM_ENTRIES; base_offset 120 sound/firewire/dice/dice-extension.c err = read_stream_entries(dice, section_addr, base_offset, base_offset 127 sound/firewire/dice/dice-extension.c base_offset += stream_count * EXT_APP_STREAM_ENTRY_SIZE; base_offset 129 sound/firewire/dice/dice-extension.c err = read_stream_entries(dice, section_addr, base_offset, base_offset 500 sound/soc/codecs/wm_adsp.c unsigned int base_offset; base_offset 507 sound/soc/codecs/wm_adsp.c .base_offset = HOST_BUFFER_FIELD(buf1_base), base_offset 512 sound/soc/codecs/wm_adsp.c .base_offset = HOST_BUFFER_FIELD(buf2_base), base_offset 517 sound/soc/codecs/wm_adsp.c .base_offset = HOST_BUFFER_FIELD(buf3_base), base_offset 3647 sound/soc/codecs/wm_adsp.c ret = wm_adsp_buffer_read(buf, caps->region_defs[i].base_offset, base_offset 160 tools/perf/util/genelf.c uint64_t unwinding_size, uint64_t base_offset) base_offset 197 tools/perf/util/genelf.c shdr->sh_addr = base_offset; base_offset 231 tools/perf/util/genelf.c shdr->sh_addr = base_offset + unwinding_table_size; base_offset 470 tools/testing/selftests/x86/fsgsbase.c unsigned long base_offset = USER_REGS_OFFSET(gs_base); base_offset 480 tools/testing/selftests/x86/fsgsbase.c if (ptrace(PTRACE_POKEUSER, child, base_offset, 0xFF) != 0) base_offset 484 tools/testing/selftests/x86/fsgsbase.c base = ptrace(PTRACE_PEEKUSER, child, base_offset, NULL);