base_dma          477 drivers/crypto/inside-secure/safexcel.c 		writel(lower_32_bits(priv->ring[i].cdr.base_dma),
base_dma          479 drivers/crypto/inside-secure/safexcel.c 		writel(upper_32_bits(priv->ring[i].cdr.base_dma),
base_dma          525 drivers/crypto/inside-secure/safexcel.c 		writel(lower_32_bits(priv->ring[i].rdr.base_dma),
base_dma          527 drivers/crypto/inside-secure/safexcel.c 		writel(upper_32_bits(priv->ring[i].rdr.base_dma),
base_dma          582 drivers/crypto/inside-secure/safexcel.h 	dma_addr_t base_dma;
base_dma           20 drivers/crypto/inside-secure/safexcel_ring.c 					&cdr->base_dma, GFP_KERNEL);
base_dma           30 drivers/crypto/inside-secure/safexcel_ring.c 					&rdr->base_dma, GFP_KERNEL);
base_dma          510 drivers/iommu/arm-smmu-v3.c 	dma_addr_t			base_dma;
base_dma          929 drivers/iommu/arm-smmu-v3.c 		ent.sync.msiaddr = q->base_dma + Q_IDX(&q->llq, prod) *
base_dma         2756 drivers/iommu/arm-smmu-v3.c 		q->base = dmam_alloc_coherent(smmu->dev, qsz, &q->base_dma,
base_dma         2771 drivers/iommu/arm-smmu-v3.c 	if (!WARN_ON(q->base_dma & (qsz - 1))) {
base_dma         2781 drivers/iommu/arm-smmu-v3.c 	q->q_base |= q->base_dma & Q_BASE_ADDR_MASK;
base_dma          367 drivers/mtd/nand/raw/qcom_nandc.c 	dma_addr_t base_dma;
base_dma          930 drivers/mtd/nand/raw/qcom_nandc.c 		slave_conf.src_addr = nandc->base_dma + reg_off;
base_dma          934 drivers/mtd/nand/raw/qcom_nandc.c 		slave_conf.dst_addr = nandc->base_dma + reg_off;
base_dma         2939 drivers/mtd/nand/raw/qcom_nandc.c 	nandc->base_dma = dma_map_resource(dev, res->start,
base_dma         2942 drivers/mtd/nand/raw/qcom_nandc.c 	if (!nandc->base_dma)
base_dma         2995 drivers/mtd/nand/raw/qcom_nandc.c 	dma_unmap_resource(&pdev->dev, nandc->base_dma, resource_size(res),