base_clk 42 drivers/clk/sunxi/clk-a10-pll2.c struct clk **clks, *base_clk, *prediv_clk; base_clk 95 drivers/clk/sunxi/clk-a10-pll2.c base_clk = clk_register_composite(NULL, "pll2-base", base_clk 101 drivers/clk/sunxi/clk-a10-pll2.c if (IS_ERR(base_clk)) { base_clk 106 drivers/clk/sunxi/clk-a10-pll2.c parent = __clk_get_name(base_clk); base_clk 48 drivers/mmc/host/sdhci-pic32.c struct clk *base_clk; base_clk 55 drivers/mmc/host/sdhci-pic32.c return clk_get_rate(sdhci_pdata->base_clk); base_clk 179 drivers/mmc/host/sdhci-pic32.c sdhci_pdata->base_clk = devm_clk_get(&pdev->dev, "base_clk"); base_clk 180 drivers/mmc/host/sdhci-pic32.c if (IS_ERR(sdhci_pdata->base_clk)) { base_clk 181 drivers/mmc/host/sdhci-pic32.c ret = PTR_ERR(sdhci_pdata->base_clk); base_clk 186 drivers/mmc/host/sdhci-pic32.c ret = clk_prepare_enable(sdhci_pdata->base_clk); base_clk 210 drivers/mmc/host/sdhci-pic32.c clk_disable_unprepare(sdhci_pdata->base_clk); base_clk 228 drivers/mmc/host/sdhci-pic32.c clk_disable_unprepare(sdhci_pdata->base_clk); base_clk 190 drivers/mmc/host/sdhci-sprd.c static inline u32 sdhci_sprd_calc_div(u32 base_clk, u32 clk) base_clk 195 drivers/mmc/host/sdhci-sprd.c if (base_clk <= clk * 2) base_clk 198 drivers/mmc/host/sdhci-sprd.c div = (u32) (base_clk / (clk * 2)); base_clk 200 drivers/mmc/host/sdhci-sprd.c if ((base_clk / div) > (clk * 2)) base_clk 88 drivers/pwm/pwm-samsung.c struct clk *base_clk; base_clk 158 drivers/pwm/pwm-samsung.c rate = clk_get_rate(chip->base_clk); base_clk 549 drivers/pwm/pwm-samsung.c chip->base_clk = devm_clk_get(&pdev->dev, "timers"); base_clk 550 drivers/pwm/pwm-samsung.c if (IS_ERR(chip->base_clk)) { base_clk 552 drivers/pwm/pwm-samsung.c return PTR_ERR(chip->base_clk); base_clk 555 drivers/pwm/pwm-samsung.c ret = clk_prepare_enable(chip->base_clk); base_clk 574 drivers/pwm/pwm-samsung.c clk_disable_unprepare(chip->base_clk); base_clk 579 drivers/pwm/pwm-samsung.c clk_get_rate(chip->base_clk), base_clk 595 drivers/pwm/pwm-samsung.c clk_disable_unprepare(chip->base_clk); base_clk 195 drivers/spi/spi-bcm-qspi.c u32 base_clk; base_clk 532 drivers/spi/spi-bcm-qspi.c spbr = qspi->base_clk / (2 * xp->speed_hz); base_clk 1346 drivers/spi/spi-bcm-qspi.c qspi->base_clk = clk_get_rate(qspi->clk); base_clk 1347 drivers/spi/spi-bcm-qspi.c qspi->max_speed_hz = qspi->base_clk / (QSPI_SPBR_MIN * 2); base_clk 141 drivers/spi/spi-pic32-sqi.c struct clk *base_clk; /* drives spi clock */ base_clk 170 drivers/spi/spi-pic32-sqi.c div = clk_get_rate(sqi->base_clk) / (2 * sck); base_clk 603 drivers/spi/spi-pic32-sqi.c sqi->base_clk = devm_clk_get(&pdev->dev, "spi_ck"); base_clk 604 drivers/spi/spi-pic32-sqi.c if (IS_ERR(sqi->base_clk)) { base_clk 605 drivers/spi/spi-pic32-sqi.c ret = PTR_ERR(sqi->base_clk); base_clk 616 drivers/spi/spi-pic32-sqi.c ret = clk_prepare_enable(sqi->base_clk); base_clk 645 drivers/spi/spi-pic32-sqi.c master->max_speed_hz = clk_get_rate(sqi->base_clk); base_clk 673 drivers/spi/spi-pic32-sqi.c clk_disable_unprepare(sqi->base_clk); base_clk 690 drivers/spi/spi-pic32-sqi.c clk_disable_unprepare(sqi->base_clk);