base_ch 1938 drivers/edac/sb_edac.c int sad_interl, idx, base_ch; base_ch 2127 drivers/edac/sb_edac.c base_ch = TAD_TGT0(reg); base_ch 2130 drivers/edac/sb_edac.c base_ch = TAD_TGT1(reg); base_ch 2133 drivers/edac/sb_edac.c base_ch = TAD_TGT2(reg); base_ch 2136 drivers/edac/sb_edac.c base_ch = TAD_TGT3(reg); base_ch 2142 drivers/edac/sb_edac.c *channel_mask = 1 << base_ch; base_ch 2144 drivers/edac/sb_edac.c pci_read_config_dword(pvt->pci_tad[base_ch], tad_ch_nilv_offset[n_tads], &tad_offset); base_ch 2148 drivers/edac/sb_edac.c *channel_mask |= 1 << ((base_ch + 2) % 4); base_ch 2166 drivers/edac/sb_edac.c *channel_mask |= 1 << ((base_ch + 1) % 4); base_ch 2178 drivers/edac/sb_edac.c base_ch, base_ch 2200 drivers/edac/sb_edac.c pci_read_config_dword(pvt->pci_tad[base_ch], rir_way_limit[n_rir], ®); base_ch 2228 drivers/edac/sb_edac.c pci_read_config_dword(pvt->pci_tad[base_ch], rir_offset[n_rir][idx], ®);