base_align        187 drivers/gpu/drm/radeon/evergreen_cs.c 	unsigned long	base_align;
base_align        195 drivers/gpu/drm/radeon/evergreen_cs.c 	surf->base_align = surf->bpe;
base_align        210 drivers/gpu/drm/radeon/evergreen_cs.c 	surf->base_align = track->group_size;
base_align        233 drivers/gpu/drm/radeon/evergreen_cs.c 	surf->base_align = track->group_size;
base_align        275 drivers/gpu/drm/radeon/evergreen_cs.c 	surf->base_align = (palign / 8) * (halign / 8) * tileb;
base_align        438 drivers/gpu/drm/radeon/evergreen_cs.c 	if (offset & (surf.base_align - 1)) {
base_align        440 drivers/gpu/drm/radeon/evergreen_cs.c 			 __func__, __LINE__, id, offset, surf.base_align);
base_align        613 drivers/gpu/drm/radeon/evergreen_cs.c 	if (offset & (surf.base_align - 1)) {
base_align        615 drivers/gpu/drm/radeon/evergreen_cs.c 			 __func__, __LINE__, offset, surf.base_align);
base_align        632 drivers/gpu/drm/radeon/evergreen_cs.c 	if (offset & (surf.base_align - 1)) {
base_align        634 drivers/gpu/drm/radeon/evergreen_cs.c 			 __func__, __LINE__, offset, surf.base_align);
base_align        711 drivers/gpu/drm/radeon/evergreen_cs.c 	if (offset & (surf.base_align - 1)) {
base_align        713 drivers/gpu/drm/radeon/evergreen_cs.c 			 __func__, __LINE__, offset, surf.base_align);
base_align        727 drivers/gpu/drm/radeon/evergreen_cs.c 	if (offset & (surf.base_align - 1)) {
base_align        729 drivers/gpu/drm/radeon/evergreen_cs.c 			 __func__, __LINE__, offset, surf.base_align);
base_align        837 drivers/gpu/drm/radeon/evergreen_cs.c 	if (toffset & (surf.base_align - 1)) {
base_align        839 drivers/gpu/drm/radeon/evergreen_cs.c 			 __func__, __LINE__, toffset, surf.base_align);
base_align        842 drivers/gpu/drm/radeon/evergreen_cs.c 	if (surf.nsamples <= 1 && moffset & (surf.base_align - 1)) {
base_align        844 drivers/gpu/drm/radeon/evergreen_cs.c 			 __func__, __LINE__, moffset, surf.base_align);
base_align        253 drivers/gpu/drm/radeon/r600_cs.c 						u64 *base_align)
base_align        268 drivers/gpu/drm/radeon/r600_cs.c 		*base_align = 1;
base_align        274 drivers/gpu/drm/radeon/r600_cs.c 		*base_align = values->group_size;
base_align        282 drivers/gpu/drm/radeon/r600_cs.c 		*base_align = values->group_size;
base_align        290 drivers/gpu/drm/radeon/r600_cs.c 		*base_align = max(macro_tile_bytes,
base_align        355 drivers/gpu/drm/radeon/r600_cs.c 	u64 base_offset, base_align;
base_align        388 drivers/gpu/drm/radeon/r600_cs.c 					  &pitch_align, &height_align, &depth_align, &base_align)) {
base_align        423 drivers/gpu/drm/radeon/r600_cs.c 	if (!IS_ALIGNED(base_offset, base_align)) {
base_align        425 drivers/gpu/drm/radeon/r600_cs.c 			 base_offset, base_align, array_mode);
base_align        524 drivers/gpu/drm/radeon/r600_cs.c 	u64 base_offset, base_align;
base_align        584 drivers/gpu/drm/radeon/r600_cs.c 					&pitch_align, &height_align, &depth_align, &base_align)) {
base_align        614 drivers/gpu/drm/radeon/r600_cs.c 		if (!IS_ALIGNED(base_offset, base_align)) {
base_align        616 drivers/gpu/drm/radeon/r600_cs.c 					base_offset, base_align, array_mode);
base_align       1411 drivers/gpu/drm/radeon/r600_cs.c 			      unsigned block_align, unsigned height_align, unsigned base_align,
base_align       1448 drivers/gpu/drm/radeon/r600_cs.c 			offset = round_up(offset, base_align);
base_align       1481 drivers/gpu/drm/radeon/r600_cs.c 	u64 base_align;
base_align       1556 drivers/gpu/drm/radeon/r600_cs.c 					  &pitch_align, &height_align, &depth_align, &base_align)) {
base_align       1569 drivers/gpu/drm/radeon/r600_cs.c 	if (!IS_ALIGNED(base_offset, base_align)) {
base_align       1571 drivers/gpu/drm/radeon/r600_cs.c 			 __func__, __LINE__, base_offset, base_align, G_038000_TILE_MODE(word0));
base_align       1574 drivers/gpu/drm/radeon/r600_cs.c 	if (!IS_ALIGNED(mip_offset, base_align)) {
base_align       1576 drivers/gpu/drm/radeon/r600_cs.c 			 __func__, __LINE__, mip_offset, base_align, G_038000_TILE_MODE(word0));
base_align       1591 drivers/gpu/drm/radeon/r600_cs.c 			  pitch_align, height_align, base_align,
base_align       1599 drivers/gpu/drm/radeon/r600_cs.c 		dev_warn(p->dev, "alignments %d %d %d %lld\n", pitch, pitch_align, height_align, base_align);
base_align        171 drivers/net/ethernet/cisco/enic/vnic_dev.c 	ring->base_align = 512;
base_align        181 drivers/net/ethernet/cisco/enic/vnic_dev.c 	ring->size_unaligned = ring->size + ring->base_align;
base_align        207 drivers/net/ethernet/cisco/enic/vnic_dev.c 		ring->base_align);
base_align         64 drivers/net/ethernet/cisco/enic/vnic_dev.h 	size_t base_align;
base_align        198 drivers/scsi/fnic/vnic_dev.c 	ring->base_align = 512;
base_align        208 drivers/scsi/fnic/vnic_dev.c 	ring->size_unaligned = ring->size + ring->base_align;
base_align        235 drivers/scsi/fnic/vnic_dev.c 		ring->base_align);
base_align        100 drivers/scsi/fnic/vnic_dev.h 	size_t base_align;
base_align        203 drivers/scsi/snic/vnic_dev.c 	ring->base_align = 512;
base_align        213 drivers/scsi/snic/vnic_dev.c 	ring->size_unaligned = ring->size + ring->base_align;
base_align        239 drivers/scsi/snic/vnic_dev.c 		ring->base_align);
base_align         58 drivers/scsi/snic/vnic_dev.h 	size_t base_align;