bar2 44 arch/alpha/include/asm/core_irongate.h igcsr32 bar2; /* 0x18 - Power Management reg block */ bar2 32 drivers/gpu/drm/nouveau/include/nvkm/core/memory.h u64 (*bar2)(struct nvkm_memory *); bar2 60 drivers/gpu/drm/nouveau/include/nvkm/core/memory.h #define nvkm_memory_bar2(p) (p)->func->bar2(p) bar2 12 drivers/gpu/drm/nouveau/include/nvkm/subdev/bar.h bool bar2; bar2 56 drivers/gpu/drm/nouveau/nvkm/subdev/bar/base.c if (bar && bar->bar2) bar2 57 drivers/gpu/drm/nouveau/nvkm/subdev/bar/base.c return bar->func->bar2.vmm(bar); bar2 65 drivers/gpu/drm/nouveau/nvkm/subdev/bar/base.c if (bar && bar->bar2) { bar2 66 drivers/gpu/drm/nouveau/nvkm/subdev/bar/base.c bar->func->bar2.init(bar); bar2 67 drivers/gpu/drm/nouveau/nvkm/subdev/bar/base.c bar->func->bar2.wait(bar); bar2 75 drivers/gpu/drm/nouveau/nvkm/subdev/bar/base.c if (bar && bar->bar2) { bar2 76 drivers/gpu/drm/nouveau/nvkm/subdev/bar/base.c bar->func->bar2.fini(bar); bar2 77 drivers/gpu/drm/nouveau/nvkm/subdev/bar/base.c bar->bar2 = false; bar2 85 drivers/gpu/drm/nouveau/nvkm/subdev/bar/base.c if (bar && bar->subdev.oneinit && !bar->bar2 && bar->func->bar2.init) { bar2 86 drivers/gpu/drm/nouveau/nvkm/subdev/bar/base.c bar->func->bar2.init(bar); bar2 87 drivers/gpu/drm/nouveau/nvkm/subdev/bar/base.c bar->func->bar2.wait(bar); bar2 88 drivers/gpu/drm/nouveau/nvkm/subdev/bar/base.c bar->bar2 = true; bar2 51 drivers/gpu/drm/nouveau/nvkm/subdev/bar/g84.c .bar2.init = nv50_bar_bar2_init, bar2 52 drivers/gpu/drm/nouveau/nvkm/subdev/bar/g84.c .bar2.fini = nv50_bar_bar2_fini, bar2 53 drivers/gpu/drm/nouveau/nvkm/subdev/bar/g84.c .bar2.wait = nv50_bar_bar1_wait, bar2 54 drivers/gpu/drm/nouveau/nvkm/subdev/bar/g84.c .bar2.vmm = nv50_bar_bar2_vmm, bar2 131 drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.c if (bar->base.func->bar2.init) { bar2 184 drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.c .bar2.init = gf100_bar_bar2_init, bar2 185 drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.c .bar2.fini = gf100_bar_bar2_fini, bar2 186 drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.c .bar2.wait = gf100_bar_bar1_wait, bar2 187 drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.c .bar2.vmm = gf100_bar_bar2_vmm, bar2 54 drivers/gpu/drm/nouveau/nvkm/subdev/bar/gm107.c .bar2.init = gf100_bar_bar2_init, bar2 55 drivers/gpu/drm/nouveau/nvkm/subdev/bar/gm107.c .bar2.fini = gf100_bar_bar2_fini, bar2 56 drivers/gpu/drm/nouveau/nvkm/subdev/bar/gm107.c .bar2.wait = gm107_bar_bar2_wait, bar2 57 drivers/gpu/drm/nouveau/nvkm/subdev/bar/gm107.c .bar2.vmm = gf100_bar_bar2_vmm, bar2 91 drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.c nvkm_wr32(device, 0x00170c, 0x80000000 | bar->bar2->node->offset >> 4); bar2 151 drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.c ret = nvkm_gpuobj_new(device, 24, 16, false, bar->mem, &bar->bar2); bar2 155 drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.c nvkm_kmap(bar->bar2); bar2 156 drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.c nvkm_wo32(bar->bar2, 0x00, 0x7fc00000); bar2 157 drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.c nvkm_wo32(bar->bar2, 0x04, lower_32_bits(limit)); bar2 158 drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.c nvkm_wo32(bar->bar2, 0x08, lower_32_bits(start)); bar2 159 drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.c nvkm_wo32(bar->bar2, 0x0c, upper_32_bits(limit) << 24 | bar2 161 drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.c nvkm_wo32(bar->bar2, 0x10, 0x00000000); bar2 162 drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.c nvkm_wo32(bar->bar2, 0x14, 0x00000000); bar2 163 drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.c nvkm_done(bar->bar2); bar2 211 drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.c nvkm_gpuobj_del(&bar->bar2); bar2 243 drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.c .bar2.init = nv50_bar_bar2_init, bar2 244 drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.c .bar2.fini = nv50_bar_bar2_fini, bar2 245 drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.c .bar2.wait = nv50_bar_bar1_wait, bar2 246 drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.c .bar2.vmm = nv50_bar_bar2_vmm, bar2 16 drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.h struct nvkm_gpuobj *bar2; bar2 20 drivers/gpu/drm/nouveau/nvkm/subdev/bar/priv.h } bar1, bar2; bar2 87 drivers/gpu/drm/nouveau/nvkm/subdev/bar/tu102.c .bar2.init = tu102_bar_bar2_init, bar2 88 drivers/gpu/drm/nouveau/nvkm/subdev/bar/tu102.c .bar2.fini = tu102_bar_bar2_fini, bar2 89 drivers/gpu/drm/nouveau/nvkm/subdev/bar/tu102.c .bar2.wait = tu102_bar_bar2_wait, bar2 90 drivers/gpu/drm/nouveau/nvkm/subdev/bar/tu102.c .bar2.vmm = gf100_bar_bar2_vmm, bar2 341 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv50.c .bar2 = nv50_instobj_bar2, bar2 10382 drivers/net/ethernet/broadcom/bnxt/bnxt.c if (bp->bar2) { bar2 10383 drivers/net/ethernet/broadcom/bnxt/bnxt.c pci_iounmap(pdev, bp->bar2); bar2 10384 drivers/net/ethernet/broadcom/bnxt/bnxt.c bp->bar2 = NULL; bar2 10834 drivers/net/ethernet/broadcom/bnxt/bnxt.c bp->bar2 = pci_ioremap_bar(pdev, 4); bar2 10835 drivers/net/ethernet/broadcom/bnxt/bnxt.c if (!bp->bar2) { bar2 1406 drivers/net/ethernet/broadcom/bnxt/bnxt.h void __iomem *bar2; bar2 927 drivers/net/ethernet/chelsio/cxgb4/cxgb4.h void __iomem *bar2; bar2 2206 drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c adap->bar2 + bar2_qoffset + SGE_UDB_KDOORBELL); bar2 5829 drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c adapter->bar2 = ioremap_wc(pci_resource_start(pdev, 2), bar2 5831 drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c if (!adapter->bar2) { bar2 6113 drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c iounmap(adapter->bar2); bar2 6195 drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c iounmap(adapter->bar2); bar2 3505 drivers/net/ethernet/chelsio/cxgb4/sge.c return adapter->bar2 + bar2_qoffset; bar2 368 drivers/net/ethernet/chelsio/cxgb4vf/adapter.h void __iomem *bar2; bar2 3040 drivers/net/ethernet/chelsio/cxgb4vf/cxgb4vf_main.c adapter->bar2 = ioremap_wc(pci_resource_start(pdev, 2), bar2 3042 drivers/net/ethernet/chelsio/cxgb4vf/cxgb4vf_main.c if (!adapter->bar2) { bar2 3305 drivers/net/ethernet/chelsio/cxgb4vf/cxgb4vf_main.c iounmap(adapter->bar2); bar2 3382 drivers/net/ethernet/chelsio/cxgb4vf/cxgb4vf_main.c iounmap(adapter->bar2); bar2 2191 drivers/net/ethernet/chelsio/cxgb4vf/sge.c return adapter->bar2 + bar2_qoffset; bar2 663 drivers/net/ethernet/intel/ixgb/ixgb_hw.h u32 bar2; bar2 1791 sound/pci/ctxfi/cthw20k1.c unsigned int bar0, bar1, bar2, bar3, bar4, bar5; bar2 1839 sound/pci/ctxfi/cthw20k1.c pci_read_config_dword(pci, PCI_BASE_ADDRESS_2, &bar2); bar2 1857 sound/pci/ctxfi/cthw20k1.c pci_write_config_dword(pci, PCI_BASE_ADDRESS_2, bar2);