bar1_index        634 arch/mips/pci/pci-octeon.c 			union cvmx_pci_bar1_indexx bar1_index;
bar1_index        636 arch/mips/pci/pci-octeon.c 			bar1_index.u32 = 0;
bar1_index        638 arch/mips/pci/pci-octeon.c 			bar1_index.s.addr_idx =
bar1_index        641 arch/mips/pci/pci-octeon.c 			bar1_index.s.ca = 1;
bar1_index        643 arch/mips/pci/pci-octeon.c 			bar1_index.s.end_swp = 1;
bar1_index        645 arch/mips/pci/pci-octeon.c 			bar1_index.s.addr_v = 1;
bar1_index        647 arch/mips/pci/pci-octeon.c 					   bar1_index.u32);
bar1_index        670 arch/mips/pci/pci-octeon.c 			union cvmx_pci_bar1_indexx bar1_index;
bar1_index        672 arch/mips/pci/pci-octeon.c 			bar1_index.u32 = 0;
bar1_index        674 arch/mips/pci/pci-octeon.c 			bar1_index.s.addr_idx =
bar1_index        677 arch/mips/pci/pci-octeon.c 			bar1_index.s.ca = 1;
bar1_index        679 arch/mips/pci/pci-octeon.c 			bar1_index.s.end_swp = 1;
bar1_index        681 arch/mips/pci/pci-octeon.c 			bar1_index.s.addr_v = 1;
bar1_index        683 arch/mips/pci/pci-octeon.c 					   bar1_index.u32);
bar1_index        705 arch/mips/pci/pcie-octeon.c 	union cvmx_npei_bar1_indexx bar1_index;
bar1_index        925 arch/mips/pci/pcie-octeon.c 	bar1_index.u32 = 0;
bar1_index        926 arch/mips/pci/pcie-octeon.c 	bar1_index.s.addr_idx = (CVMX_PCIE_BAR1_PHYS_BASE >> 22);
bar1_index        927 arch/mips/pci/pcie-octeon.c 	bar1_index.s.ca = 1;	   /* Not Cached */
bar1_index        928 arch/mips/pci/pcie-octeon.c 	bar1_index.s.end_swp = 1;  /* Endian Swap mode */
bar1_index        929 arch/mips/pci/pcie-octeon.c 	bar1_index.s.addr_v = 1;   /* Valid entry */
bar1_index        941 arch/mips/pci/pcie-octeon.c 				    bar1_index.u32);
bar1_index        944 arch/mips/pci/pcie-octeon.c 		bar1_index.s.addr_idx += (((1ull << 28) / 16ull) >> 22);
bar1_index       1162 arch/mips/pci/pcie-octeon.c 	union cvmx_pemx_bar1_indexx bar1_index;
bar1_index       1408 arch/mips/pci/pcie-octeon.c 	bar1_index.u64 = 0;
bar1_index       1409 arch/mips/pci/pcie-octeon.c 	bar1_index.s.addr_idx = (CVMX_PCIE_BAR1_PHYS_BASE >> 22);
bar1_index       1410 arch/mips/pci/pcie-octeon.c 	bar1_index.s.ca = 1;	   /* Not Cached */
bar1_index       1411 arch/mips/pci/pcie-octeon.c 	bar1_index.s.end_swp = 1;  /* Endian Swap mode */
bar1_index       1412 arch/mips/pci/pcie-octeon.c 	bar1_index.s.addr_v = 1;   /* Valid entry */
bar1_index       1415 arch/mips/pci/pcie-octeon.c 		cvmx_write_csr(CVMX_PEMX_BAR1_INDEXX(i, pcie_port), bar1_index.u64);
bar1_index       1417 arch/mips/pci/pcie-octeon.c 		bar1_index.s.addr_idx += (((1ull << 28) / 16ull) >> 22);
bar1_index        557 drivers/net/ethernet/cavium/liquidio/octeon_console.c 	oct->console_nb_info.bar1_index = BAR1_INDEX_STATIC_MAP;
bar1_index        558 drivers/net/ethernet/cavium/liquidio/octeon_console.c 	oct->fn_list.bar1_idx_setup(oct, addr, oct->console_nb_info.bar1_index,
bar1_index        526 drivers/net/ethernet/cavium/liquidio/octeon_device.h 		int bar1_index;
bar1_index        105 drivers/net/ethernet/cavium/liquidio/octeon_mem_ops.c 		int bar1_index = oct->console_nb_info.bar1_index;
bar1_index        108 drivers/net/ethernet/cavium/liquidio/octeon_mem_ops.c 			+ (bar1_index << ilog2(OCTEON_BAR1_ENTRY_SIZE))