bankw            1971 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 		unsigned bankw, bankh, mtaspect, tile_split, num_banks;
bankw            1973 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 		bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
bankw            1984 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 		fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_WIDTH, bankw);
bankw            2013 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 		unsigned bankw, bankh, mtaspect, tile_split, num_banks;
bankw            2015 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 		bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
bankw            2026 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 		fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_WIDTH, bankw);
bankw            1918 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 		unsigned bankw, bankh, mtaspect, tile_split, num_banks;
bankw            1920 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 		bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
bankw            1929 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 		fb_format |= GRPH_BANK_WIDTH(bankw);
bankw            1892 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c 		unsigned bankw, bankh, mtaspect, tile_split, num_banks;
bankw            1894 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c 		bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
bankw            1903 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c 		fb_format |= (bankw << GRPH_CONTROL__GRPH_BANK_WIDTH__SHIFT);
bankw            2825 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 		unsigned int bankw, bankh, mtaspect, tile_split, num_banks;
bankw            2827 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 		bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
bankw            2838 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 		tiling_info->gfx8.bank_width = bankw;
bankw            1156 drivers/gpu/drm/radeon/atombios_crtc.c 	unsigned bankw, bankh, mtaspect, tile_split;
bankw            1277 drivers/gpu/drm/radeon/atombios_crtc.c 		evergreen_tiling_fields(tiling_flags, &bankw, &bankh, &mtaspect, &tile_split);
bankw            1343 drivers/gpu/drm/radeon/atombios_crtc.c 		fb_format |= EVERGREEN_GRPH_BANK_WIDTH(bankw);
bankw            1114 drivers/gpu/drm/radeon/evergreen.c void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
bankw            1118 drivers/gpu/drm/radeon/evergreen.c 	*bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK;
bankw            1122 drivers/gpu/drm/radeon/evergreen.c 	switch (*bankw) {
bankw            1124 drivers/gpu/drm/radeon/evergreen.c 	case 1: *bankw = EVERGREEN_ADDR_SURF_BANK_WIDTH_1; break;
bankw            1125 drivers/gpu/drm/radeon/evergreen.c 	case 2: *bankw = EVERGREEN_ADDR_SURF_BANK_WIDTH_2; break;
bankw            1126 drivers/gpu/drm/radeon/evergreen.c 	case 4: *bankw = EVERGREEN_ADDR_SURF_BANK_WIDTH_4; break;
bankw            1127 drivers/gpu/drm/radeon/evergreen.c 	case 8: *bankw = EVERGREEN_ADDR_SURF_BANK_WIDTH_8; break;
bankw             177 drivers/gpu/drm/radeon/evergreen_cs.c 	unsigned	bankw;
bankw             269 drivers/gpu/drm/radeon/evergreen_cs.c 	palign = (8 * surf->bankw * track->npipes) * surf->mtilea;
bankw             348 drivers/gpu/drm/radeon/evergreen_cs.c 	switch (surf->bankw) {
bankw             349 drivers/gpu/drm/radeon/evergreen_cs.c 	case 0: surf->bankw = 1; break;
bankw             350 drivers/gpu/drm/radeon/evergreen_cs.c 	case 1: surf->bankw = 2; break;
bankw             351 drivers/gpu/drm/radeon/evergreen_cs.c 	case 2: surf->bankw = 4; break;
bankw             352 drivers/gpu/drm/radeon/evergreen_cs.c 	case 3: surf->bankw = 8; break;
bankw             355 drivers/gpu/drm/radeon/evergreen_cs.c 			 __func__, __LINE__, prefix, surf->bankw);
bankw             411 drivers/gpu/drm/radeon/evergreen_cs.c 	surf.bankw = G_028C74_BANK_WIDTH(track->cb_color_attrib[id]);
bankw             487 drivers/gpu/drm/radeon/evergreen_cs.c 			surf.bankw, surf.bankh,
bankw             578 drivers/gpu/drm/radeon/evergreen_cs.c 	surf.bankw = G_028040_BANK_WIDTH(track->db_z_info);
bankw             675 drivers/gpu/drm/radeon/evergreen_cs.c 	surf.bankw = G_028040_BANK_WIDTH(track->db_z_info);
bankw             785 drivers/gpu/drm/radeon/evergreen_cs.c 	surf.bankw = G_03001C_BANK_WIDTH(texdw[7]);
bankw             923 drivers/gpu/drm/radeon/evergreen_cs.c 				surf.bankw, surf.bankh,
bankw            1183 drivers/gpu/drm/radeon/evergreen_cs.c 				unsigned bankw, bankh, mtaspect, tile_split;
bankw            1186 drivers/gpu/drm/radeon/evergreen_cs.c 							&bankw, &bankh, &mtaspect,
bankw            1190 drivers/gpu/drm/radeon/evergreen_cs.c 						DB_BANK_WIDTH(bankw) |
bankw            1447 drivers/gpu/drm/radeon/evergreen_cs.c 				unsigned bankw, bankh, mtaspect, tile_split;
bankw            1450 drivers/gpu/drm/radeon/evergreen_cs.c 							&bankw, &bankh, &mtaspect,
bankw            1454 drivers/gpu/drm/radeon/evergreen_cs.c 					   CB_BANK_WIDTH(bankw) |
bankw            1475 drivers/gpu/drm/radeon/evergreen_cs.c 				unsigned bankw, bankh, mtaspect, tile_split;
bankw            1478 drivers/gpu/drm/radeon/evergreen_cs.c 							&bankw, &bankh, &mtaspect,
bankw            1482 drivers/gpu/drm/radeon/evergreen_cs.c 					   CB_BANK_WIDTH(bankw) |
bankw            2364 drivers/gpu/drm/radeon/evergreen_cs.c 						unsigned bankw, bankh, mtaspect, tile_split;
bankw            2367 drivers/gpu/drm/radeon/evergreen_cs.c 									&bankw, &bankh, &mtaspect,
bankw            2371 drivers/gpu/drm/radeon/evergreen_cs.c 							TEX_BANK_WIDTH(bankw) |
bankw             352 drivers/gpu/drm/radeon/radeon.h extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
bankw             682 drivers/gpu/drm/radeon/radeon_object.c 		unsigned bankw, bankh, mtaspect, tilesplit, stilesplit;
bankw             684 drivers/gpu/drm/radeon/radeon_object.c 		bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK;
bankw             689 drivers/gpu/drm/radeon/radeon_object.c 		switch (bankw) {