avg_time_slots_per_mtp 2521 drivers/gpu/drm/amd/display/dc/core/dc_link.c 	struct fixed31_32 avg_time_slots_per_mtp;
avg_time_slots_per_mtp 2584 drivers/gpu/drm/amd/display/dc/core/dc_link.c 	avg_time_slots_per_mtp = dc_fixpt_div(pbn, pbn_per_slot);
avg_time_slots_per_mtp 2588 drivers/gpu/drm/amd/display/dc/core/dc_link.c 		avg_time_slots_per_mtp);
avg_time_slots_per_mtp 2601 drivers/gpu/drm/amd/display/dc/core/dc_link.c 	struct fixed31_32 avg_time_slots_per_mtp = dc_fixpt_from_int(0);
avg_time_slots_per_mtp 2616 drivers/gpu/drm/amd/display/dc/core/dc_link.c 		avg_time_slots_per_mtp);
avg_time_slots_per_mtp  714 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 	struct fixed31_32 avg_time_slots_per_mtp)
avg_time_slots_per_mtp  718 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 		avg_time_slots_per_mtp);
avg_time_slots_per_mtp  722 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 				avg_time_slots_per_mtp,
avg_time_slots_per_mtp  626 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 	struct fixed31_32 avg_time_slots_per_mtp)
avg_time_slots_per_mtp  630 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 		avg_time_slots_per_mtp);
avg_time_slots_per_mtp  634 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 				avg_time_slots_per_mtp,
avg_time_slots_per_mtp  544 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h 	struct fixed31_32 avg_time_slots_per_mtp);
avg_time_slots_per_mtp  148 drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h 		struct fixed31_32 avg_time_slots_per_mtp);
avg_time_slots_per_mtp   50 drivers/gpu/drm/amd/display/dc/virtual/virtual_stream_encoder.c 	struct fixed31_32 avg_time_slots_per_mtp) {}
avg_time_slots_per_mtp  164 drivers/gpu/drm/radeon/radeon_dp_mst.c static int radeon_dp_mst_set_vcp_size(struct radeon_encoder *mst, s64 avg_time_slots_per_mtp)
avg_time_slots_per_mtp  172 drivers/gpu/drm/radeon/radeon_dp_mst.c 	uint32_t x = drm_fixp2int(avg_time_slots_per_mtp);
avg_time_slots_per_mtp  173 drivers/gpu/drm/radeon/radeon_dp_mst.c 	uint32_t y = drm_fixp2int_ceil((avg_time_slots_per_mtp - x) << 26);
avg_time_slots_per_mtp  390 drivers/gpu/drm/radeon/radeon_dp_mst.c 	s64 fixed_pbn, fixed_pbn_per_slot, avg_time_slots_per_mtp;
avg_time_slots_per_mtp  457 drivers/gpu/drm/radeon/radeon_dp_mst.c 		avg_time_slots_per_mtp = drm_fixp_div(fixed_pbn, fixed_pbn_per_slot);
avg_time_slots_per_mtp  458 drivers/gpu/drm/radeon/radeon_dp_mst.c 		radeon_dp_mst_set_vcp_size(radeon_encoder, avg_time_slots_per_mtp);