root/arch/x86/include/asm/mpspec.h

INCLUDED FROM

DEFINITIONS

1. get_smp_config
2. early_get_smp_config
3. find_smp_config
4. e820__memblock_alloc_reserved_mpc_new
5. physids_coerce
6. physids_promote
7. physid_set_mask_of_physid

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 #ifndef _ASM_X86_MPSPEC_H
   3 #define _ASM_X86_MPSPEC_H
   4 
   5 
   6 #include <asm/mpspec_def.h>
   7 #include <asm/x86_init.h>
   8 #include <asm/apicdef.h>
   9 
  10 extern int pic_mode;
  11 
  12 #ifdef CONFIG_X86_32
  13 
  14 /*
  15  * Summit or generic (i.e. installer) kernels need lots of bus entries.
  16  * Maximum 256 PCI busses, plus 1 ISA bus in each of 4 cabinets.
  17  */
  18 #if CONFIG_BASE_SMALL == 0
  19 # define MAX_MP_BUSSES          260
  20 #else
  21 # define MAX_MP_BUSSES          32
  22 #endif
  23 
  24 #define MAX_IRQ_SOURCES         256
  25 
  26 extern unsigned int def_to_bigsmp;
  27 
  28 #else /* CONFIG_X86_64: */
  29 
  30 #define MAX_MP_BUSSES           256
  31 /* Each PCI slot may be a combo card with its own bus.  4 IRQ pins per slot. */
  32 #define MAX_IRQ_SOURCES         (MAX_MP_BUSSES * 4)
  33 
  34 #endif /* CONFIG_X86_64 */
  35 
  36 #ifdef CONFIG_EISA
  37 extern int mp_bus_id_to_type[MAX_MP_BUSSES];
  38 #endif
  39 
  40 extern DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
  41 
  42 extern unsigned int boot_cpu_physical_apicid;
  43 extern u8 boot_cpu_apic_version;
  44 extern unsigned long mp_lapic_addr;
  45 
  46 #ifdef CONFIG_X86_LOCAL_APIC
  47 extern int smp_found_config;
  48 #else
  49 # define smp_found_config 0
  50 #endif
  51 
  52 static inline void get_smp_config(void)
  53 {
  54         x86_init.mpparse.get_smp_config(0);
  55 }
  56 
  57 static inline void early_get_smp_config(void)
  58 {
  59         x86_init.mpparse.get_smp_config(1);
  60 }
  61 
  62 static inline void find_smp_config(void)
  63 {
  64         x86_init.mpparse.find_smp_config();
  65 }
  66 
  67 #ifdef CONFIG_X86_MPPARSE
  68 extern void e820__memblock_alloc_reserved_mpc_new(void);
  69 extern int enable_update_mptable;
  70 extern int default_mpc_apic_id(struct mpc_cpu *m);
  71 extern void default_smp_read_mpc_oem(struct mpc_table *mpc);
  72 # ifdef CONFIG_X86_IO_APIC
  73 extern void default_mpc_oem_bus_info(struct mpc_bus *m, char *str);
  74 # else
  75 #  define default_mpc_oem_bus_info NULL
  76 # endif
  77 extern void default_find_smp_config(void);
  78 extern void default_get_smp_config(unsigned int early);
  79 #else
  80 static inline void e820__memblock_alloc_reserved_mpc_new(void) { }
  81 #define enable_update_mptable 0
  82 #define default_mpc_apic_id NULL
  83 #define default_smp_read_mpc_oem NULL
  84 #define default_mpc_oem_bus_info NULL
  85 #define default_find_smp_config x86_init_noop
  86 #define default_get_smp_config x86_init_uint_noop
  87 #endif
  88 
  89 int generic_processor_info(int apicid, int version);
  90 
  91 #define PHYSID_ARRAY_SIZE       BITS_TO_LONGS(MAX_LOCAL_APIC)
  92 
  93 struct physid_mask {
  94         unsigned long mask[PHYSID_ARRAY_SIZE];
  95 };
  96 
  97 typedef struct physid_mask physid_mask_t;
  98 
  99 #define physid_set(physid, map)                 set_bit(physid, (map).mask)
 100 #define physid_clear(physid, map)               clear_bit(physid, (map).mask)
 101 #define physid_isset(physid, map)               test_bit(physid, (map).mask)
 102 #define physid_test_and_set(physid, map)                        \
 103         test_and_set_bit(physid, (map).mask)
 104 
 105 #define physids_and(dst, src1, src2)                                    \
 106         bitmap_and((dst).mask, (src1).mask, (src2).mask, MAX_LOCAL_APIC)
 107 
 108 #define physids_or(dst, src1, src2)                                     \
 109         bitmap_or((dst).mask, (src1).mask, (src2).mask, MAX_LOCAL_APIC)
 110 
 111 #define physids_clear(map)                                      \
 112         bitmap_zero((map).mask, MAX_LOCAL_APIC)
 113 
 114 #define physids_complement(dst, src)                            \
 115         bitmap_complement((dst).mask, (src).mask, MAX_LOCAL_APIC)
 116 
 117 #define physids_empty(map)                                      \
 118         bitmap_empty((map).mask, MAX_LOCAL_APIC)
 119 
 120 #define physids_equal(map1, map2)                               \
 121         bitmap_equal((map1).mask, (map2).mask, MAX_LOCAL_APIC)
 122 
 123 #define physids_weight(map)                                     \
 124         bitmap_weight((map).mask, MAX_LOCAL_APIC)
 125 
 126 #define physids_shift_right(d, s, n)                            \
 127         bitmap_shift_right((d).mask, (s).mask, n, MAX_LOCAL_APIC)
 128 
 129 #define physids_shift_left(d, s, n)                             \
 130         bitmap_shift_left((d).mask, (s).mask, n, MAX_LOCAL_APIC)
 131 
 132 static inline unsigned long physids_coerce(physid_mask_t *map)
 133 {
 134         return map->mask[0];
 135 }
 136 
 137 static inline void physids_promote(unsigned long physids, physid_mask_t *map)
 138 {
 139         physids_clear(*map);
 140         map->mask[0] = physids;
 141 }
 142 
 143 static inline void physid_set_mask_of_physid(int physid, physid_mask_t *map)
 144 {
 145         physids_clear(*map);
 146         physid_set(physid, *map);
 147 }
 148 
 149 #define PHYSID_MASK_ALL         { {[0 ... PHYSID_ARRAY_SIZE-1] = ~0UL} }
 150 #define PHYSID_MASK_NONE        { {[0 ... PHYSID_ARRAY_SIZE-1] = 0UL} }
 151 
 152 extern physid_mask_t phys_cpu_present_map;
 153 
 154 #endif /* _ASM_X86_MPSPEC_H */