root/arch/x86/include/asm/uv/uv_mmrs.h

INCLUDED FROM

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * SGI UV MMR definitions
   7  *
   8  * Copyright (C) 2007-2016 Silicon Graphics, Inc. All rights reserved.
   9  */
  10 
  11 #ifndef _ASM_X86_UV_UV_MMRS_H
  12 #define _ASM_X86_UV_UV_MMRS_H
  13 
  14 /*
  15  * This file contains MMR definitions for all UV hubs types.
  16  *
  17  * To minimize coding differences between hub types, the symbols are
  18  * grouped by architecture types.
  19  *
  20  * UVH  - definitions common to all UV hub types.
  21  * UVXH - definitions common to all UV eXtended hub types (currently 2, 3, 4).
  22  * UV1H - definitions specific to UV type 1 hub.
  23  * UV2H - definitions specific to UV type 2 hub.
  24  * UV3H - definitions specific to UV type 3 hub.
  25  * UV4H - definitions specific to UV type 4 hub.
  26  *
  27  * So in general, MMR addresses and structures are identical on all hubs types.
  28  * These MMRs are identified as:
  29  *      #define UVH_xxx         <address>
  30  *      union uvh_xxx {
  31  *              unsigned long       v;
  32  *              struct uvh_int_cmpd_s {
  33  *              } s;
  34  *      };
  35  *
  36  * If the MMR exists on all hub types but have different addresses,
  37  * use a conditional operator to define the value at runtime.
  38  *      #define UV1Hxxx a
  39  *      #define UV2Hxxx b
  40  *      #define UV3Hxxx c
  41  *      #define UV4Hxxx d
  42  *      #define UV4AHxxx e
  43  *      #define UVHxxx  (is_uv1_hub() ? UV1Hxxx :
  44  *                      (is_uv2_hub() ? UV2Hxxx :
  45  *                      (is_uv3_hub() ? UV3Hxxx :
  46  *                      (is_uv4a_hub() ? UV4AHxxx :
  47  *                                      UV4Hxxx))
  48  *
  49  * If the MMR exists on all hub types > 1 but have different addresses, the
  50  * variation using "UVX" as the prefix exists.
  51  *      #define UV2Hxxx b
  52  *      #define UV3Hxxx c
  53  *      #define UV4Hxxx d
  54  *      #define UV4AHxxx e
  55  *      #define UVHxxx  (is_uv2_hub() ? UV2Hxxx :
  56  *                      (is_uv3_hub() ? UV3Hxxx :
  57  *                      (is_uv4a_hub() ? UV4AHxxx :
  58  *                                      UV4Hxxx))
  59  *
  60  *      union uvh_xxx {
  61  *              unsigned long       v;
  62  *              struct uvh_xxx_s {       # Common fields only
  63  *              } s;
  64  *              struct uv1h_xxx_s {      # Full UV1 definition (*)
  65  *              } s1;
  66  *              struct uv2h_xxx_s {      # Full UV2 definition (*)
  67  *              } s2;
  68  *              struct uv3h_xxx_s {      # Full UV3 definition (*)
  69  *              } s3;
  70  *              (NOTE: No struct uv4ah_xxx_s members exist)
  71  *              struct uv4h_xxx_s {      # Full UV4 definition (*)
  72  *              } s4;
  73  *      };
  74  *              (* - if present and different than the common struct)
  75  *
  76  * Only essential differences are enumerated. For example, if the address is
  77  * the same for all UV's, only a single #define is generated. Likewise,
  78  * if the contents is the same for all hubs, only the "s" structure is
  79  * generated.
  80  *
  81  * If the MMR exists on ONLY 1 type of hub, no generic definition is
  82  * generated:
  83  *      #define UVnH_xxx        <uvn address>
  84  *      union uvnh_xxx {
  85  *              unsigned long       v;
  86  *              struct uvh_int_cmpd_s {
  87  *              } sn;
  88  *      };
  89  *
  90  * (GEN Flags: mflags_opt= undefs=function UV234=UVXH)
  91  */
  92 
  93 #define UV_MMR_ENABLE           (1UL << 63)
  94 
  95 #define UV1_HUB_PART_NUMBER     0x88a5
  96 #define UV2_HUB_PART_NUMBER     0x8eb8
  97 #define UV2_HUB_PART_NUMBER_X   0x1111
  98 #define UV3_HUB_PART_NUMBER     0x9578
  99 #define UV3_HUB_PART_NUMBER_X   0x4321
 100 #define UV4_HUB_PART_NUMBER     0x99a1
 101 
 102 /* Compat: Indicate which UV Hubs are supported. */
 103 #define UV1_HUB_IS_SUPPORTED    1
 104 #define UV2_HUB_IS_SUPPORTED    1
 105 #define UV3_HUB_IS_SUPPORTED    1
 106 #define UV4_HUB_IS_SUPPORTED    1
 107 #define UV4A_HUB_IS_SUPPORTED   1
 108 
 109 /* Error function to catch undefined references */
 110 extern unsigned long uv_undefined(char *str);
 111 
 112 /* ========================================================================= */
 113 /*                          UVH_BAU_DATA_BROADCAST                           */
 114 /* ========================================================================= */
 115 #define UVH_BAU_DATA_BROADCAST 0x61688UL
 116 
 117 #define UV1H_BAU_DATA_BROADCAST_32 0x440
 118 #define UV2H_BAU_DATA_BROADCAST_32 0x440
 119 #define UV3H_BAU_DATA_BROADCAST_32 0x440
 120 #define UV4H_BAU_DATA_BROADCAST_32 0x360
 121 #define UVH_BAU_DATA_BROADCAST_32 (                                     \
 122         is_uv1_hub() ? UV1H_BAU_DATA_BROADCAST_32 :                     \
 123         is_uv2_hub() ? UV2H_BAU_DATA_BROADCAST_32 :                     \
 124         is_uv3_hub() ? UV3H_BAU_DATA_BROADCAST_32 :                     \
 125         /*is_uv4_hub*/ UV4H_BAU_DATA_BROADCAST_32)
 126 
 127 #define UVH_BAU_DATA_BROADCAST_ENABLE_SHFT              0
 128 #define UVH_BAU_DATA_BROADCAST_ENABLE_MASK              0x0000000000000001UL
 129 
 130 
 131 union uvh_bau_data_broadcast_u {
 132         unsigned long   v;
 133         struct uvh_bau_data_broadcast_s {
 134                 unsigned long   enable:1;                       /* RW */
 135                 unsigned long   rsvd_1_63:63;
 136         } s;
 137 };
 138 
 139 /* ========================================================================= */
 140 /*                           UVH_BAU_DATA_CONFIG                             */
 141 /* ========================================================================= */
 142 #define UVH_BAU_DATA_CONFIG 0x61680UL
 143 
 144 #define UV1H_BAU_DATA_CONFIG_32 0x438
 145 #define UV2H_BAU_DATA_CONFIG_32 0x438
 146 #define UV3H_BAU_DATA_CONFIG_32 0x438
 147 #define UV4H_BAU_DATA_CONFIG_32 0x358
 148 #define UVH_BAU_DATA_CONFIG_32 (                                        \
 149         is_uv1_hub() ? UV1H_BAU_DATA_CONFIG_32 :                        \
 150         is_uv2_hub() ? UV2H_BAU_DATA_CONFIG_32 :                        \
 151         is_uv3_hub() ? UV3H_BAU_DATA_CONFIG_32 :                        \
 152         /*is_uv4_hub*/ UV4H_BAU_DATA_CONFIG_32)
 153 
 154 #define UVH_BAU_DATA_CONFIG_VECTOR_SHFT                 0
 155 #define UVH_BAU_DATA_CONFIG_DM_SHFT                     8
 156 #define UVH_BAU_DATA_CONFIG_DESTMODE_SHFT               11
 157 #define UVH_BAU_DATA_CONFIG_STATUS_SHFT                 12
 158 #define UVH_BAU_DATA_CONFIG_P_SHFT                      13
 159 #define UVH_BAU_DATA_CONFIG_T_SHFT                      15
 160 #define UVH_BAU_DATA_CONFIG_M_SHFT                      16
 161 #define UVH_BAU_DATA_CONFIG_APIC_ID_SHFT                32
 162 #define UVH_BAU_DATA_CONFIG_VECTOR_MASK                 0x00000000000000ffUL
 163 #define UVH_BAU_DATA_CONFIG_DM_MASK                     0x0000000000000700UL
 164 #define UVH_BAU_DATA_CONFIG_DESTMODE_MASK               0x0000000000000800UL
 165 #define UVH_BAU_DATA_CONFIG_STATUS_MASK                 0x0000000000001000UL
 166 #define UVH_BAU_DATA_CONFIG_P_MASK                      0x0000000000002000UL
 167 #define UVH_BAU_DATA_CONFIG_T_MASK                      0x0000000000008000UL
 168 #define UVH_BAU_DATA_CONFIG_M_MASK                      0x0000000000010000UL
 169 #define UVH_BAU_DATA_CONFIG_APIC_ID_MASK                0xffffffff00000000UL
 170 
 171 
 172 union uvh_bau_data_config_u {
 173         unsigned long   v;
 174         struct uvh_bau_data_config_s {
 175                 unsigned long   vector_:8;                      /* RW */
 176                 unsigned long   dm:3;                           /* RW */
 177                 unsigned long   destmode:1;                     /* RW */
 178                 unsigned long   status:1;                       /* RO */
 179                 unsigned long   p:1;                            /* RO */
 180                 unsigned long   rsvd_14:1;
 181                 unsigned long   t:1;                            /* RO */
 182                 unsigned long   m:1;                            /* RW */
 183                 unsigned long   rsvd_17_31:15;
 184                 unsigned long   apic_id:32;                     /* RW */
 185         } s;
 186 };
 187 
 188 /* ========================================================================= */
 189 /*                           UVH_EVENT_OCCURRED0                             */
 190 /* ========================================================================= */
 191 #define UVH_EVENT_OCCURRED0 0x70000UL
 192 #define UVH_EVENT_OCCURRED0_32 0x5e8
 193 
 194 #define UVH_EVENT_OCCURRED0_LB_HCERR_SHFT               0
 195 #define UVH_EVENT_OCCURRED0_RH_AOERR0_SHFT              11
 196 #define UVH_EVENT_OCCURRED0_LB_HCERR_MASK               0x0000000000000001UL
 197 #define UVH_EVENT_OCCURRED0_RH_AOERR0_MASK              0x0000000000000800UL
 198 
 199 #define UV1H_EVENT_OCCURRED0_GR0_HCERR_SHFT             1
 200 #define UV1H_EVENT_OCCURRED0_GR1_HCERR_SHFT             2
 201 #define UV1H_EVENT_OCCURRED0_LH_HCERR_SHFT              3
 202 #define UV1H_EVENT_OCCURRED0_RH_HCERR_SHFT              4
 203 #define UV1H_EVENT_OCCURRED0_XN_HCERR_SHFT              5
 204 #define UV1H_EVENT_OCCURRED0_SI_HCERR_SHFT              6
 205 #define UV1H_EVENT_OCCURRED0_LB_AOERR0_SHFT             7
 206 #define UV1H_EVENT_OCCURRED0_GR0_AOERR0_SHFT            8
 207 #define UV1H_EVENT_OCCURRED0_GR1_AOERR0_SHFT            9
 208 #define UV1H_EVENT_OCCURRED0_LH_AOERR0_SHFT             10
 209 #define UV1H_EVENT_OCCURRED0_XN_AOERR0_SHFT             12
 210 #define UV1H_EVENT_OCCURRED0_SI_AOERR0_SHFT             13
 211 #define UV1H_EVENT_OCCURRED0_LB_AOERR1_SHFT             14
 212 #define UV1H_EVENT_OCCURRED0_GR0_AOERR1_SHFT            15
 213 #define UV1H_EVENT_OCCURRED0_GR1_AOERR1_SHFT            16
 214 #define UV1H_EVENT_OCCURRED0_LH_AOERR1_SHFT             17
 215 #define UV1H_EVENT_OCCURRED0_RH_AOERR1_SHFT             18
 216 #define UV1H_EVENT_OCCURRED0_XN_AOERR1_SHFT             19
 217 #define UV1H_EVENT_OCCURRED0_SI_AOERR1_SHFT             20
 218 #define UV1H_EVENT_OCCURRED0_RH_VPI_INT_SHFT            21
 219 #define UV1H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_SHFT   22
 220 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_0_SHFT          23
 221 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_1_SHFT          24
 222 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_2_SHFT          25
 223 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_3_SHFT          26
 224 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_4_SHFT          27
 225 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_5_SHFT          28
 226 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_6_SHFT          29
 227 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_7_SHFT          30
 228 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_8_SHFT          31
 229 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_9_SHFT          32
 230 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_10_SHFT         33
 231 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_11_SHFT         34
 232 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_12_SHFT         35
 233 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_13_SHFT         36
 234 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_14_SHFT         37
 235 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_15_SHFT         38
 236 #define UV1H_EVENT_OCCURRED0_L1_NMI_INT_SHFT            39
 237 #define UV1H_EVENT_OCCURRED0_STOP_CLOCK_SHFT            40
 238 #define UV1H_EVENT_OCCURRED0_ASIC_TO_L1_SHFT            41
 239 #define UV1H_EVENT_OCCURRED0_L1_TO_ASIC_SHFT            42
 240 #define UV1H_EVENT_OCCURRED0_LTC_INT_SHFT               43
 241 #define UV1H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_SHFT        44
 242 #define UV1H_EVENT_OCCURRED0_IPI_INT_SHFT               45
 243 #define UV1H_EVENT_OCCURRED0_EXTIO_INT0_SHFT            46
 244 #define UV1H_EVENT_OCCURRED0_EXTIO_INT1_SHFT            47
 245 #define UV1H_EVENT_OCCURRED0_EXTIO_INT2_SHFT            48
 246 #define UV1H_EVENT_OCCURRED0_EXTIO_INT3_SHFT            49
 247 #define UV1H_EVENT_OCCURRED0_PROFILE_INT_SHFT           50
 248 #define UV1H_EVENT_OCCURRED0_RTC0_SHFT                  51
 249 #define UV1H_EVENT_OCCURRED0_RTC1_SHFT                  52
 250 #define UV1H_EVENT_OCCURRED0_RTC2_SHFT                  53
 251 #define UV1H_EVENT_OCCURRED0_RTC3_SHFT                  54
 252 #define UV1H_EVENT_OCCURRED0_BAU_DATA_SHFT              55
 253 #define UV1H_EVENT_OCCURRED0_POWER_MANAGEMENT_REQ_SHFT  56
 254 #define UV1H_EVENT_OCCURRED0_GR0_HCERR_MASK             0x0000000000000002UL
 255 #define UV1H_EVENT_OCCURRED0_GR1_HCERR_MASK             0x0000000000000004UL
 256 #define UV1H_EVENT_OCCURRED0_LH_HCERR_MASK              0x0000000000000008UL
 257 #define UV1H_EVENT_OCCURRED0_RH_HCERR_MASK              0x0000000000000010UL
 258 #define UV1H_EVENT_OCCURRED0_XN_HCERR_MASK              0x0000000000000020UL
 259 #define UV1H_EVENT_OCCURRED0_SI_HCERR_MASK              0x0000000000000040UL
 260 #define UV1H_EVENT_OCCURRED0_LB_AOERR0_MASK             0x0000000000000080UL
 261 #define UV1H_EVENT_OCCURRED0_GR0_AOERR0_MASK            0x0000000000000100UL
 262 #define UV1H_EVENT_OCCURRED0_GR1_AOERR0_MASK            0x0000000000000200UL
 263 #define UV1H_EVENT_OCCURRED0_LH_AOERR0_MASK             0x0000000000000400UL
 264 #define UV1H_EVENT_OCCURRED0_XN_AOERR0_MASK             0x0000000000001000UL
 265 #define UV1H_EVENT_OCCURRED0_SI_AOERR0_MASK             0x0000000000002000UL
 266 #define UV1H_EVENT_OCCURRED0_LB_AOERR1_MASK             0x0000000000004000UL
 267 #define UV1H_EVENT_OCCURRED0_GR0_AOERR1_MASK            0x0000000000008000UL
 268 #define UV1H_EVENT_OCCURRED0_GR1_AOERR1_MASK            0x0000000000010000UL
 269 #define UV1H_EVENT_OCCURRED0_LH_AOERR1_MASK             0x0000000000020000UL
 270 #define UV1H_EVENT_OCCURRED0_RH_AOERR1_MASK             0x0000000000040000UL
 271 #define UV1H_EVENT_OCCURRED0_XN_AOERR1_MASK             0x0000000000080000UL
 272 #define UV1H_EVENT_OCCURRED0_SI_AOERR1_MASK             0x0000000000100000UL
 273 #define UV1H_EVENT_OCCURRED0_RH_VPI_INT_MASK            0x0000000000200000UL
 274 #define UV1H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_MASK   0x0000000000400000UL
 275 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_0_MASK          0x0000000000800000UL
 276 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_1_MASK          0x0000000001000000UL
 277 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_2_MASK          0x0000000002000000UL
 278 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_3_MASK          0x0000000004000000UL
 279 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_4_MASK          0x0000000008000000UL
 280 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_5_MASK          0x0000000010000000UL
 281 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_6_MASK          0x0000000020000000UL
 282 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_7_MASK          0x0000000040000000UL
 283 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_8_MASK          0x0000000080000000UL
 284 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_9_MASK          0x0000000100000000UL
 285 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_10_MASK         0x0000000200000000UL
 286 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_11_MASK         0x0000000400000000UL
 287 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_12_MASK         0x0000000800000000UL
 288 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_13_MASK         0x0000001000000000UL
 289 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_14_MASK         0x0000002000000000UL
 290 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_15_MASK         0x0000004000000000UL
 291 #define UV1H_EVENT_OCCURRED0_L1_NMI_INT_MASK            0x0000008000000000UL
 292 #define UV1H_EVENT_OCCURRED0_STOP_CLOCK_MASK            0x0000010000000000UL
 293 #define UV1H_EVENT_OCCURRED0_ASIC_TO_L1_MASK            0x0000020000000000UL
 294 #define UV1H_EVENT_OCCURRED0_L1_TO_ASIC_MASK            0x0000040000000000UL
 295 #define UV1H_EVENT_OCCURRED0_LTC_INT_MASK               0x0000080000000000UL
 296 #define UV1H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_MASK        0x0000100000000000UL
 297 #define UV1H_EVENT_OCCURRED0_IPI_INT_MASK               0x0000200000000000UL
 298 #define UV1H_EVENT_OCCURRED0_EXTIO_INT0_MASK            0x0000400000000000UL
 299 #define UV1H_EVENT_OCCURRED0_EXTIO_INT1_MASK            0x0000800000000000UL
 300 #define UV1H_EVENT_OCCURRED0_EXTIO_INT2_MASK            0x0001000000000000UL
 301 #define UV1H_EVENT_OCCURRED0_EXTIO_INT3_MASK            0x0002000000000000UL
 302 #define UV1H_EVENT_OCCURRED0_PROFILE_INT_MASK           0x0004000000000000UL
 303 #define UV1H_EVENT_OCCURRED0_RTC0_MASK                  0x0008000000000000UL
 304 #define UV1H_EVENT_OCCURRED0_RTC1_MASK                  0x0010000000000000UL
 305 #define UV1H_EVENT_OCCURRED0_RTC2_MASK                  0x0020000000000000UL
 306 #define UV1H_EVENT_OCCURRED0_RTC3_MASK                  0x0040000000000000UL
 307 #define UV1H_EVENT_OCCURRED0_BAU_DATA_MASK              0x0080000000000000UL
 308 #define UV1H_EVENT_OCCURRED0_POWER_MANAGEMENT_REQ_MASK  0x0100000000000000UL
 309 
 310 #define UVXH_EVENT_OCCURRED0_RH_HCERR_SHFT              2
 311 #define UVXH_EVENT_OCCURRED0_LH0_HCERR_SHFT             3
 312 #define UVXH_EVENT_OCCURRED0_LH1_HCERR_SHFT             4
 313 #define UVXH_EVENT_OCCURRED0_GR0_HCERR_SHFT             5
 314 #define UVXH_EVENT_OCCURRED0_GR1_HCERR_SHFT             6
 315 #define UVXH_EVENT_OCCURRED0_NI0_HCERR_SHFT             7
 316 #define UVXH_EVENT_OCCURRED0_NI1_HCERR_SHFT             8
 317 #define UVXH_EVENT_OCCURRED0_LB_AOERR0_SHFT             9
 318 #define UVXH_EVENT_OCCURRED0_LH0_AOERR0_SHFT            12
 319 #define UVXH_EVENT_OCCURRED0_LH1_AOERR0_SHFT            13
 320 #define UVXH_EVENT_OCCURRED0_GR0_AOERR0_SHFT            14
 321 #define UVXH_EVENT_OCCURRED0_GR1_AOERR0_SHFT            15
 322 #define UVXH_EVENT_OCCURRED0_XB_AOERR0_SHFT             16
 323 #define UVXH_EVENT_OCCURRED0_RH_HCERR_MASK              0x0000000000000004UL
 324 #define UVXH_EVENT_OCCURRED0_LH0_HCERR_MASK             0x0000000000000008UL
 325 #define UVXH_EVENT_OCCURRED0_LH1_HCERR_MASK             0x0000000000000010UL
 326 #define UVXH_EVENT_OCCURRED0_GR0_HCERR_MASK             0x0000000000000020UL
 327 #define UVXH_EVENT_OCCURRED0_GR1_HCERR_MASK             0x0000000000000040UL
 328 #define UVXH_EVENT_OCCURRED0_NI0_HCERR_MASK             0x0000000000000080UL
 329 #define UVXH_EVENT_OCCURRED0_NI1_HCERR_MASK             0x0000000000000100UL
 330 #define UVXH_EVENT_OCCURRED0_LB_AOERR0_MASK             0x0000000000000200UL
 331 #define UVXH_EVENT_OCCURRED0_LH0_AOERR0_MASK            0x0000000000001000UL
 332 #define UVXH_EVENT_OCCURRED0_LH1_AOERR0_MASK            0x0000000000002000UL
 333 #define UVXH_EVENT_OCCURRED0_GR0_AOERR0_MASK            0x0000000000004000UL
 334 #define UVXH_EVENT_OCCURRED0_GR1_AOERR0_MASK            0x0000000000008000UL
 335 #define UVXH_EVENT_OCCURRED0_XB_AOERR0_MASK             0x0000000000010000UL
 336 
 337 #define UV2H_EVENT_OCCURRED0_QP_HCERR_SHFT              1
 338 #define UV2H_EVENT_OCCURRED0_QP_AOERR0_SHFT             10
 339 #define UV2H_EVENT_OCCURRED0_RT_AOERR0_SHFT             17
 340 #define UV2H_EVENT_OCCURRED0_NI0_AOERR0_SHFT            18
 341 #define UV2H_EVENT_OCCURRED0_NI1_AOERR0_SHFT            19
 342 #define UV2H_EVENT_OCCURRED0_LB_AOERR1_SHFT             20
 343 #define UV2H_EVENT_OCCURRED0_QP_AOERR1_SHFT             21
 344 #define UV2H_EVENT_OCCURRED0_RH_AOERR1_SHFT             22
 345 #define UV2H_EVENT_OCCURRED0_LH0_AOERR1_SHFT            23
 346 #define UV2H_EVENT_OCCURRED0_LH1_AOERR1_SHFT            24
 347 #define UV2H_EVENT_OCCURRED0_GR0_AOERR1_SHFT            25
 348 #define UV2H_EVENT_OCCURRED0_GR1_AOERR1_SHFT            26
 349 #define UV2H_EVENT_OCCURRED0_XB_AOERR1_SHFT             27
 350 #define UV2H_EVENT_OCCURRED0_RT_AOERR1_SHFT             28
 351 #define UV2H_EVENT_OCCURRED0_NI0_AOERR1_SHFT            29
 352 #define UV2H_EVENT_OCCURRED0_NI1_AOERR1_SHFT            30
 353 #define UV2H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_SHFT   31
 354 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_0_SHFT          32
 355 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_1_SHFT          33
 356 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_2_SHFT          34
 357 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_3_SHFT          35
 358 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_4_SHFT          36
 359 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_5_SHFT          37
 360 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_6_SHFT          38
 361 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_7_SHFT          39
 362 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_8_SHFT          40
 363 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_9_SHFT          41
 364 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_10_SHFT         42
 365 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_11_SHFT         43
 366 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_12_SHFT         44
 367 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_13_SHFT         45
 368 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_14_SHFT         46
 369 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_15_SHFT         47
 370 #define UV2H_EVENT_OCCURRED0_L1_NMI_INT_SHFT            48
 371 #define UV2H_EVENT_OCCURRED0_STOP_CLOCK_SHFT            49
 372 #define UV2H_EVENT_OCCURRED0_ASIC_TO_L1_SHFT            50
 373 #define UV2H_EVENT_OCCURRED0_L1_TO_ASIC_SHFT            51
 374 #define UV2H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_SHFT        52
 375 #define UV2H_EVENT_OCCURRED0_IPI_INT_SHFT               53
 376 #define UV2H_EVENT_OCCURRED0_EXTIO_INT0_SHFT            54
 377 #define UV2H_EVENT_OCCURRED0_EXTIO_INT1_SHFT            55
 378 #define UV2H_EVENT_OCCURRED0_EXTIO_INT2_SHFT            56
 379 #define UV2H_EVENT_OCCURRED0_EXTIO_INT3_SHFT            57
 380 #define UV2H_EVENT_OCCURRED0_PROFILE_INT_SHFT           58
 381 #define UV2H_EVENT_OCCURRED0_QP_HCERR_MASK              0x0000000000000002UL
 382 #define UV2H_EVENT_OCCURRED0_QP_AOERR0_MASK             0x0000000000000400UL
 383 #define UV2H_EVENT_OCCURRED0_RT_AOERR0_MASK             0x0000000000020000UL
 384 #define UV2H_EVENT_OCCURRED0_NI0_AOERR0_MASK            0x0000000000040000UL
 385 #define UV2H_EVENT_OCCURRED0_NI1_AOERR0_MASK            0x0000000000080000UL
 386 #define UV2H_EVENT_OCCURRED0_LB_AOERR1_MASK             0x0000000000100000UL
 387 #define UV2H_EVENT_OCCURRED0_QP_AOERR1_MASK             0x0000000000200000UL
 388 #define UV2H_EVENT_OCCURRED0_RH_AOERR1_MASK             0x0000000000400000UL
 389 #define UV2H_EVENT_OCCURRED0_LH0_AOERR1_MASK            0x0000000000800000UL
 390 #define UV2H_EVENT_OCCURRED0_LH1_AOERR1_MASK            0x0000000001000000UL
 391 #define UV2H_EVENT_OCCURRED0_GR0_AOERR1_MASK            0x0000000002000000UL
 392 #define UV2H_EVENT_OCCURRED0_GR1_AOERR1_MASK            0x0000000004000000UL
 393 #define UV2H_EVENT_OCCURRED0_XB_AOERR1_MASK             0x0000000008000000UL
 394 #define UV2H_EVENT_OCCURRED0_RT_AOERR1_MASK             0x0000000010000000UL
 395 #define UV2H_EVENT_OCCURRED0_NI0_AOERR1_MASK            0x0000000020000000UL
 396 #define UV2H_EVENT_OCCURRED0_NI1_AOERR1_MASK            0x0000000040000000UL
 397 #define UV2H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_MASK   0x0000000080000000UL
 398 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_0_MASK          0x0000000100000000UL
 399 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_1_MASK          0x0000000200000000UL
 400 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_2_MASK          0x0000000400000000UL
 401 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_3_MASK          0x0000000800000000UL
 402 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_4_MASK          0x0000001000000000UL
 403 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_5_MASK          0x0000002000000000UL
 404 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_6_MASK          0x0000004000000000UL
 405 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_7_MASK          0x0000008000000000UL
 406 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_8_MASK          0x0000010000000000UL
 407 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_9_MASK          0x0000020000000000UL
 408 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_10_MASK         0x0000040000000000UL
 409 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_11_MASK         0x0000080000000000UL
 410 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_12_MASK         0x0000100000000000UL
 411 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_13_MASK         0x0000200000000000UL
 412 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_14_MASK         0x0000400000000000UL
 413 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_15_MASK         0x0000800000000000UL
 414 #define UV2H_EVENT_OCCURRED0_L1_NMI_INT_MASK            0x0001000000000000UL
 415 #define UV2H_EVENT_OCCURRED0_STOP_CLOCK_MASK            0x0002000000000000UL
 416 #define UV2H_EVENT_OCCURRED0_ASIC_TO_L1_MASK            0x0004000000000000UL
 417 #define UV2H_EVENT_OCCURRED0_L1_TO_ASIC_MASK            0x0008000000000000UL
 418 #define UV2H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_MASK        0x0010000000000000UL
 419 #define UV2H_EVENT_OCCURRED0_IPI_INT_MASK               0x0020000000000000UL
 420 #define UV2H_EVENT_OCCURRED0_EXTIO_INT0_MASK            0x0040000000000000UL
 421 #define UV2H_EVENT_OCCURRED0_EXTIO_INT1_MASK            0x0080000000000000UL
 422 #define UV2H_EVENT_OCCURRED0_EXTIO_INT2_MASK            0x0100000000000000UL
 423 #define UV2H_EVENT_OCCURRED0_EXTIO_INT3_MASK            0x0200000000000000UL
 424 #define UV2H_EVENT_OCCURRED0_PROFILE_INT_MASK           0x0400000000000000UL
 425 
 426 #define UV3H_EVENT_OCCURRED0_QP_HCERR_SHFT              1
 427 #define UV3H_EVENT_OCCURRED0_QP_AOERR0_SHFT             10
 428 #define UV3H_EVENT_OCCURRED0_RT_AOERR0_SHFT             17
 429 #define UV3H_EVENT_OCCURRED0_NI0_AOERR0_SHFT            18
 430 #define UV3H_EVENT_OCCURRED0_NI1_AOERR0_SHFT            19
 431 #define UV3H_EVENT_OCCURRED0_LB_AOERR1_SHFT             20
 432 #define UV3H_EVENT_OCCURRED0_QP_AOERR1_SHFT             21
 433 #define UV3H_EVENT_OCCURRED0_RH_AOERR1_SHFT             22
 434 #define UV3H_EVENT_OCCURRED0_LH0_AOERR1_SHFT            23
 435 #define UV3H_EVENT_OCCURRED0_LH1_AOERR1_SHFT            24
 436 #define UV3H_EVENT_OCCURRED0_GR0_AOERR1_SHFT            25
 437 #define UV3H_EVENT_OCCURRED0_GR1_AOERR1_SHFT            26
 438 #define UV3H_EVENT_OCCURRED0_XB_AOERR1_SHFT             27
 439 #define UV3H_EVENT_OCCURRED0_RT_AOERR1_SHFT             28
 440 #define UV3H_EVENT_OCCURRED0_NI0_AOERR1_SHFT            29
 441 #define UV3H_EVENT_OCCURRED0_NI1_AOERR1_SHFT            30
 442 #define UV3H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_SHFT   31
 443 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_0_SHFT          32
 444 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_1_SHFT          33
 445 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_2_SHFT          34
 446 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_3_SHFT          35
 447 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_4_SHFT          36
 448 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_5_SHFT          37
 449 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_6_SHFT          38
 450 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_7_SHFT          39
 451 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_8_SHFT          40
 452 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_9_SHFT          41
 453 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_10_SHFT         42
 454 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_11_SHFT         43
 455 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_12_SHFT         44
 456 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_13_SHFT         45
 457 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_14_SHFT         46
 458 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_15_SHFT         47
 459 #define UV3H_EVENT_OCCURRED0_L1_NMI_INT_SHFT            48
 460 #define UV3H_EVENT_OCCURRED0_STOP_CLOCK_SHFT            49
 461 #define UV3H_EVENT_OCCURRED0_ASIC_TO_L1_SHFT            50
 462 #define UV3H_EVENT_OCCURRED0_L1_TO_ASIC_SHFT            51
 463 #define UV3H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_SHFT        52
 464 #define UV3H_EVENT_OCCURRED0_IPI_INT_SHFT               53
 465 #define UV3H_EVENT_OCCURRED0_EXTIO_INT0_SHFT            54
 466 #define UV3H_EVENT_OCCURRED0_EXTIO_INT1_SHFT            55
 467 #define UV3H_EVENT_OCCURRED0_EXTIO_INT2_SHFT            56
 468 #define UV3H_EVENT_OCCURRED0_EXTIO_INT3_SHFT            57
 469 #define UV3H_EVENT_OCCURRED0_PROFILE_INT_SHFT           58
 470 #define UV3H_EVENT_OCCURRED0_QP_HCERR_MASK              0x0000000000000002UL
 471 #define UV3H_EVENT_OCCURRED0_QP_AOERR0_MASK             0x0000000000000400UL
 472 #define UV3H_EVENT_OCCURRED0_RT_AOERR0_MASK             0x0000000000020000UL
 473 #define UV3H_EVENT_OCCURRED0_NI0_AOERR0_MASK            0x0000000000040000UL
 474 #define UV3H_EVENT_OCCURRED0_NI1_AOERR0_MASK            0x0000000000080000UL
 475 #define UV3H_EVENT_OCCURRED0_LB_AOERR1_MASK             0x0000000000100000UL
 476 #define UV3H_EVENT_OCCURRED0_QP_AOERR1_MASK             0x0000000000200000UL
 477 #define UV3H_EVENT_OCCURRED0_RH_AOERR1_MASK             0x0000000000400000UL
 478 #define UV3H_EVENT_OCCURRED0_LH0_AOERR1_MASK            0x0000000000800000UL
 479 #define UV3H_EVENT_OCCURRED0_LH1_AOERR1_MASK            0x0000000001000000UL
 480 #define UV3H_EVENT_OCCURRED0_GR0_AOERR1_MASK            0x0000000002000000UL
 481 #define UV3H_EVENT_OCCURRED0_GR1_AOERR1_MASK            0x0000000004000000UL
 482 #define UV3H_EVENT_OCCURRED0_XB_AOERR1_MASK             0x0000000008000000UL
 483 #define UV3H_EVENT_OCCURRED0_RT_AOERR1_MASK             0x0000000010000000UL
 484 #define UV3H_EVENT_OCCURRED0_NI0_AOERR1_MASK            0x0000000020000000UL
 485 #define UV3H_EVENT_OCCURRED0_NI1_AOERR1_MASK            0x0000000040000000UL
 486 #define UV3H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_MASK   0x0000000080000000UL
 487 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_0_MASK          0x0000000100000000UL
 488 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_1_MASK          0x0000000200000000UL
 489 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_2_MASK          0x0000000400000000UL
 490 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_3_MASK          0x0000000800000000UL
 491 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_4_MASK          0x0000001000000000UL
 492 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_5_MASK          0x0000002000000000UL
 493 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_6_MASK          0x0000004000000000UL
 494 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_7_MASK          0x0000008000000000UL
 495 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_8_MASK          0x0000010000000000UL
 496 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_9_MASK          0x0000020000000000UL
 497 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_10_MASK         0x0000040000000000UL
 498 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_11_MASK         0x0000080000000000UL
 499 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_12_MASK         0x0000100000000000UL
 500 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_13_MASK         0x0000200000000000UL
 501 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_14_MASK         0x0000400000000000UL
 502 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_15_MASK         0x0000800000000000UL
 503 #define UV3H_EVENT_OCCURRED0_L1_NMI_INT_MASK            0x0001000000000000UL
 504 #define UV3H_EVENT_OCCURRED0_STOP_CLOCK_MASK            0x0002000000000000UL
 505 #define UV3H_EVENT_OCCURRED0_ASIC_TO_L1_MASK            0x0004000000000000UL
 506 #define UV3H_EVENT_OCCURRED0_L1_TO_ASIC_MASK            0x0008000000000000UL
 507 #define UV3H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_MASK        0x0010000000000000UL
 508 #define UV3H_EVENT_OCCURRED0_IPI_INT_MASK               0x0020000000000000UL
 509 #define UV3H_EVENT_OCCURRED0_EXTIO_INT0_MASK            0x0040000000000000UL
 510 #define UV3H_EVENT_OCCURRED0_EXTIO_INT1_MASK            0x0080000000000000UL
 511 #define UV3H_EVENT_OCCURRED0_EXTIO_INT2_MASK            0x0100000000000000UL
 512 #define UV3H_EVENT_OCCURRED0_EXTIO_INT3_MASK            0x0200000000000000UL
 513 #define UV3H_EVENT_OCCURRED0_PROFILE_INT_MASK           0x0400000000000000UL
 514 
 515 #define UV4H_EVENT_OCCURRED0_KT_HCERR_SHFT              1
 516 #define UV4H_EVENT_OCCURRED0_KT_AOERR0_SHFT             10
 517 #define UV4H_EVENT_OCCURRED0_RTQ0_AOERR0_SHFT           17
 518 #define UV4H_EVENT_OCCURRED0_RTQ1_AOERR0_SHFT           18
 519 #define UV4H_EVENT_OCCURRED0_RTQ2_AOERR0_SHFT           19
 520 #define UV4H_EVENT_OCCURRED0_RTQ3_AOERR0_SHFT           20
 521 #define UV4H_EVENT_OCCURRED0_NI0_AOERR0_SHFT            21
 522 #define UV4H_EVENT_OCCURRED0_NI1_AOERR0_SHFT            22
 523 #define UV4H_EVENT_OCCURRED0_LB_AOERR1_SHFT             23
 524 #define UV4H_EVENT_OCCURRED0_KT_AOERR1_SHFT             24
 525 #define UV4H_EVENT_OCCURRED0_RH_AOERR1_SHFT             25
 526 #define UV4H_EVENT_OCCURRED0_LH0_AOERR1_SHFT            26
 527 #define UV4H_EVENT_OCCURRED0_LH1_AOERR1_SHFT            27
 528 #define UV4H_EVENT_OCCURRED0_GR0_AOERR1_SHFT            28
 529 #define UV4H_EVENT_OCCURRED0_GR1_AOERR1_SHFT            29
 530 #define UV4H_EVENT_OCCURRED0_XB_AOERR1_SHFT             30
 531 #define UV4H_EVENT_OCCURRED0_RTQ0_AOERR1_SHFT           31
 532 #define UV4H_EVENT_OCCURRED0_RTQ1_AOERR1_SHFT           32
 533 #define UV4H_EVENT_OCCURRED0_RTQ2_AOERR1_SHFT           33
 534 #define UV4H_EVENT_OCCURRED0_RTQ3_AOERR1_SHFT           34
 535 #define UV4H_EVENT_OCCURRED0_NI0_AOERR1_SHFT            35
 536 #define UV4H_EVENT_OCCURRED0_NI1_AOERR1_SHFT            36
 537 #define UV4H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_SHFT   37
 538 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_0_SHFT          38
 539 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_1_SHFT          39
 540 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_2_SHFT          40
 541 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_3_SHFT          41
 542 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_4_SHFT          42
 543 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_5_SHFT          43
 544 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_6_SHFT          44
 545 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_7_SHFT          45
 546 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_8_SHFT          46
 547 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_9_SHFT          47
 548 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_10_SHFT         48
 549 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_11_SHFT         49
 550 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_12_SHFT         50
 551 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_13_SHFT         51
 552 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_14_SHFT         52
 553 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_15_SHFT         53
 554 #define UV4H_EVENT_OCCURRED0_L1_NMI_INT_SHFT            54
 555 #define UV4H_EVENT_OCCURRED0_STOP_CLOCK_SHFT            55
 556 #define UV4H_EVENT_OCCURRED0_ASIC_TO_L1_SHFT            56
 557 #define UV4H_EVENT_OCCURRED0_L1_TO_ASIC_SHFT            57
 558 #define UV4H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_SHFT        58
 559 #define UV4H_EVENT_OCCURRED0_IPI_INT_SHFT               59
 560 #define UV4H_EVENT_OCCURRED0_EXTIO_INT0_SHFT            60
 561 #define UV4H_EVENT_OCCURRED0_EXTIO_INT1_SHFT            61
 562 #define UV4H_EVENT_OCCURRED0_EXTIO_INT2_SHFT            62
 563 #define UV4H_EVENT_OCCURRED0_EXTIO_INT3_SHFT            63
 564 #define UV4H_EVENT_OCCURRED0_KT_HCERR_MASK              0x0000000000000002UL
 565 #define UV4H_EVENT_OCCURRED0_KT_AOERR0_MASK             0x0000000000000400UL
 566 #define UV4H_EVENT_OCCURRED0_RTQ0_AOERR0_MASK           0x0000000000020000UL
 567 #define UV4H_EVENT_OCCURRED0_RTQ1_AOERR0_MASK           0x0000000000040000UL
 568 #define UV4H_EVENT_OCCURRED0_RTQ2_AOERR0_MASK           0x0000000000080000UL
 569 #define UV4H_EVENT_OCCURRED0_RTQ3_AOERR0_MASK           0x0000000000100000UL
 570 #define UV4H_EVENT_OCCURRED0_NI0_AOERR0_MASK            0x0000000000200000UL
 571 #define UV4H_EVENT_OCCURRED0_NI1_AOERR0_MASK            0x0000000000400000UL
 572 #define UV4H_EVENT_OCCURRED0_LB_AOERR1_MASK             0x0000000000800000UL
 573 #define UV4H_EVENT_OCCURRED0_KT_AOERR1_MASK             0x0000000001000000UL
 574 #define UV4H_EVENT_OCCURRED0_RH_AOERR1_MASK             0x0000000002000000UL
 575 #define UV4H_EVENT_OCCURRED0_LH0_AOERR1_MASK            0x0000000004000000UL
 576 #define UV4H_EVENT_OCCURRED0_LH1_AOERR1_MASK            0x0000000008000000UL
 577 #define UV4H_EVENT_OCCURRED0_GR0_AOERR1_MASK            0x0000000010000000UL
 578 #define UV4H_EVENT_OCCURRED0_GR1_AOERR1_MASK            0x0000000020000000UL
 579 #define UV4H_EVENT_OCCURRED0_XB_AOERR1_MASK             0x0000000040000000UL
 580 #define UV4H_EVENT_OCCURRED0_RTQ0_AOERR1_MASK           0x0000000080000000UL
 581 #define UV4H_EVENT_OCCURRED0_RTQ1_AOERR1_MASK           0x0000000100000000UL
 582 #define UV4H_EVENT_OCCURRED0_RTQ2_AOERR1_MASK           0x0000000200000000UL
 583 #define UV4H_EVENT_OCCURRED0_RTQ3_AOERR1_MASK           0x0000000400000000UL
 584 #define UV4H_EVENT_OCCURRED0_NI0_AOERR1_MASK            0x0000000800000000UL
 585 #define UV4H_EVENT_OCCURRED0_NI1_AOERR1_MASK            0x0000001000000000UL
 586 #define UV4H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_MASK   0x0000002000000000UL
 587 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_0_MASK          0x0000004000000000UL
 588 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_1_MASK          0x0000008000000000UL
 589 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_2_MASK          0x0000010000000000UL
 590 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_3_MASK          0x0000020000000000UL
 591 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_4_MASK          0x0000040000000000UL
 592 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_5_MASK          0x0000080000000000UL
 593 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_6_MASK          0x0000100000000000UL
 594 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_7_MASK          0x0000200000000000UL
 595 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_8_MASK          0x0000400000000000UL
 596 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_9_MASK          0x0000800000000000UL
 597 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_10_MASK         0x0001000000000000UL
 598 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_11_MASK         0x0002000000000000UL
 599 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_12_MASK         0x0004000000000000UL
 600 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_13_MASK         0x0008000000000000UL
 601 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_14_MASK         0x0010000000000000UL
 602 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_15_MASK         0x0020000000000000UL
 603 #define UV4H_EVENT_OCCURRED0_L1_NMI_INT_MASK            0x0040000000000000UL
 604 #define UV4H_EVENT_OCCURRED0_STOP_CLOCK_MASK            0x0080000000000000UL
 605 #define UV4H_EVENT_OCCURRED0_ASIC_TO_L1_MASK            0x0100000000000000UL
 606 #define UV4H_EVENT_OCCURRED0_L1_TO_ASIC_MASK            0x0200000000000000UL
 607 #define UV4H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_MASK        0x0400000000000000UL
 608 #define UV4H_EVENT_OCCURRED0_IPI_INT_MASK               0x0800000000000000UL
 609 #define UV4H_EVENT_OCCURRED0_EXTIO_INT0_MASK            0x1000000000000000UL
 610 #define UV4H_EVENT_OCCURRED0_EXTIO_INT1_MASK            0x2000000000000000UL
 611 #define UV4H_EVENT_OCCURRED0_EXTIO_INT2_MASK            0x4000000000000000UL
 612 #define UV4H_EVENT_OCCURRED0_EXTIO_INT3_MASK            0x8000000000000000UL
 613 
 614 #define UVH_EVENT_OCCURRED0_EXTIO_INT0_SHFT (                           \
 615         is_uv1_hub() ? UV1H_EVENT_OCCURRED0_EXTIO_INT0_SHFT :           \
 616         is_uv2_hub() ? UV2H_EVENT_OCCURRED0_EXTIO_INT0_SHFT :           \
 617         is_uv3_hub() ? UV3H_EVENT_OCCURRED0_EXTIO_INT0_SHFT :           \
 618         /*is_uv4_hub*/ UV4H_EVENT_OCCURRED0_EXTIO_INT0_SHFT)
 619 
 620 union uvh_event_occurred0_u {
 621         unsigned long   v;
 622         struct uvh_event_occurred0_s {
 623                 unsigned long   lb_hcerr:1;                     /* RW, W1C */
 624                 unsigned long   rsvd_1_10:10;
 625                 unsigned long   rh_aoerr0:1;                    /* RW, W1C */
 626                 unsigned long   rsvd_12_63:52;
 627         } s;
 628         struct uvxh_event_occurred0_s {
 629                 unsigned long   lb_hcerr:1;                     /* RW */
 630                 unsigned long   rsvd_1:1;
 631                 unsigned long   rh_hcerr:1;                     /* RW */
 632                 unsigned long   lh0_hcerr:1;                    /* RW */
 633                 unsigned long   lh1_hcerr:1;                    /* RW */
 634                 unsigned long   gr0_hcerr:1;                    /* RW */
 635                 unsigned long   gr1_hcerr:1;                    /* RW */
 636                 unsigned long   ni0_hcerr:1;                    /* RW */
 637                 unsigned long   ni1_hcerr:1;                    /* RW */
 638                 unsigned long   lb_aoerr0:1;                    /* RW */
 639                 unsigned long   rsvd_10:1;
 640                 unsigned long   rh_aoerr0:1;                    /* RW */
 641                 unsigned long   lh0_aoerr0:1;                   /* RW */
 642                 unsigned long   lh1_aoerr0:1;                   /* RW */
 643                 unsigned long   gr0_aoerr0:1;                   /* RW */
 644                 unsigned long   gr1_aoerr0:1;                   /* RW */
 645                 unsigned long   xb_aoerr0:1;                    /* RW */
 646                 unsigned long   rsvd_17_63:47;
 647         } sx;
 648         struct uv4h_event_occurred0_s {
 649                 unsigned long   lb_hcerr:1;                     /* RW */
 650                 unsigned long   kt_hcerr:1;                     /* RW */
 651                 unsigned long   rh_hcerr:1;                     /* RW */
 652                 unsigned long   lh0_hcerr:1;                    /* RW */
 653                 unsigned long   lh1_hcerr:1;                    /* RW */
 654                 unsigned long   gr0_hcerr:1;                    /* RW */
 655                 unsigned long   gr1_hcerr:1;                    /* RW */
 656                 unsigned long   ni0_hcerr:1;                    /* RW */
 657                 unsigned long   ni1_hcerr:1;                    /* RW */
 658                 unsigned long   lb_aoerr0:1;                    /* RW */
 659                 unsigned long   kt_aoerr0:1;                    /* RW */
 660                 unsigned long   rh_aoerr0:1;                    /* RW */
 661                 unsigned long   lh0_aoerr0:1;                   /* RW */
 662                 unsigned long   lh1_aoerr0:1;                   /* RW */
 663                 unsigned long   gr0_aoerr0:1;                   /* RW */
 664                 unsigned long   gr1_aoerr0:1;                   /* RW */
 665                 unsigned long   xb_aoerr0:1;                    /* RW */
 666                 unsigned long   rtq0_aoerr0:1;                  /* RW */
 667                 unsigned long   rtq1_aoerr0:1;                  /* RW */
 668                 unsigned long   rtq2_aoerr0:1;                  /* RW */
 669                 unsigned long   rtq3_aoerr0:1;                  /* RW */
 670                 unsigned long   ni0_aoerr0:1;                   /* RW */
 671                 unsigned long   ni1_aoerr0:1;                   /* RW */
 672                 unsigned long   lb_aoerr1:1;                    /* RW */
 673                 unsigned long   kt_aoerr1:1;                    /* RW */
 674                 unsigned long   rh_aoerr1:1;                    /* RW */
 675                 unsigned long   lh0_aoerr1:1;                   /* RW */
 676                 unsigned long   lh1_aoerr1:1;                   /* RW */
 677                 unsigned long   gr0_aoerr1:1;                   /* RW */
 678                 unsigned long   gr1_aoerr1:1;                   /* RW */
 679                 unsigned long   xb_aoerr1:1;                    /* RW */
 680                 unsigned long   rtq0_aoerr1:1;                  /* RW */
 681                 unsigned long   rtq1_aoerr1:1;                  /* RW */
 682                 unsigned long   rtq2_aoerr1:1;                  /* RW */
 683                 unsigned long   rtq3_aoerr1:1;                  /* RW */
 684                 unsigned long   ni0_aoerr1:1;                   /* RW */
 685                 unsigned long   ni1_aoerr1:1;                   /* RW */
 686                 unsigned long   system_shutdown_int:1;          /* RW */
 687                 unsigned long   lb_irq_int_0:1;                 /* RW */
 688                 unsigned long   lb_irq_int_1:1;                 /* RW */
 689                 unsigned long   lb_irq_int_2:1;                 /* RW */
 690                 unsigned long   lb_irq_int_3:1;                 /* RW */
 691                 unsigned long   lb_irq_int_4:1;                 /* RW */
 692                 unsigned long   lb_irq_int_5:1;                 /* RW */
 693                 unsigned long   lb_irq_int_6:1;                 /* RW */
 694                 unsigned long   lb_irq_int_7:1;                 /* RW */
 695                 unsigned long   lb_irq_int_8:1;                 /* RW */
 696                 unsigned long   lb_irq_int_9:1;                 /* RW */
 697                 unsigned long   lb_irq_int_10:1;                /* RW */
 698                 unsigned long   lb_irq_int_11:1;                /* RW */
 699                 unsigned long   lb_irq_int_12:1;                /* RW */
 700                 unsigned long   lb_irq_int_13:1;                /* RW */
 701                 unsigned long   lb_irq_int_14:1;                /* RW */
 702                 unsigned long   lb_irq_int_15:1;                /* RW */
 703                 unsigned long   l1_nmi_int:1;                   /* RW */
 704                 unsigned long   stop_clock:1;                   /* RW */
 705                 unsigned long   asic_to_l1:1;                   /* RW */
 706                 unsigned long   l1_to_asic:1;                   /* RW */
 707                 unsigned long   la_seq_trigger:1;               /* RW */
 708                 unsigned long   ipi_int:1;                      /* RW */
 709                 unsigned long   extio_int0:1;                   /* RW */
 710                 unsigned long   extio_int1:1;                   /* RW */
 711                 unsigned long   extio_int2:1;                   /* RW */
 712                 unsigned long   extio_int3:1;                   /* RW */
 713         } s4;
 714 };
 715 
 716 /* ========================================================================= */
 717 /*                        UVH_EVENT_OCCURRED0_ALIAS                          */
 718 /* ========================================================================= */
 719 #define UVH_EVENT_OCCURRED0_ALIAS 0x70008UL
 720 #define UVH_EVENT_OCCURRED0_ALIAS_32 0x5f0
 721 
 722 
 723 /* ========================================================================= */
 724 /*                         UVH_EXTIO_INT0_BROADCAST                          */
 725 /* ========================================================================= */
 726 #define UVH_EXTIO_INT0_BROADCAST 0x61448UL
 727 
 728 #define UV1H_EXTIO_INT0_BROADCAST_32 0x3f0
 729 #define UV2H_EXTIO_INT0_BROADCAST_32 0x3f0
 730 #define UV3H_EXTIO_INT0_BROADCAST_32 0x3f0
 731 #define UV4H_EXTIO_INT0_BROADCAST_32 0x310
 732 #define UVH_EXTIO_INT0_BROADCAST_32 (                                   \
 733         is_uv1_hub() ? UV1H_EXTIO_INT0_BROADCAST_32 :                   \
 734         is_uv2_hub() ? UV2H_EXTIO_INT0_BROADCAST_32 :                   \
 735         is_uv3_hub() ? UV3H_EXTIO_INT0_BROADCAST_32 :                   \
 736         /*is_uv4_hub*/ UV4H_EXTIO_INT0_BROADCAST_32)
 737 
 738 #define UVH_EXTIO_INT0_BROADCAST_ENABLE_SHFT            0
 739 #define UVH_EXTIO_INT0_BROADCAST_ENABLE_MASK            0x0000000000000001UL
 740 
 741 
 742 union uvh_extio_int0_broadcast_u {
 743         unsigned long   v;
 744         struct uvh_extio_int0_broadcast_s {
 745                 unsigned long   enable:1;                       /* RW */
 746                 unsigned long   rsvd_1_63:63;
 747         } s;
 748 };
 749 
 750 /* ========================================================================= */
 751 /*                         UVH_GR0_TLB_INT0_CONFIG                           */
 752 /* ========================================================================= */
 753 #define UVH_GR0_TLB_INT0_CONFIG 0x61b00UL
 754 
 755 #define UVH_GR0_TLB_INT0_CONFIG_VECTOR_SHFT             0
 756 #define UVH_GR0_TLB_INT0_CONFIG_DM_SHFT                 8
 757 #define UVH_GR0_TLB_INT0_CONFIG_DESTMODE_SHFT           11
 758 #define UVH_GR0_TLB_INT0_CONFIG_STATUS_SHFT             12
 759 #define UVH_GR0_TLB_INT0_CONFIG_P_SHFT                  13
 760 #define UVH_GR0_TLB_INT0_CONFIG_T_SHFT                  15
 761 #define UVH_GR0_TLB_INT0_CONFIG_M_SHFT                  16
 762 #define UVH_GR0_TLB_INT0_CONFIG_APIC_ID_SHFT            32
 763 #define UVH_GR0_TLB_INT0_CONFIG_VECTOR_MASK             0x00000000000000ffUL
 764 #define UVH_GR0_TLB_INT0_CONFIG_DM_MASK                 0x0000000000000700UL
 765 #define UVH_GR0_TLB_INT0_CONFIG_DESTMODE_MASK           0x0000000000000800UL
 766 #define UVH_GR0_TLB_INT0_CONFIG_STATUS_MASK             0x0000000000001000UL
 767 #define UVH_GR0_TLB_INT0_CONFIG_P_MASK                  0x0000000000002000UL
 768 #define UVH_GR0_TLB_INT0_CONFIG_T_MASK                  0x0000000000008000UL
 769 #define UVH_GR0_TLB_INT0_CONFIG_M_MASK                  0x0000000000010000UL
 770 #define UVH_GR0_TLB_INT0_CONFIG_APIC_ID_MASK            0xffffffff00000000UL
 771 
 772 
 773 union uvh_gr0_tlb_int0_config_u {
 774         unsigned long   v;
 775         struct uvh_gr0_tlb_int0_config_s {
 776                 unsigned long   vector_:8;                      /* RW */
 777                 unsigned long   dm:3;                           /* RW */
 778                 unsigned long   destmode:1;                     /* RW */
 779                 unsigned long   status:1;                       /* RO */
 780                 unsigned long   p:1;                            /* RO */
 781                 unsigned long   rsvd_14:1;
 782                 unsigned long   t:1;                            /* RO */
 783                 unsigned long   m:1;                            /* RW */
 784                 unsigned long   rsvd_17_31:15;
 785                 unsigned long   apic_id:32;                     /* RW */
 786         } s;
 787 };
 788 
 789 /* ========================================================================= */
 790 /*                         UVH_GR0_TLB_INT1_CONFIG                           */
 791 /* ========================================================================= */
 792 #define UVH_GR0_TLB_INT1_CONFIG 0x61b40UL
 793 
 794 #define UVH_GR0_TLB_INT1_CONFIG_VECTOR_SHFT             0
 795 #define UVH_GR0_TLB_INT1_CONFIG_DM_SHFT                 8
 796 #define UVH_GR0_TLB_INT1_CONFIG_DESTMODE_SHFT           11
 797 #define UVH_GR0_TLB_INT1_CONFIG_STATUS_SHFT             12
 798 #define UVH_GR0_TLB_INT1_CONFIG_P_SHFT                  13
 799 #define UVH_GR0_TLB_INT1_CONFIG_T_SHFT                  15
 800 #define UVH_GR0_TLB_INT1_CONFIG_M_SHFT                  16
 801 #define UVH_GR0_TLB_INT1_CONFIG_APIC_ID_SHFT            32
 802 #define UVH_GR0_TLB_INT1_CONFIG_VECTOR_MASK             0x00000000000000ffUL
 803 #define UVH_GR0_TLB_INT1_CONFIG_DM_MASK                 0x0000000000000700UL
 804 #define UVH_GR0_TLB_INT1_CONFIG_DESTMODE_MASK           0x0000000000000800UL
 805 #define UVH_GR0_TLB_INT1_CONFIG_STATUS_MASK             0x0000000000001000UL
 806 #define UVH_GR0_TLB_INT1_CONFIG_P_MASK                  0x0000000000002000UL
 807 #define UVH_GR0_TLB_INT1_CONFIG_T_MASK                  0x0000000000008000UL
 808 #define UVH_GR0_TLB_INT1_CONFIG_M_MASK                  0x0000000000010000UL
 809 #define UVH_GR0_TLB_INT1_CONFIG_APIC_ID_MASK            0xffffffff00000000UL
 810 
 811 
 812 union uvh_gr0_tlb_int1_config_u {
 813         unsigned long   v;
 814         struct uvh_gr0_tlb_int1_config_s {
 815                 unsigned long   vector_:8;                      /* RW */
 816                 unsigned long   dm:3;                           /* RW */
 817                 unsigned long   destmode:1;                     /* RW */
 818                 unsigned long   status:1;                       /* RO */
 819                 unsigned long   p:1;                            /* RO */
 820                 unsigned long   rsvd_14:1;
 821                 unsigned long   t:1;                            /* RO */
 822                 unsigned long   m:1;                            /* RW */
 823                 unsigned long   rsvd_17_31:15;
 824                 unsigned long   apic_id:32;                     /* RW */
 825         } s;
 826 };
 827 
 828 /* ========================================================================= */
 829 /*                         UVH_GR0_TLB_MMR_CONTROL                           */
 830 /* ========================================================================= */
 831 #define UV1H_GR0_TLB_MMR_CONTROL 0x401080UL
 832 #define UV2H_GR0_TLB_MMR_CONTROL 0xc01080UL
 833 #define UV3H_GR0_TLB_MMR_CONTROL 0xc01080UL
 834 #define UV4H_GR0_TLB_MMR_CONTROL 0x601080UL
 835 #define UVH_GR0_TLB_MMR_CONTROL (                                       \
 836         is_uv1_hub() ? UV1H_GR0_TLB_MMR_CONTROL :                       \
 837         is_uv2_hub() ? UV2H_GR0_TLB_MMR_CONTROL :                       \
 838         is_uv3_hub() ? UV3H_GR0_TLB_MMR_CONTROL :                       \
 839         /*is_uv4_hub*/ UV4H_GR0_TLB_MMR_CONTROL)
 840 
 841 #define UVH_GR0_TLB_MMR_CONTROL_INDEX_SHFT              0
 842 #define UVH_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT      16
 843 #define UVH_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT  20
 844 #define UVH_GR0_TLB_MMR_CONTROL_MMR_WRITE_SHFT          30
 845 #define UVH_GR0_TLB_MMR_CONTROL_MMR_READ_SHFT           31
 846 #define UVH_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK      0x0000000000010000UL
 847 #define UVH_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK  0x0000000000100000UL
 848 #define UVH_GR0_TLB_MMR_CONTROL_MMR_WRITE_MASK          0x0000000040000000UL
 849 #define UVH_GR0_TLB_MMR_CONTROL_MMR_READ_MASK           0x0000000080000000UL
 850 
 851 #define UV1H_GR0_TLB_MMR_CONTROL_INDEX_SHFT             0
 852 #define UV1H_GR0_TLB_MMR_CONTROL_MEM_SEL_SHFT           12
 853 #define UV1H_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT     16
 854 #define UV1H_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT 20
 855 #define UV1H_GR0_TLB_MMR_CONTROL_MMR_WRITE_SHFT         30
 856 #define UV1H_GR0_TLB_MMR_CONTROL_MMR_READ_SHFT          31
 857 #define UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_CON_SHFT       48
 858 #define UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBRAM_SHFT    52
 859 #define UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBPGSIZE_SHFT 54
 860 #define UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBRREG_SHFT   56
 861 #define UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBLRUV_SHFT   60
 862 #define UV1H_GR0_TLB_MMR_CONTROL_INDEX_MASK             0x0000000000000fffUL
 863 #define UV1H_GR0_TLB_MMR_CONTROL_MEM_SEL_MASK           0x0000000000003000UL
 864 #define UV1H_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK     0x0000000000010000UL
 865 #define UV1H_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK 0x0000000000100000UL
 866 #define UV1H_GR0_TLB_MMR_CONTROL_MMR_WRITE_MASK         0x0000000040000000UL
 867 #define UV1H_GR0_TLB_MMR_CONTROL_MMR_READ_MASK          0x0000000080000000UL
 868 #define UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_CON_MASK       0x0001000000000000UL
 869 #define UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBRAM_MASK    0x0010000000000000UL
 870 #define UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBPGSIZE_MASK 0x0040000000000000UL
 871 #define UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBRREG_MASK   0x0100000000000000UL
 872 #define UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBLRUV_MASK   0x1000000000000000UL
 873 
 874 #define UVXH_GR0_TLB_MMR_CONTROL_INDEX_SHFT             0
 875 #define UVXH_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT     16
 876 #define UVXH_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT 20
 877 #define UVXH_GR0_TLB_MMR_CONTROL_MMR_WRITE_SHFT         30
 878 #define UVXH_GR0_TLB_MMR_CONTROL_MMR_READ_SHFT          31
 879 #define UVXH_GR0_TLB_MMR_CONTROL_MMR_OP_DONE_SHFT       32
 880 #define UVXH_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK     0x0000000000010000UL
 881 #define UVXH_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK 0x0000000000100000UL
 882 #define UVXH_GR0_TLB_MMR_CONTROL_MMR_WRITE_MASK         0x0000000040000000UL
 883 #define UVXH_GR0_TLB_MMR_CONTROL_MMR_READ_MASK          0x0000000080000000UL
 884 #define UVXH_GR0_TLB_MMR_CONTROL_MMR_OP_DONE_MASK       0x0000000100000000UL
 885 
 886 #define UV2H_GR0_TLB_MMR_CONTROL_INDEX_SHFT             0
 887 #define UV2H_GR0_TLB_MMR_CONTROL_MEM_SEL_SHFT           12
 888 #define UV2H_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT     16
 889 #define UV2H_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT 20
 890 #define UV2H_GR0_TLB_MMR_CONTROL_MMR_WRITE_SHFT         30
 891 #define UV2H_GR0_TLB_MMR_CONTROL_MMR_READ_SHFT          31
 892 #define UV2H_GR0_TLB_MMR_CONTROL_MMR_OP_DONE_SHFT       32
 893 #define UV2H_GR0_TLB_MMR_CONTROL_MMR_INJ_CON_SHFT       48
 894 #define UV2H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBRAM_SHFT    52
 895 #define UV2H_GR0_TLB_MMR_CONTROL_INDEX_MASK             0x0000000000000fffUL
 896 #define UV2H_GR0_TLB_MMR_CONTROL_MEM_SEL_MASK           0x0000000000003000UL
 897 #define UV2H_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK     0x0000000000010000UL
 898 #define UV2H_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK 0x0000000000100000UL
 899 #define UV2H_GR0_TLB_MMR_CONTROL_MMR_WRITE_MASK         0x0000000040000000UL
 900 #define UV2H_GR0_TLB_MMR_CONTROL_MMR_READ_MASK          0x0000000080000000UL
 901 #define UV2H_GR0_TLB_MMR_CONTROL_MMR_OP_DONE_MASK       0x0000000100000000UL
 902 #define UV2H_GR0_TLB_MMR_CONTROL_MMR_INJ_CON_MASK       0x0001000000000000UL
 903 #define UV2H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBRAM_MASK    0x0010000000000000UL
 904 
 905 #define UV3H_GR0_TLB_MMR_CONTROL_INDEX_SHFT             0
 906 #define UV3H_GR0_TLB_MMR_CONTROL_MEM_SEL_SHFT           12
 907 #define UV3H_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT     16
 908 #define UV3H_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT 20
 909 #define UV3H_GR0_TLB_MMR_CONTROL_ECC_SEL_SHFT           21
 910 #define UV3H_GR0_TLB_MMR_CONTROL_MMR_WRITE_SHFT         30
 911 #define UV3H_GR0_TLB_MMR_CONTROL_MMR_READ_SHFT          31
 912 #define UV3H_GR0_TLB_MMR_CONTROL_MMR_OP_DONE_SHFT       32
 913 #define UV3H_GR0_TLB_MMR_CONTROL_INDEX_MASK             0x0000000000000fffUL
 914 #define UV3H_GR0_TLB_MMR_CONTROL_MEM_SEL_MASK           0x0000000000003000UL
 915 #define UV3H_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK     0x0000000000010000UL
 916 #define UV3H_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK 0x0000000000100000UL
 917 #define UV3H_GR0_TLB_MMR_CONTROL_ECC_SEL_MASK           0x0000000000200000UL
 918 #define UV3H_GR0_TLB_MMR_CONTROL_MMR_WRITE_MASK         0x0000000040000000UL
 919 #define UV3H_GR0_TLB_MMR_CONTROL_MMR_READ_MASK          0x0000000080000000UL
 920 #define UV3H_GR0_TLB_MMR_CONTROL_MMR_OP_DONE_MASK       0x0000000100000000UL
 921 
 922 #define UV4H_GR0_TLB_MMR_CONTROL_INDEX_SHFT             0
 923 #define UV4H_GR0_TLB_MMR_CONTROL_MEM_SEL_SHFT           13
 924 #define UV4H_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT     16
 925 #define UV4H_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT 20
 926 #define UV4H_GR0_TLB_MMR_CONTROL_ECC_SEL_SHFT           21
 927 #define UV4H_GR0_TLB_MMR_CONTROL_MMR_WRITE_SHFT         30
 928 #define UV4H_GR0_TLB_MMR_CONTROL_MMR_READ_SHFT          31
 929 #define UV4H_GR0_TLB_MMR_CONTROL_MMR_OP_DONE_SHFT       32
 930 #define UV4H_GR0_TLB_MMR_CONTROL_PAGE_SIZE_SHFT         59
 931 #define UV4H_GR0_TLB_MMR_CONTROL_INDEX_MASK             0x0000000000001fffUL
 932 #define UV4H_GR0_TLB_MMR_CONTROL_MEM_SEL_MASK           0x0000000000006000UL
 933 #define UV4H_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK     0x0000000000010000UL
 934 #define UV4H_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK 0x0000000000100000UL
 935 #define UV4H_GR0_TLB_MMR_CONTROL_ECC_SEL_MASK           0x0000000000200000UL
 936 #define UV4H_GR0_TLB_MMR_CONTROL_MMR_WRITE_MASK         0x0000000040000000UL
 937 #define UV4H_GR0_TLB_MMR_CONTROL_MMR_READ_MASK          0x0000000080000000UL
 938 #define UV4H_GR0_TLB_MMR_CONTROL_MMR_OP_DONE_MASK       0x0000000100000000UL
 939 #define UV4H_GR0_TLB_MMR_CONTROL_PAGE_SIZE_MASK         0xf800000000000000UL
 940 
 941 #define UVH_GR0_TLB_MMR_CONTROL_INDEX_MASK (                            \
 942         is_uv1_hub() ? UV1H_GR0_TLB_MMR_CONTROL_INDEX_MASK :            \
 943         is_uv2_hub() ? UV2H_GR0_TLB_MMR_CONTROL_INDEX_MASK :            \
 944         is_uv3_hub() ? UV3H_GR0_TLB_MMR_CONTROL_INDEX_MASK :            \
 945         /*is_uv4_hub*/ UV4H_GR0_TLB_MMR_CONTROL_INDEX_MASK)
 946 #define UVH_GR0_TLB_MMR_CONTROL_MEM_SEL_MASK (                          \
 947         is_uv1_hub() ? UV1H_GR0_TLB_MMR_CONTROL_MEM_SEL_MASK :          \
 948         is_uv2_hub() ? UV2H_GR0_TLB_MMR_CONTROL_MEM_SEL_MASK :          \
 949         is_uv3_hub() ? UV3H_GR0_TLB_MMR_CONTROL_MEM_SEL_MASK :          \
 950         /*is_uv4_hub*/ UV4H_GR0_TLB_MMR_CONTROL_MEM_SEL_MASK)
 951 #define UVH_GR0_TLB_MMR_CONTROL_MEM_SEL_SHFT (                          \
 952         is_uv1_hub() ? UV1H_GR0_TLB_MMR_CONTROL_MEM_SEL_SHFT :          \
 953         is_uv2_hub() ? UV2H_GR0_TLB_MMR_CONTROL_MEM_SEL_SHFT :          \
 954         is_uv3_hub() ? UV3H_GR0_TLB_MMR_CONTROL_MEM_SEL_SHFT :          \
 955         /*is_uv4_hub*/ UV4H_GR0_TLB_MMR_CONTROL_MEM_SEL_SHFT)
 956 
 957 union uvh_gr0_tlb_mmr_control_u {
 958         unsigned long   v;
 959         struct uvh_gr0_tlb_mmr_control_s {
 960                 unsigned long   rsvd_0_15:16;
 961                 unsigned long   auto_valid_en:1;                /* RW */
 962                 unsigned long   rsvd_17_19:3;
 963                 unsigned long   mmr_hash_index_en:1;            /* RW */
 964                 unsigned long   rsvd_21_29:9;
 965                 unsigned long   mmr_write:1;                    /* WP */
 966                 unsigned long   mmr_read:1;                     /* WP */
 967                 unsigned long   rsvd_32_48:17;
 968                 unsigned long   rsvd_49_51:3;
 969                 unsigned long   rsvd_52_63:12;
 970         } s;
 971         struct uv1h_gr0_tlb_mmr_control_s {
 972                 unsigned long   index:12;                       /* RW */
 973                 unsigned long   mem_sel:2;                      /* RW */
 974                 unsigned long   rsvd_14_15:2;
 975                 unsigned long   auto_valid_en:1;                /* RW */
 976                 unsigned long   rsvd_17_19:3;
 977                 unsigned long   mmr_hash_index_en:1;            /* RW */
 978                 unsigned long   rsvd_21_29:9;
 979                 unsigned long   mmr_write:1;                    /* WP */
 980                 unsigned long   mmr_read:1;                     /* WP */
 981                 unsigned long   rsvd_32_47:16;
 982                 unsigned long   mmr_inj_con:1;                  /* RW */
 983                 unsigned long   rsvd_49_51:3;
 984                 unsigned long   mmr_inj_tlbram:1;               /* RW */
 985                 unsigned long   rsvd_53:1;
 986                 unsigned long   mmr_inj_tlbpgsize:1;            /* RW */
 987                 unsigned long   rsvd_55:1;
 988                 unsigned long   mmr_inj_tlbrreg:1;              /* RW */
 989                 unsigned long   rsvd_57_59:3;
 990                 unsigned long   mmr_inj_tlblruv:1;              /* RW */
 991                 unsigned long   rsvd_61_63:3;
 992         } s1;
 993         struct uvxh_gr0_tlb_mmr_control_s {
 994                 unsigned long   rsvd_0_15:16;
 995                 unsigned long   auto_valid_en:1;                /* RW */
 996                 unsigned long   rsvd_17_19:3;
 997                 unsigned long   mmr_hash_index_en:1;            /* RW */
 998                 unsigned long   rsvd_21_29:9;
 999                 unsigned long   mmr_write:1;                    /* WP */
1000                 unsigned long   mmr_read:1;                     /* WP */
1001                 unsigned long   mmr_op_done:1;                  /* RW */
1002                 unsigned long   rsvd_33_47:15;
1003                 unsigned long   rsvd_48:1;
1004                 unsigned long   rsvd_49_51:3;
1005                 unsigned long   rsvd_52_63:12;
1006         } sx;
1007         struct uv2h_gr0_tlb_mmr_control_s {
1008                 unsigned long   index:12;                       /* RW */
1009                 unsigned long   mem_sel:2;                      /* RW */
1010                 unsigned long   rsvd_14_15:2;
1011                 unsigned long   auto_valid_en:1;                /* RW */
1012                 unsigned long   rsvd_17_19:3;
1013                 unsigned long   mmr_hash_index_en:1;            /* RW */
1014                 unsigned long   rsvd_21_29:9;
1015                 unsigned long   mmr_write:1;                    /* WP */
1016                 unsigned long   mmr_read:1;                     /* WP */
1017                 unsigned long   mmr_op_done:1;                  /* RW */
1018                 unsigned long   rsvd_33_47:15;
1019                 unsigned long   mmr_inj_con:1;                  /* RW */
1020                 unsigned long   rsvd_49_51:3;
1021                 unsigned long   mmr_inj_tlbram:1;               /* RW */
1022                 unsigned long   rsvd_53_63:11;
1023         } s2;
1024         struct uv3h_gr0_tlb_mmr_control_s {
1025                 unsigned long   index:12;                       /* RW */
1026                 unsigned long   mem_sel:2;                      /* RW */
1027                 unsigned long   rsvd_14_15:2;
1028                 unsigned long   auto_valid_en:1;                /* RW */
1029                 unsigned long   rsvd_17_19:3;
1030                 unsigned long   mmr_hash_index_en:1;            /* RW */
1031                 unsigned long   ecc_sel:1;                      /* RW */
1032                 unsigned long   rsvd_22_29:8;
1033                 unsigned long   mmr_write:1;                    /* WP */
1034                 unsigned long   mmr_read:1;                     /* WP */
1035                 unsigned long   mmr_op_done:1;                  /* RW */
1036                 unsigned long   rsvd_33_47:15;
1037                 unsigned long   undef_48:1;                     /* Undefined */
1038                 unsigned long   rsvd_49_51:3;
1039                 unsigned long   undef_52:1;                     /* Undefined */
1040                 unsigned long   rsvd_53_63:11;
1041         } s3;
1042         struct uv4h_gr0_tlb_mmr_control_s {
1043                 unsigned long   index:13;                       /* RW */
1044                 unsigned long   mem_sel:2;                      /* RW */
1045                 unsigned long   rsvd_15:1;
1046                 unsigned long   auto_valid_en:1;                /* RW */
1047                 unsigned long   rsvd_17_19:3;
1048                 unsigned long   mmr_hash_index_en:1;            /* RW */
1049                 unsigned long   ecc_sel:1;                      /* RW */
1050                 unsigned long   rsvd_22_29:8;
1051                 unsigned long   mmr_write:1;                    /* WP */
1052                 unsigned long   mmr_read:1;                     /* WP */
1053                 unsigned long   mmr_op_done:1;                  /* RW */
1054                 unsigned long   rsvd_33_47:15;
1055                 unsigned long   undef_48:1;                     /* Undefined */
1056                 unsigned long   rsvd_49_51:3;
1057                 unsigned long   rsvd_52_58:7;
1058                 unsigned long   page_size:5;                    /* RW */
1059         } s4;
1060 };
1061 
1062 /* ========================================================================= */
1063 /*                       UVH_GR0_TLB_MMR_READ_DATA_HI                        */
1064 /* ========================================================================= */
1065 #define UV1H_GR0_TLB_MMR_READ_DATA_HI 0x4010a0UL
1066 #define UV2H_GR0_TLB_MMR_READ_DATA_HI 0xc010a0UL
1067 #define UV3H_GR0_TLB_MMR_READ_DATA_HI 0xc010a0UL
1068 #define UV4H_GR0_TLB_MMR_READ_DATA_HI 0x6010a0UL
1069 #define UVH_GR0_TLB_MMR_READ_DATA_HI (                                  \
1070         is_uv1_hub() ? UV1H_GR0_TLB_MMR_READ_DATA_HI :                  \
1071         is_uv2_hub() ? UV2H_GR0_TLB_MMR_READ_DATA_HI :                  \
1072         is_uv3_hub() ? UV3H_GR0_TLB_MMR_READ_DATA_HI :                  \
1073         /*is_uv4_hub*/ UV4H_GR0_TLB_MMR_READ_DATA_HI)
1074 
1075 #define UVH_GR0_TLB_MMR_READ_DATA_HI_PFN_SHFT           0
1076 
1077 #define UV1H_GR0_TLB_MMR_READ_DATA_HI_PFN_SHFT          0
1078 #define UV1H_GR0_TLB_MMR_READ_DATA_HI_GAA_SHFT          41
1079 #define UV1H_GR0_TLB_MMR_READ_DATA_HI_DIRTY_SHFT        43
1080 #define UV1H_GR0_TLB_MMR_READ_DATA_HI_LARGER_SHFT       44
1081 #define UV1H_GR0_TLB_MMR_READ_DATA_HI_PFN_MASK          0x000001ffffffffffUL
1082 #define UV1H_GR0_TLB_MMR_READ_DATA_HI_GAA_MASK          0x0000060000000000UL
1083 #define UV1H_GR0_TLB_MMR_READ_DATA_HI_DIRTY_MASK        0x0000080000000000UL
1084 #define UV1H_GR0_TLB_MMR_READ_DATA_HI_LARGER_MASK       0x0000100000000000UL
1085 
1086 #define UVXH_GR0_TLB_MMR_READ_DATA_HI_PFN_SHFT          0
1087 
1088 #define UV2H_GR0_TLB_MMR_READ_DATA_HI_PFN_SHFT          0
1089 #define UV2H_GR0_TLB_MMR_READ_DATA_HI_GAA_SHFT          41
1090 #define UV2H_GR0_TLB_MMR_READ_DATA_HI_DIRTY_SHFT        43
1091 #define UV2H_GR0_TLB_MMR_READ_DATA_HI_LARGER_SHFT       44
1092 #define UV2H_GR0_TLB_MMR_READ_DATA_HI_PFN_MASK          0x000001ffffffffffUL
1093 #define UV2H_GR0_TLB_MMR_READ_DATA_HI_GAA_MASK          0x0000060000000000UL
1094 #define UV2H_GR0_TLB_MMR_READ_DATA_HI_DIRTY_MASK        0x0000080000000000UL
1095 #define UV2H_GR0_TLB_MMR_READ_DATA_HI_LARGER_MASK       0x0000100000000000UL
1096 
1097 #define UV3H_GR0_TLB_MMR_READ_DATA_HI_PFN_SHFT          0
1098 #define UV3H_GR0_TLB_MMR_READ_DATA_HI_GAA_SHFT          41
1099 #define UV3H_GR0_TLB_MMR_READ_DATA_HI_DIRTY_SHFT        43
1100 #define UV3H_GR0_TLB_MMR_READ_DATA_HI_LARGER_SHFT       44
1101 #define UV3H_GR0_TLB_MMR_READ_DATA_HI_AA_EXT_SHFT       45
1102 #define UV3H_GR0_TLB_MMR_READ_DATA_HI_WAY_ECC_SHFT      55
1103 #define UV3H_GR0_TLB_MMR_READ_DATA_HI_PFN_MASK          0x000001ffffffffffUL
1104 #define UV3H_GR0_TLB_MMR_READ_DATA_HI_GAA_MASK          0x0000060000000000UL
1105 #define UV3H_GR0_TLB_MMR_READ_DATA_HI_DIRTY_MASK        0x0000080000000000UL
1106 #define UV3H_GR0_TLB_MMR_READ_DATA_HI_LARGER_MASK       0x0000100000000000UL
1107 #define UV3H_GR0_TLB_MMR_READ_DATA_HI_AA_EXT_MASK       0x0000200000000000UL
1108 #define UV3H_GR0_TLB_MMR_READ_DATA_HI_WAY_ECC_MASK      0xff80000000000000UL
1109 
1110 #define UV4H_GR0_TLB_MMR_READ_DATA_HI_PFN_SHFT          0
1111 #define UV4H_GR0_TLB_MMR_READ_DATA_HI_PNID_SHFT         34
1112 #define UV4H_GR0_TLB_MMR_READ_DATA_HI_GAA_SHFT          49
1113 #define UV4H_GR0_TLB_MMR_READ_DATA_HI_DIRTY_SHFT        51
1114 #define UV4H_GR0_TLB_MMR_READ_DATA_HI_LARGER_SHFT       52
1115 #define UV4H_GR0_TLB_MMR_READ_DATA_HI_AA_EXT_SHFT       53
1116 #define UV4H_GR0_TLB_MMR_READ_DATA_HI_WAY_ECC_SHFT      55
1117 #define UV4H_GR0_TLB_MMR_READ_DATA_HI_PFN_MASK          0x00000003ffffffffUL
1118 #define UV4H_GR0_TLB_MMR_READ_DATA_HI_PNID_MASK         0x0001fffc00000000UL
1119 #define UV4H_GR0_TLB_MMR_READ_DATA_HI_GAA_MASK          0x0006000000000000UL
1120 #define UV4H_GR0_TLB_MMR_READ_DATA_HI_DIRTY_MASK        0x0008000000000000UL
1121 #define UV4H_GR0_TLB_MMR_READ_DATA_HI_LARGER_MASK       0x0010000000000000UL
1122 #define UV4H_GR0_TLB_MMR_READ_DATA_HI_AA_EXT_MASK       0x0020000000000000UL
1123 #define UV4H_GR0_TLB_MMR_READ_DATA_HI_WAY_ECC_MASK      0xff80000000000000UL
1124 
1125 
1126 union uvh_gr0_tlb_mmr_read_data_hi_u {
1127         unsigned long   v;
1128         struct uv1h_gr0_tlb_mmr_read_data_hi_s {
1129                 unsigned long   pfn:41;                         /* RO */
1130                 unsigned long   gaa:2;                          /* RO */
1131                 unsigned long   dirty:1;                        /* RO */
1132                 unsigned long   larger:1;                       /* RO */
1133                 unsigned long   rsvd_45_63:19;
1134         } s1;
1135         struct uv2h_gr0_tlb_mmr_read_data_hi_s {
1136                 unsigned long   pfn:41;                         /* RO */
1137                 unsigned long   gaa:2;                          /* RO */
1138                 unsigned long   dirty:1;                        /* RO */
1139                 unsigned long   larger:1;                       /* RO */
1140                 unsigned long   rsvd_45_63:19;
1141         } s2;
1142         struct uv3h_gr0_tlb_mmr_read_data_hi_s {
1143                 unsigned long   pfn:41;                         /* RO */
1144                 unsigned long   gaa:2;                          /* RO */
1145                 unsigned long   dirty:1;                        /* RO */
1146                 unsigned long   larger:1;                       /* RO */
1147                 unsigned long   aa_ext:1;                       /* RO */
1148                 unsigned long   undef_46_54:9;                  /* Undefined */
1149                 unsigned long   way_ecc:9;                      /* RO */
1150         } s3;
1151         struct uv4h_gr0_tlb_mmr_read_data_hi_s {
1152                 unsigned long   pfn:34;                         /* RO */
1153                 unsigned long   pnid:15;                        /* RO */
1154                 unsigned long   gaa:2;                          /* RO */
1155                 unsigned long   dirty:1;                        /* RO */
1156                 unsigned long   larger:1;                       /* RO */
1157                 unsigned long   aa_ext:1;                       /* RO */
1158                 unsigned long   undef_54:1;                     /* Undefined */
1159                 unsigned long   way_ecc:9;                      /* RO */
1160         } s4;
1161 };
1162 
1163 /* ========================================================================= */
1164 /*                       UVH_GR0_TLB_MMR_READ_DATA_LO                        */
1165 /* ========================================================================= */
1166 #define UV1H_GR0_TLB_MMR_READ_DATA_LO 0x4010a8UL
1167 #define UV2H_GR0_TLB_MMR_READ_DATA_LO 0xc010a8UL
1168 #define UV3H_GR0_TLB_MMR_READ_DATA_LO 0xc010a8UL
1169 #define UV4H_GR0_TLB_MMR_READ_DATA_LO 0x6010a8UL
1170 #define UVH_GR0_TLB_MMR_READ_DATA_LO (                                  \
1171         is_uv1_hub() ? UV1H_GR0_TLB_MMR_READ_DATA_LO :                  \
1172         is_uv2_hub() ? UV2H_GR0_TLB_MMR_READ_DATA_LO :                  \
1173         is_uv3_hub() ? UV3H_GR0_TLB_MMR_READ_DATA_LO :                  \
1174         /*is_uv4_hub*/ UV4H_GR0_TLB_MMR_READ_DATA_LO)
1175 
1176 #define UVH_GR0_TLB_MMR_READ_DATA_LO_VPN_SHFT           0
1177 #define UVH_GR0_TLB_MMR_READ_DATA_LO_ASID_SHFT          39
1178 #define UVH_GR0_TLB_MMR_READ_DATA_LO_VALID_SHFT         63
1179 #define UVH_GR0_TLB_MMR_READ_DATA_LO_VPN_MASK           0x0000007fffffffffUL
1180 #define UVH_GR0_TLB_MMR_READ_DATA_LO_ASID_MASK          0x7fffff8000000000UL
1181 #define UVH_GR0_TLB_MMR_READ_DATA_LO_VALID_MASK         0x8000000000000000UL
1182 
1183 #define UV1H_GR0_TLB_MMR_READ_DATA_LO_VPN_SHFT          0
1184 #define UV1H_GR0_TLB_MMR_READ_DATA_LO_ASID_SHFT         39
1185 #define UV1H_GR0_TLB_MMR_READ_DATA_LO_VALID_SHFT        63
1186 #define UV1H_GR0_TLB_MMR_READ_DATA_LO_VPN_MASK          0x0000007fffffffffUL
1187 #define UV1H_GR0_TLB_MMR_READ_DATA_LO_ASID_MASK         0x7fffff8000000000UL
1188 #define UV1H_GR0_TLB_MMR_READ_DATA_LO_VALID_MASK        0x8000000000000000UL
1189 
1190 #define UVXH_GR0_TLB_MMR_READ_DATA_LO_VPN_SHFT          0
1191 #define UVXH_GR0_TLB_MMR_READ_DATA_LO_ASID_SHFT         39
1192 #define UVXH_GR0_TLB_MMR_READ_DATA_LO_VALID_SHFT        63
1193 #define UVXH_GR0_TLB_MMR_READ_DATA_LO_VPN_MASK          0x0000007fffffffffUL
1194 #define UVXH_GR0_TLB_MMR_READ_DATA_LO_ASID_MASK         0x7fffff8000000000UL
1195 #define UVXH_GR0_TLB_MMR_READ_DATA_LO_VALID_MASK        0x8000000000000000UL
1196 
1197 #define UV2H_GR0_TLB_MMR_READ_DATA_LO_VPN_SHFT          0
1198 #define UV2H_GR0_TLB_MMR_READ_DATA_LO_ASID_SHFT         39
1199 #define UV2H_GR0_TLB_MMR_READ_DATA_LO_VALID_SHFT        63
1200 #define UV2H_GR0_TLB_MMR_READ_DATA_LO_VPN_MASK          0x0000007fffffffffUL
1201 #define UV2H_GR0_TLB_MMR_READ_DATA_LO_ASID_MASK         0x7fffff8000000000UL
1202 #define UV2H_GR0_TLB_MMR_READ_DATA_LO_VALID_MASK        0x8000000000000000UL
1203 
1204 #define UV3H_GR0_TLB_MMR_READ_DATA_LO_VPN_SHFT          0
1205 #define UV3H_GR0_TLB_MMR_READ_DATA_LO_ASID_SHFT         39
1206 #define UV3H_GR0_TLB_MMR_READ_DATA_LO_VALID_SHFT        63
1207 #define UV3H_GR0_TLB_MMR_READ_DATA_LO_VPN_MASK          0x0000007fffffffffUL
1208 #define UV3H_GR0_TLB_MMR_READ_DATA_LO_ASID_MASK         0x7fffff8000000000UL
1209 #define UV3H_GR0_TLB_MMR_READ_DATA_LO_VALID_MASK        0x8000000000000000UL
1210 
1211 #define UV4H_GR0_TLB_MMR_READ_DATA_LO_VPN_SHFT          0
1212 #define UV4H_GR0_TLB_MMR_READ_DATA_LO_ASID_SHFT         39
1213 #define UV4H_GR0_TLB_MMR_READ_DATA_LO_VALID_SHFT        63
1214 #define UV4H_GR0_TLB_MMR_READ_DATA_LO_VPN_MASK          0x0000007fffffffffUL
1215 #define UV4H_GR0_TLB_MMR_READ_DATA_LO_ASID_MASK         0x7fffff8000000000UL
1216 #define UV4H_GR0_TLB_MMR_READ_DATA_LO_VALID_MASK        0x8000000000000000UL
1217 
1218 
1219 union uvh_gr0_tlb_mmr_read_data_lo_u {
1220         unsigned long   v;
1221         struct uvh_gr0_tlb_mmr_read_data_lo_s {
1222                 unsigned long   vpn:39;                         /* RO */
1223                 unsigned long   asid:24;                        /* RO */
1224                 unsigned long   valid:1;                        /* RO */
1225         } s;
1226         struct uv1h_gr0_tlb_mmr_read_data_lo_s {
1227                 unsigned long   vpn:39;                         /* RO */
1228                 unsigned long   asid:24;                        /* RO */
1229                 unsigned long   valid:1;                        /* RO */
1230         } s1;
1231         struct uvxh_gr0_tlb_mmr_read_data_lo_s {
1232                 unsigned long   vpn:39;                         /* RO */
1233                 unsigned long   asid:24;                        /* RO */
1234                 unsigned long   valid:1;                        /* RO */
1235         } sx;
1236         struct uv2h_gr0_tlb_mmr_read_data_lo_s {
1237                 unsigned long   vpn:39;                         /* RO */
1238                 unsigned long   asid:24;                        /* RO */
1239                 unsigned long   valid:1;                        /* RO */
1240         } s2;
1241         struct uv3h_gr0_tlb_mmr_read_data_lo_s {
1242                 unsigned long   vpn:39;                         /* RO */
1243                 unsigned long   asid:24;                        /* RO */
1244                 unsigned long   valid:1;                        /* RO */
1245         } s3;
1246         struct uv4h_gr0_tlb_mmr_read_data_lo_s {
1247                 unsigned long   vpn:39;                         /* RO */
1248                 unsigned long   asid:24;                        /* RO */
1249                 unsigned long   valid:1;                        /* RO */
1250         } s4;
1251 };
1252 
1253 /* ========================================================================= */
1254 /*                         UVH_GR1_TLB_INT0_CONFIG                           */
1255 /* ========================================================================= */
1256 #define UV1H_GR1_TLB_INT0_CONFIG 0x61f00UL
1257 #define UV2H_GR1_TLB_INT0_CONFIG 0x61f00UL
1258 #define UV3H_GR1_TLB_INT0_CONFIG 0x61f00UL
1259 #define UV4H_GR1_TLB_INT0_CONFIG 0x62100UL
1260 #define UVH_GR1_TLB_INT0_CONFIG (                                       \
1261         is_uv1_hub() ? UV1H_GR1_TLB_INT0_CONFIG :                       \
1262         is_uv2_hub() ? UV2H_GR1_TLB_INT0_CONFIG :                       \
1263         is_uv3_hub() ? UV3H_GR1_TLB_INT0_CONFIG :                       \
1264         /*is_uv4_hub*/ UV4H_GR1_TLB_INT0_CONFIG)
1265 
1266 #define UVH_GR1_TLB_INT0_CONFIG_VECTOR_SHFT             0
1267 #define UVH_GR1_TLB_INT0_CONFIG_DM_SHFT                 8
1268 #define UVH_GR1_TLB_INT0_CONFIG_DESTMODE_SHFT           11
1269 #define UVH_GR1_TLB_INT0_CONFIG_STATUS_SHFT             12
1270 #define UVH_GR1_TLB_INT0_CONFIG_P_SHFT                  13
1271 #define UVH_GR1_TLB_INT0_CONFIG_T_SHFT                  15
1272 #define UVH_GR1_TLB_INT0_CONFIG_M_SHFT                  16
1273 #define UVH_GR1_TLB_INT0_CONFIG_APIC_ID_SHFT            32
1274 #define UVH_GR1_TLB_INT0_CONFIG_VECTOR_MASK             0x00000000000000ffUL
1275 #define UVH_GR1_TLB_INT0_CONFIG_DM_MASK                 0x0000000000000700UL
1276 #define UVH_GR1_TLB_INT0_CONFIG_DESTMODE_MASK           0x0000000000000800UL
1277 #define UVH_GR1_TLB_INT0_CONFIG_STATUS_MASK             0x0000000000001000UL
1278 #define UVH_GR1_TLB_INT0_CONFIG_P_MASK                  0x0000000000002000UL
1279 #define UVH_GR1_TLB_INT0_CONFIG_T_MASK                  0x0000000000008000UL
1280 #define UVH_GR1_TLB_INT0_CONFIG_M_MASK                  0x0000000000010000UL
1281 #define UVH_GR1_TLB_INT0_CONFIG_APIC_ID_MASK            0xffffffff00000000UL
1282 
1283 
1284 union uvh_gr1_tlb_int0_config_u {
1285         unsigned long   v;
1286         struct uvh_gr1_tlb_int0_config_s {
1287                 unsigned long   vector_:8;                      /* RW */
1288                 unsigned long   dm:3;                           /* RW */
1289                 unsigned long   destmode:1;                     /* RW */
1290                 unsigned long   status:1;                       /* RO */
1291                 unsigned long   p:1;                            /* RO */
1292                 unsigned long   rsvd_14:1;
1293                 unsigned long   t:1;                            /* RO */
1294                 unsigned long   m:1;                            /* RW */
1295                 unsigned long   rsvd_17_31:15;
1296                 unsigned long   apic_id:32;                     /* RW */
1297         } s;
1298 };
1299 
1300 /* ========================================================================= */
1301 /*                         UVH_GR1_TLB_INT1_CONFIG                           */
1302 /* ========================================================================= */
1303 #define UV1H_GR1_TLB_INT1_CONFIG 0x61f40UL
1304 #define UV2H_GR1_TLB_INT1_CONFIG 0x61f40UL
1305 #define UV3H_GR1_TLB_INT1_CONFIG 0x61f40UL
1306 #define UV4H_GR1_TLB_INT1_CONFIG 0x62140UL
1307 #define UVH_GR1_TLB_INT1_CONFIG (                                       \
1308         is_uv1_hub() ? UV1H_GR1_TLB_INT1_CONFIG :                       \
1309         is_uv2_hub() ? UV2H_GR1_TLB_INT1_CONFIG :                       \
1310         is_uv3_hub() ? UV3H_GR1_TLB_INT1_CONFIG :                       \
1311         /*is_uv4_hub*/ UV4H_GR1_TLB_INT1_CONFIG)
1312 
1313 #define UVH_GR1_TLB_INT1_CONFIG_VECTOR_SHFT             0
1314 #define UVH_GR1_TLB_INT1_CONFIG_DM_SHFT                 8
1315 #define UVH_GR1_TLB_INT1_CONFIG_DESTMODE_SHFT           11
1316 #define UVH_GR1_TLB_INT1_CONFIG_STATUS_SHFT             12
1317 #define UVH_GR1_TLB_INT1_CONFIG_P_SHFT                  13
1318 #define UVH_GR1_TLB_INT1_CONFIG_T_SHFT                  15
1319 #define UVH_GR1_TLB_INT1_CONFIG_M_SHFT                  16
1320 #define UVH_GR1_TLB_INT1_CONFIG_APIC_ID_SHFT            32
1321 #define UVH_GR1_TLB_INT1_CONFIG_VECTOR_MASK             0x00000000000000ffUL
1322 #define UVH_GR1_TLB_INT1_CONFIG_DM_MASK                 0x0000000000000700UL
1323 #define UVH_GR1_TLB_INT1_CONFIG_DESTMODE_MASK           0x0000000000000800UL
1324 #define UVH_GR1_TLB_INT1_CONFIG_STATUS_MASK             0x0000000000001000UL
1325 #define UVH_GR1_TLB_INT1_CONFIG_P_MASK                  0x0000000000002000UL
1326 #define UVH_GR1_TLB_INT1_CONFIG_T_MASK                  0x0000000000008000UL
1327 #define UVH_GR1_TLB_INT1_CONFIG_M_MASK                  0x0000000000010000UL
1328 #define UVH_GR1_TLB_INT1_CONFIG_APIC_ID_MASK            0xffffffff00000000UL
1329 
1330 
1331 union uvh_gr1_tlb_int1_config_u {
1332         unsigned long   v;
1333         struct uvh_gr1_tlb_int1_config_s {
1334                 unsigned long   vector_:8;                      /* RW */
1335                 unsigned long   dm:3;                           /* RW */
1336                 unsigned long   destmode:1;                     /* RW */
1337                 unsigned long   status:1;                       /* RO */
1338                 unsigned long   p:1;                            /* RO */
1339                 unsigned long   rsvd_14:1;
1340                 unsigned long   t:1;                            /* RO */
1341                 unsigned long   m:1;                            /* RW */
1342                 unsigned long   rsvd_17_31:15;
1343                 unsigned long   apic_id:32;                     /* RW */
1344         } s;
1345 };
1346 
1347 /* ========================================================================= */
1348 /*                         UVH_GR1_TLB_MMR_CONTROL                           */
1349 /* ========================================================================= */
1350 #define UV1H_GR1_TLB_MMR_CONTROL 0x801080UL
1351 #define UV2H_GR1_TLB_MMR_CONTROL 0x1001080UL
1352 #define UV3H_GR1_TLB_MMR_CONTROL 0x1001080UL
1353 #define UV4H_GR1_TLB_MMR_CONTROL 0x701080UL
1354 #define UVH_GR1_TLB_MMR_CONTROL (                                       \
1355         is_uv1_hub() ? UV1H_GR1_TLB_MMR_CONTROL :                       \
1356         is_uv2_hub() ? UV2H_GR1_TLB_MMR_CONTROL :                       \
1357         is_uv3_hub() ? UV3H_GR1_TLB_MMR_CONTROL :                       \
1358         /*is_uv4_hub*/ UV4H_GR1_TLB_MMR_CONTROL)
1359 
1360 #define UVH_GR1_TLB_MMR_CONTROL_INDEX_SHFT              0
1361 #define UVH_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT      16
1362 #define UVH_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT  20
1363 #define UVH_GR1_TLB_MMR_CONTROL_MMR_WRITE_SHFT          30
1364 #define UVH_GR1_TLB_MMR_CONTROL_MMR_READ_SHFT           31
1365 #define UVH_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK      0x0000000000010000UL
1366 #define UVH_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK  0x0000000000100000UL
1367 #define UVH_GR1_TLB_MMR_CONTROL_MMR_WRITE_MASK          0x0000000040000000UL
1368 #define UVH_GR1_TLB_MMR_CONTROL_MMR_READ_MASK           0x0000000080000000UL
1369 
1370 #define UV1H_GR1_TLB_MMR_CONTROL_INDEX_SHFT             0
1371 #define UV1H_GR1_TLB_MMR_CONTROL_MEM_SEL_SHFT           12
1372 #define UV1H_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT     16
1373 #define UV1H_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT 20
1374 #define UV1H_GR1_TLB_MMR_CONTROL_MMR_WRITE_SHFT         30
1375 #define UV1H_GR1_TLB_MMR_CONTROL_MMR_READ_SHFT          31
1376 #define UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_CON_SHFT       48
1377 #define UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBRAM_SHFT    52
1378 #define UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBPGSIZE_SHFT 54
1379 #define UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBRREG_SHFT   56
1380 #define UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBLRUV_SHFT   60
1381 #define UV1H_GR1_TLB_MMR_CONTROL_INDEX_MASK             0x0000000000000fffUL
1382 #define UV1H_GR1_TLB_MMR_CONTROL_MEM_SEL_MASK           0x0000000000003000UL
1383 #define UV1H_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK     0x0000000000010000UL
1384 #define UV1H_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK 0x0000000000100000UL
1385 #define UV1H_GR1_TLB_MMR_CONTROL_MMR_WRITE_MASK         0x0000000040000000UL
1386 #define UV1H_GR1_TLB_MMR_CONTROL_MMR_READ_MASK          0x0000000080000000UL
1387 #define UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_CON_MASK       0x0001000000000000UL
1388 #define UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBRAM_MASK    0x0010000000000000UL
1389 #define UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBPGSIZE_MASK 0x0040000000000000UL
1390 #define UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBRREG_MASK   0x0100000000000000UL
1391 #define UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBLRUV_MASK   0x1000000000000000UL
1392 
1393 #define UVXH_GR1_TLB_MMR_CONTROL_INDEX_SHFT             0
1394 #define UVXH_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT     16
1395 #define UVXH_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT 20
1396 #define UVXH_GR1_TLB_MMR_CONTROL_MMR_WRITE_SHFT         30
1397 #define UVXH_GR1_TLB_MMR_CONTROL_MMR_READ_SHFT          31
1398 #define UVXH_GR1_TLB_MMR_CONTROL_MMR_OP_DONE_SHFT       32
1399 #define UVXH_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK     0x0000000000010000UL
1400 #define UVXH_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK 0x0000000000100000UL
1401 #define UVXH_GR1_TLB_MMR_CONTROL_MMR_WRITE_MASK         0x0000000040000000UL
1402 #define UVXH_GR1_TLB_MMR_CONTROL_MMR_READ_MASK          0x0000000080000000UL
1403 #define UVXH_GR1_TLB_MMR_CONTROL_MMR_OP_DONE_MASK       0x0000000100000000UL
1404 
1405 #define UV2H_GR1_TLB_MMR_CONTROL_INDEX_SHFT             0
1406 #define UV2H_GR1_TLB_MMR_CONTROL_MEM_SEL_SHFT           12
1407 #define UV2H_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT     16
1408 #define UV2H_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT 20
1409 #define UV2H_GR1_TLB_MMR_CONTROL_MMR_WRITE_SHFT         30
1410 #define UV2H_GR1_TLB_MMR_CONTROL_MMR_READ_SHFT          31
1411 #define UV2H_GR1_TLB_MMR_CONTROL_MMR_OP_DONE_SHFT       32
1412 #define UV2H_GR1_TLB_MMR_CONTROL_MMR_INJ_CON_SHFT       48
1413 #define UV2H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBRAM_SHFT    52
1414 #define UV2H_GR1_TLB_MMR_CONTROL_INDEX_MASK             0x0000000000000fffUL
1415 #define UV2H_GR1_TLB_MMR_CONTROL_MEM_SEL_MASK           0x0000000000003000UL
1416 #define UV2H_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK     0x0000000000010000UL
1417 #define UV2H_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK 0x0000000000100000UL
1418 #define UV2H_GR1_TLB_MMR_CONTROL_MMR_WRITE_MASK         0x0000000040000000UL
1419 #define UV2H_GR1_TLB_MMR_CONTROL_MMR_READ_MASK          0x0000000080000000UL
1420 #define UV2H_GR1_TLB_MMR_CONTROL_MMR_OP_DONE_MASK       0x0000000100000000UL
1421 #define UV2H_GR1_TLB_MMR_CONTROL_MMR_INJ_CON_MASK       0x0001000000000000UL
1422 #define UV2H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBRAM_MASK    0x0010000000000000UL
1423 
1424 #define UV3H_GR1_TLB_MMR_CONTROL_INDEX_SHFT             0
1425 #define UV3H_GR1_TLB_MMR_CONTROL_MEM_SEL_SHFT           12
1426 #define UV3H_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT     16
1427 #define UV3H_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT 20
1428 #define UV3H_GR1_TLB_MMR_CONTROL_ECC_SEL_SHFT           21
1429 #define UV3H_GR1_TLB_MMR_CONTROL_MMR_WRITE_SHFT         30
1430 #define UV3H_GR1_TLB_MMR_CONTROL_MMR_READ_SHFT          31
1431 #define UV3H_GR1_TLB_MMR_CONTROL_MMR_OP_DONE_SHFT       32
1432 #define UV3H_GR1_TLB_MMR_CONTROL_INDEX_MASK             0x0000000000000fffUL
1433 #define UV3H_GR1_TLB_MMR_CONTROL_MEM_SEL_MASK           0x0000000000003000UL
1434 #define UV3H_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK     0x0000000000010000UL
1435 #define UV3H_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK 0x0000000000100000UL
1436 #define UV3H_GR1_TLB_MMR_CONTROL_ECC_SEL_MASK           0x0000000000200000UL
1437 #define UV3H_GR1_TLB_MMR_CONTROL_MMR_WRITE_MASK         0x0000000040000000UL
1438 #define UV3H_GR1_TLB_MMR_CONTROL_MMR_READ_MASK          0x0000000080000000UL
1439 #define UV3H_GR1_TLB_MMR_CONTROL_MMR_OP_DONE_MASK       0x0000000100000000UL
1440 
1441 #define UV4H_GR1_TLB_MMR_CONTROL_INDEX_SHFT             0
1442 #define UV4H_GR1_TLB_MMR_CONTROL_MEM_SEL_SHFT           13
1443 #define UV4H_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT     16
1444 #define UV4H_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT 20
1445 #define UV4H_GR1_TLB_MMR_CONTROL_ECC_SEL_SHFT           21
1446 #define UV4H_GR1_TLB_MMR_CONTROL_MMR_WRITE_SHFT         30
1447 #define UV4H_GR1_TLB_MMR_CONTROL_MMR_READ_SHFT          31
1448 #define UV4H_GR1_TLB_MMR_CONTROL_MMR_OP_DONE_SHFT       32
1449 #define UV4H_GR1_TLB_MMR_CONTROL_PAGE_SIZE_SHFT         59
1450 #define UV4H_GR1_TLB_MMR_CONTROL_INDEX_MASK             0x0000000000001fffUL
1451 #define UV4H_GR1_TLB_MMR_CONTROL_MEM_SEL_MASK           0x0000000000006000UL
1452 #define UV4H_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK     0x0000000000010000UL
1453 #define UV4H_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK 0x0000000000100000UL
1454 #define UV4H_GR1_TLB_MMR_CONTROL_ECC_SEL_MASK           0x0000000000200000UL
1455 #define UV4H_GR1_TLB_MMR_CONTROL_MMR_WRITE_MASK         0x0000000040000000UL
1456 #define UV4H_GR1_TLB_MMR_CONTROL_MMR_READ_MASK          0x0000000080000000UL
1457 #define UV4H_GR1_TLB_MMR_CONTROL_MMR_OP_DONE_MASK       0x0000000100000000UL
1458 #define UV4H_GR1_TLB_MMR_CONTROL_PAGE_SIZE_MASK         0xf800000000000000UL
1459 
1460 
1461 union uvh_gr1_tlb_mmr_control_u {
1462         unsigned long   v;
1463         struct uvh_gr1_tlb_mmr_control_s {
1464                 unsigned long   rsvd_0_15:16;
1465                 unsigned long   auto_valid_en:1;                /* RW */
1466                 unsigned long   rsvd_17_19:3;
1467                 unsigned long   mmr_hash_index_en:1;            /* RW */
1468                 unsigned long   rsvd_21_29:9;
1469                 unsigned long   mmr_write:1;                    /* WP */
1470                 unsigned long   mmr_read:1;                     /* WP */
1471                 unsigned long   rsvd_32_48:17;
1472                 unsigned long   rsvd_49_51:3;
1473                 unsigned long   rsvd_52_63:12;
1474         } s;
1475         struct uv1h_gr1_tlb_mmr_control_s {
1476                 unsigned long   index:12;                       /* RW */
1477                 unsigned long   mem_sel:2;                      /* RW */
1478                 unsigned long   rsvd_14_15:2;
1479                 unsigned long   auto_valid_en:1;                /* RW */
1480                 unsigned long   rsvd_17_19:3;
1481                 unsigned long   mmr_hash_index_en:1;            /* RW */
1482                 unsigned long   rsvd_21_29:9;
1483                 unsigned long   mmr_write:1;                    /* WP */
1484                 unsigned long   mmr_read:1;                     /* WP */
1485                 unsigned long   rsvd_32_47:16;
1486                 unsigned long   mmr_inj_con:1;                  /* RW */
1487                 unsigned long   rsvd_49_51:3;
1488                 unsigned long   mmr_inj_tlbram:1;               /* RW */
1489                 unsigned long   rsvd_53:1;
1490                 unsigned long   mmr_inj_tlbpgsize:1;            /* RW */
1491                 unsigned long   rsvd_55:1;
1492                 unsigned long   mmr_inj_tlbrreg:1;              /* RW */
1493                 unsigned long   rsvd_57_59:3;
1494                 unsigned long   mmr_inj_tlblruv:1;              /* RW */
1495                 unsigned long   rsvd_61_63:3;
1496         } s1;
1497         struct uvxh_gr1_tlb_mmr_control_s {
1498                 unsigned long   rsvd_0_15:16;
1499                 unsigned long   auto_valid_en:1;                /* RW */
1500                 unsigned long   rsvd_17_19:3;
1501                 unsigned long   mmr_hash_index_en:1;            /* RW */
1502                 unsigned long   rsvd_21_29:9;
1503                 unsigned long   mmr_write:1;                    /* WP */
1504                 unsigned long   mmr_read:1;                     /* WP */
1505                 unsigned long   mmr_op_done:1;                  /* RW */
1506                 unsigned long   rsvd_33_47:15;
1507                 unsigned long   rsvd_48:1;
1508                 unsigned long   rsvd_49_51:3;
1509                 unsigned long   rsvd_52_63:12;
1510         } sx;
1511         struct uv2h_gr1_tlb_mmr_control_s {
1512                 unsigned long   index:12;                       /* RW */
1513                 unsigned long   mem_sel:2;                      /* RW */
1514                 unsigned long   rsvd_14_15:2;
1515                 unsigned long   auto_valid_en:1;                /* RW */
1516                 unsigned long   rsvd_17_19:3;
1517                 unsigned long   mmr_hash_index_en:1;            /* RW */
1518                 unsigned long   rsvd_21_29:9;
1519                 unsigned long   mmr_write:1;                    /* WP */
1520                 unsigned long   mmr_read:1;                     /* WP */
1521                 unsigned long   mmr_op_done:1;                  /* RW */
1522                 unsigned long   rsvd_33_47:15;
1523                 unsigned long   mmr_inj_con:1;                  /* RW */
1524                 unsigned long   rsvd_49_51:3;
1525                 unsigned long   mmr_inj_tlbram:1;               /* RW */
1526                 unsigned long   rsvd_53_63:11;
1527         } s2;
1528         struct uv3h_gr1_tlb_mmr_control_s {
1529                 unsigned long   index:12;                       /* RW */
1530                 unsigned long   mem_sel:2;                      /* RW */
1531                 unsigned long   rsvd_14_15:2;
1532                 unsigned long   auto_valid_en:1;                /* RW */
1533                 unsigned long   rsvd_17_19:3;
1534                 unsigned long   mmr_hash_index_en:1;            /* RW */
1535                 unsigned long   ecc_sel:1;                      /* RW */
1536                 unsigned long   rsvd_22_29:8;
1537                 unsigned long   mmr_write:1;                    /* WP */
1538                 unsigned long   mmr_read:1;                     /* WP */
1539                 unsigned long   mmr_op_done:1;                  /* RW */
1540                 unsigned long   rsvd_33_47:15;
1541                 unsigned long   undef_48:1;                     /* Undefined */
1542                 unsigned long   rsvd_49_51:3;
1543                 unsigned long   undef_52:1;                     /* Undefined */
1544                 unsigned long   rsvd_53_63:11;
1545         } s3;
1546         struct uv4h_gr1_tlb_mmr_control_s {
1547                 unsigned long   index:13;                       /* RW */
1548                 unsigned long   mem_sel:2;                      /* RW */
1549                 unsigned long   rsvd_15:1;
1550                 unsigned long   auto_valid_en:1;                /* RW */
1551                 unsigned long   rsvd_17_19:3;
1552                 unsigned long   mmr_hash_index_en:1;            /* RW */
1553                 unsigned long   ecc_sel:1;                      /* RW */
1554                 unsigned long   rsvd_22_29:8;
1555                 unsigned long   mmr_write:1;                    /* WP */
1556                 unsigned long   mmr_read:1;                     /* WP */
1557                 unsigned long   mmr_op_done:1;                  /* RW */
1558                 unsigned long   rsvd_33_47:15;
1559                 unsigned long   undef_48:1;                     /* Undefined */
1560                 unsigned long   rsvd_49_51:3;
1561                 unsigned long   rsvd_52_58:7;
1562                 unsigned long   page_size:5;                    /* RW */
1563         } s4;
1564 };
1565 
1566 /* ========================================================================= */
1567 /*                       UVH_GR1_TLB_MMR_READ_DATA_HI                        */
1568 /* ========================================================================= */
1569 #define UV1H_GR1_TLB_MMR_READ_DATA_HI 0x8010a0UL
1570 #define UV2H_GR1_TLB_MMR_READ_DATA_HI 0x10010a0UL
1571 #define UV3H_GR1_TLB_MMR_READ_DATA_HI 0x10010a0UL
1572 #define UV4H_GR1_TLB_MMR_READ_DATA_HI 0x7010a0UL
1573 #define UVH_GR1_TLB_MMR_READ_DATA_HI (                                  \
1574         is_uv1_hub() ? UV1H_GR1_TLB_MMR_READ_DATA_HI :                  \
1575         is_uv2_hub() ? UV2H_GR1_TLB_MMR_READ_DATA_HI :                  \
1576         is_uv3_hub() ? UV3H_GR1_TLB_MMR_READ_DATA_HI :                  \
1577         /*is_uv4_hub*/ UV4H_GR1_TLB_MMR_READ_DATA_HI)
1578 
1579 #define UVH_GR1_TLB_MMR_READ_DATA_HI_PFN_SHFT           0
1580 
1581 #define UV1H_GR1_TLB_MMR_READ_DATA_HI_PFN_SHFT          0
1582 #define UV1H_GR1_TLB_MMR_READ_DATA_HI_GAA_SHFT          41
1583 #define UV1H_GR1_TLB_MMR_READ_DATA_HI_DIRTY_SHFT        43
1584 #define UV1H_GR1_TLB_MMR_READ_DATA_HI_LARGER_SHFT       44
1585 #define UV1H_GR1_TLB_MMR_READ_DATA_HI_PFN_MASK          0x000001ffffffffffUL
1586 #define UV1H_GR1_TLB_MMR_READ_DATA_HI_GAA_MASK          0x0000060000000000UL
1587 #define UV1H_GR1_TLB_MMR_READ_DATA_HI_DIRTY_MASK        0x0000080000000000UL
1588 #define UV1H_GR1_TLB_MMR_READ_DATA_HI_LARGER_MASK       0x0000100000000000UL
1589 
1590 #define UVXH_GR1_TLB_MMR_READ_DATA_HI_PFN_SHFT          0
1591 
1592 #define UV2H_GR1_TLB_MMR_READ_DATA_HI_PFN_SHFT          0
1593 #define UV2H_GR1_TLB_MMR_READ_DATA_HI_GAA_SHFT          41
1594 #define UV2H_GR1_TLB_MMR_READ_DATA_HI_DIRTY_SHFT        43
1595 #define UV2H_GR1_TLB_MMR_READ_DATA_HI_LARGER_SHFT       44
1596 #define UV2H_GR1_TLB_MMR_READ_DATA_HI_PFN_MASK          0x000001ffffffffffUL
1597 #define UV2H_GR1_TLB_MMR_READ_DATA_HI_GAA_MASK          0x0000060000000000UL
1598 #define UV2H_GR1_TLB_MMR_READ_DATA_HI_DIRTY_MASK        0x0000080000000000UL
1599 #define UV2H_GR1_TLB_MMR_READ_DATA_HI_LARGER_MASK       0x0000100000000000UL
1600 
1601 #define UV3H_GR1_TLB_MMR_READ_DATA_HI_PFN_SHFT          0
1602 #define UV3H_GR1_TLB_MMR_READ_DATA_HI_GAA_SHFT          41
1603 #define UV3H_GR1_TLB_MMR_READ_DATA_HI_DIRTY_SHFT        43
1604 #define UV3H_GR1_TLB_MMR_READ_DATA_HI_LARGER_SHFT       44
1605 #define UV3H_GR1_TLB_MMR_READ_DATA_HI_AA_EXT_SHFT       45
1606 #define UV3H_GR1_TLB_MMR_READ_DATA_HI_WAY_ECC_SHFT      55
1607 #define UV3H_GR1_TLB_MMR_READ_DATA_HI_PFN_MASK          0x000001ffffffffffUL
1608 #define UV3H_GR1_TLB_MMR_READ_DATA_HI_GAA_MASK          0x0000060000000000UL
1609 #define UV3H_GR1_TLB_MMR_READ_DATA_HI_DIRTY_MASK        0x0000080000000000UL
1610 #define UV3H_GR1_TLB_MMR_READ_DATA_HI_LARGER_MASK       0x0000100000000000UL
1611 #define UV3H_GR1_TLB_MMR_READ_DATA_HI_AA_EXT_MASK       0x0000200000000000UL
1612 #define UV3H_GR1_TLB_MMR_READ_DATA_HI_WAY_ECC_MASK      0xff80000000000000UL
1613 
1614 #define UV4H_GR1_TLB_MMR_READ_DATA_HI_PFN_SHFT          0
1615 #define UV4H_GR1_TLB_MMR_READ_DATA_HI_PNID_SHFT         34
1616 #define UV4H_GR1_TLB_MMR_READ_DATA_HI_GAA_SHFT          49
1617 #define UV4H_GR1_TLB_MMR_READ_DATA_HI_DIRTY_SHFT        51
1618 #define UV4H_GR1_TLB_MMR_READ_DATA_HI_LARGER_SHFT       52
1619 #define UV4H_GR1_TLB_MMR_READ_DATA_HI_AA_EXT_SHFT       53
1620 #define UV4H_GR1_TLB_MMR_READ_DATA_HI_WAY_ECC_SHFT      55
1621 #define UV4H_GR1_TLB_MMR_READ_DATA_HI_PFN_MASK          0x00000003ffffffffUL
1622 #define UV4H_GR1_TLB_MMR_READ_DATA_HI_PNID_MASK         0x0001fffc00000000UL
1623 #define UV4H_GR1_TLB_MMR_READ_DATA_HI_GAA_MASK          0x0006000000000000UL
1624 #define UV4H_GR1_TLB_MMR_READ_DATA_HI_DIRTY_MASK        0x0008000000000000UL
1625 #define UV4H_GR1_TLB_MMR_READ_DATA_HI_LARGER_MASK       0x0010000000000000UL
1626 #define UV4H_GR1_TLB_MMR_READ_DATA_HI_AA_EXT_MASK       0x0020000000000000UL
1627 #define UV4H_GR1_TLB_MMR_READ_DATA_HI_WAY_ECC_MASK      0xff80000000000000UL
1628 
1629 
1630 union uvh_gr1_tlb_mmr_read_data_hi_u {
1631         unsigned long   v;
1632         struct uv1h_gr1_tlb_mmr_read_data_hi_s {
1633                 unsigned long   pfn:41;                         /* RO */
1634                 unsigned long   gaa:2;                          /* RO */
1635                 unsigned long   dirty:1;                        /* RO */
1636                 unsigned long   larger:1;                       /* RO */
1637                 unsigned long   rsvd_45_63:19;
1638         } s1;
1639         struct uv2h_gr1_tlb_mmr_read_data_hi_s {
1640                 unsigned long   pfn:41;                         /* RO */
1641                 unsigned long   gaa:2;                          /* RO */
1642                 unsigned long   dirty:1;                        /* RO */
1643                 unsigned long   larger:1;                       /* RO */
1644                 unsigned long   rsvd_45_63:19;
1645         } s2;
1646         struct uv3h_gr1_tlb_mmr_read_data_hi_s {
1647                 unsigned long   pfn:41;                         /* RO */
1648                 unsigned long   gaa:2;                          /* RO */
1649                 unsigned long   dirty:1;                        /* RO */
1650                 unsigned long   larger:1;                       /* RO */
1651                 unsigned long   aa_ext:1;                       /* RO */
1652                 unsigned long   undef_46_54:9;                  /* Undefined */
1653                 unsigned long   way_ecc:9;                      /* RO */
1654         } s3;
1655         struct uv4h_gr1_tlb_mmr_read_data_hi_s {
1656                 unsigned long   pfn:34;                         /* RO */
1657                 unsigned long   pnid:15;                        /* RO */
1658                 unsigned long   gaa:2;                          /* RO */
1659                 unsigned long   dirty:1;                        /* RO */
1660                 unsigned long   larger:1;                       /* RO */
1661                 unsigned long   aa_ext:1;                       /* RO */
1662                 unsigned long   undef_54:1;                     /* Undefined */
1663                 unsigned long   way_ecc:9;                      /* RO */
1664         } s4;
1665 };
1666 
1667 /* ========================================================================= */
1668 /*                       UVH_GR1_TLB_MMR_READ_DATA_LO                        */
1669 /* ========================================================================= */
1670 #define UV1H_GR1_TLB_MMR_READ_DATA_LO 0x8010a8UL
1671 #define UV2H_GR1_TLB_MMR_READ_DATA_LO 0x10010a8UL
1672 #define UV3H_GR1_TLB_MMR_READ_DATA_LO 0x10010a8UL
1673 #define UV4H_GR1_TLB_MMR_READ_DATA_LO 0x7010a8UL
1674 #define UVH_GR1_TLB_MMR_READ_DATA_LO (                                  \
1675         is_uv1_hub() ? UV1H_GR1_TLB_MMR_READ_DATA_LO :                  \
1676         is_uv2_hub() ? UV2H_GR1_TLB_MMR_READ_DATA_LO :                  \
1677         is_uv3_hub() ? UV3H_GR1_TLB_MMR_READ_DATA_LO :                  \
1678         /*is_uv4_hub*/ UV4H_GR1_TLB_MMR_READ_DATA_LO)
1679 
1680 #define UVH_GR1_TLB_MMR_READ_DATA_LO_VPN_SHFT           0
1681 #define UVH_GR1_TLB_MMR_READ_DATA_LO_ASID_SHFT          39
1682 #define UVH_GR1_TLB_MMR_READ_DATA_LO_VALID_SHFT         63
1683 #define UVH_GR1_TLB_MMR_READ_DATA_LO_VPN_MASK           0x0000007fffffffffUL
1684 #define UVH_GR1_TLB_MMR_READ_DATA_LO_ASID_MASK          0x7fffff8000000000UL
1685 #define UVH_GR1_TLB_MMR_READ_DATA_LO_VALID_MASK         0x8000000000000000UL
1686 
1687 #define UV1H_GR1_TLB_MMR_READ_DATA_LO_VPN_SHFT          0
1688 #define UV1H_GR1_TLB_MMR_READ_DATA_LO_ASID_SHFT         39
1689 #define UV1H_GR1_TLB_MMR_READ_DATA_LO_VALID_SHFT        63
1690 #define UV1H_GR1_TLB_MMR_READ_DATA_LO_VPN_MASK          0x0000007fffffffffUL
1691 #define UV1H_GR1_TLB_MMR_READ_DATA_LO_ASID_MASK         0x7fffff8000000000UL
1692 #define UV1H_GR1_TLB_MMR_READ_DATA_LO_VALID_MASK        0x8000000000000000UL
1693 
1694 #define UVXH_GR1_TLB_MMR_READ_DATA_LO_VPN_SHFT          0
1695 #define UVXH_GR1_TLB_MMR_READ_DATA_LO_ASID_SHFT         39
1696 #define UVXH_GR1_TLB_MMR_READ_DATA_LO_VALID_SHFT        63
1697 #define UVXH_GR1_TLB_MMR_READ_DATA_LO_VPN_MASK          0x0000007fffffffffUL
1698 #define UVXH_GR1_TLB_MMR_READ_DATA_LO_ASID_MASK         0x7fffff8000000000UL
1699 #define UVXH_GR1_TLB_MMR_READ_DATA_LO_VALID_MASK        0x8000000000000000UL
1700 
1701 #define UV2H_GR1_TLB_MMR_READ_DATA_LO_VPN_SHFT          0
1702 #define UV2H_GR1_TLB_MMR_READ_DATA_LO_ASID_SHFT         39
1703 #define UV2H_GR1_TLB_MMR_READ_DATA_LO_VALID_SHFT        63
1704 #define UV2H_GR1_TLB_MMR_READ_DATA_LO_VPN_MASK          0x0000007fffffffffUL
1705 #define UV2H_GR1_TLB_MMR_READ_DATA_LO_ASID_MASK         0x7fffff8000000000UL
1706 #define UV2H_GR1_TLB_MMR_READ_DATA_LO_VALID_MASK        0x8000000000000000UL
1707 
1708 #define UV3H_GR1_TLB_MMR_READ_DATA_LO_VPN_SHFT          0
1709 #define UV3H_GR1_TLB_MMR_READ_DATA_LO_ASID_SHFT         39
1710 #define UV3H_GR1_TLB_MMR_READ_DATA_LO_VALID_SHFT        63
1711 #define UV3H_GR1_TLB_MMR_READ_DATA_LO_VPN_MASK          0x0000007fffffffffUL
1712 #define UV3H_GR1_TLB_MMR_READ_DATA_LO_ASID_MASK         0x7fffff8000000000UL
1713 #define UV3H_GR1_TLB_MMR_READ_DATA_LO_VALID_MASK        0x8000000000000000UL
1714 
1715 #define UV4H_GR1_TLB_MMR_READ_DATA_LO_VPN_SHFT          0
1716 #define UV4H_GR1_TLB_MMR_READ_DATA_LO_ASID_SHFT         39
1717 #define UV4H_GR1_TLB_MMR_READ_DATA_LO_VALID_SHFT        63
1718 #define UV4H_GR1_TLB_MMR_READ_DATA_LO_VPN_MASK          0x0000007fffffffffUL
1719 #define UV4H_GR1_TLB_MMR_READ_DATA_LO_ASID_MASK         0x7fffff8000000000UL
1720 #define UV4H_GR1_TLB_MMR_READ_DATA_LO_VALID_MASK        0x8000000000000000UL
1721 
1722 
1723 union uvh_gr1_tlb_mmr_read_data_lo_u {
1724         unsigned long   v;
1725         struct uvh_gr1_tlb_mmr_read_data_lo_s {
1726                 unsigned long   vpn:39;                         /* RO */
1727                 unsigned long   asid:24;                        /* RO */
1728                 unsigned long   valid:1;                        /* RO */
1729         } s;
1730         struct uv1h_gr1_tlb_mmr_read_data_lo_s {
1731                 unsigned long   vpn:39;                         /* RO */
1732                 unsigned long   asid:24;                        /* RO */
1733                 unsigned long   valid:1;                        /* RO */
1734         } s1;
1735         struct uvxh_gr1_tlb_mmr_read_data_lo_s {
1736                 unsigned long   vpn:39;                         /* RO */
1737                 unsigned long   asid:24;                        /* RO */
1738                 unsigned long   valid:1;                        /* RO */
1739         } sx;
1740         struct uv2h_gr1_tlb_mmr_read_data_lo_s {
1741                 unsigned long   vpn:39;                         /* RO */
1742                 unsigned long   asid:24;                        /* RO */
1743                 unsigned long   valid:1;                        /* RO */
1744         } s2;
1745         struct uv3h_gr1_tlb_mmr_read_data_lo_s {
1746                 unsigned long   vpn:39;                         /* RO */
1747                 unsigned long   asid:24;                        /* RO */
1748                 unsigned long   valid:1;                        /* RO */
1749         } s3;
1750         struct uv4h_gr1_tlb_mmr_read_data_lo_s {
1751                 unsigned long   vpn:39;                         /* RO */
1752                 unsigned long   asid:24;                        /* RO */
1753                 unsigned long   valid:1;                        /* RO */
1754         } s4;
1755 };
1756 
1757 /* ========================================================================= */
1758 /*                               UVH_INT_CMPB                                */
1759 /* ========================================================================= */
1760 #define UVH_INT_CMPB 0x22080UL
1761 
1762 #define UVH_INT_CMPB_REAL_TIME_CMPB_SHFT                0
1763 #define UVH_INT_CMPB_REAL_TIME_CMPB_MASK                0x00ffffffffffffffUL
1764 
1765 
1766 union uvh_int_cmpb_u {
1767         unsigned long   v;
1768         struct uvh_int_cmpb_s {
1769                 unsigned long   real_time_cmpb:56;              /* RW */
1770                 unsigned long   rsvd_56_63:8;
1771         } s;
1772 };
1773 
1774 /* ========================================================================= */
1775 /*                               UVH_INT_CMPC                                */
1776 /* ========================================================================= */
1777 #define UVH_INT_CMPC 0x22100UL
1778 
1779 
1780 #define UV1H_INT_CMPC_REAL_TIME_CMPC_SHFT               0
1781 #define UV1H_INT_CMPC_REAL_TIME_CMPC_MASK               0x00ffffffffffffffUL
1782 
1783 #define UVXH_INT_CMPC_REAL_TIME_CMP_2_SHFT              0
1784 #define UVXH_INT_CMPC_REAL_TIME_CMP_2_MASK              0x00ffffffffffffffUL
1785 
1786 
1787 union uvh_int_cmpc_u {
1788         unsigned long   v;
1789         struct uvh_int_cmpc_s {
1790                 unsigned long   real_time_cmpc:56;              /* RW */
1791                 unsigned long   rsvd_56_63:8;
1792         } s;
1793 };
1794 
1795 /* ========================================================================= */
1796 /*                               UVH_INT_CMPD                                */
1797 /* ========================================================================= */
1798 #define UVH_INT_CMPD 0x22180UL
1799 
1800 
1801 #define UV1H_INT_CMPD_REAL_TIME_CMPD_SHFT               0
1802 #define UV1H_INT_CMPD_REAL_TIME_CMPD_MASK               0x00ffffffffffffffUL
1803 
1804 #define UVXH_INT_CMPD_REAL_TIME_CMP_3_SHFT              0
1805 #define UVXH_INT_CMPD_REAL_TIME_CMP_3_MASK              0x00ffffffffffffffUL
1806 
1807 
1808 union uvh_int_cmpd_u {
1809         unsigned long   v;
1810         struct uvh_int_cmpd_s {
1811                 unsigned long   real_time_cmpd:56;              /* RW */
1812                 unsigned long   rsvd_56_63:8;
1813         } s;
1814 };
1815 
1816 /* ========================================================================= */
1817 /*                               UVH_IPI_INT                                 */
1818 /* ========================================================================= */
1819 #define UVH_IPI_INT 0x60500UL
1820 
1821 #define UV1H_IPI_INT_32 0x348
1822 #define UV2H_IPI_INT_32 0x348
1823 #define UV3H_IPI_INT_32 0x348
1824 #define UV4H_IPI_INT_32 0x268
1825 #define UVH_IPI_INT_32 (                                                \
1826         is_uv1_hub() ? UV1H_IPI_INT_32 :                                \
1827         is_uv2_hub() ? UV2H_IPI_INT_32 :                                \
1828         is_uv3_hub() ? UV3H_IPI_INT_32 :                                \
1829         /*is_uv4_hub*/ UV4H_IPI_INT_32)
1830 
1831 #define UVH_IPI_INT_VECTOR_SHFT                         0
1832 #define UVH_IPI_INT_DELIVERY_MODE_SHFT                  8
1833 #define UVH_IPI_INT_DESTMODE_SHFT                       11
1834 #define UVH_IPI_INT_APIC_ID_SHFT                        16
1835 #define UVH_IPI_INT_SEND_SHFT                           63
1836 #define UVH_IPI_INT_VECTOR_MASK                         0x00000000000000ffUL
1837 #define UVH_IPI_INT_DELIVERY_MODE_MASK                  0x0000000000000700UL
1838 #define UVH_IPI_INT_DESTMODE_MASK                       0x0000000000000800UL
1839 #define UVH_IPI_INT_APIC_ID_MASK                        0x0000ffffffff0000UL
1840 #define UVH_IPI_INT_SEND_MASK                           0x8000000000000000UL
1841 
1842 
1843 union uvh_ipi_int_u {
1844         unsigned long   v;
1845         struct uvh_ipi_int_s {
1846                 unsigned long   vector_:8;                      /* RW */
1847                 unsigned long   delivery_mode:3;                /* RW */
1848                 unsigned long   destmode:1;                     /* RW */
1849                 unsigned long   rsvd_12_15:4;
1850                 unsigned long   apic_id:32;                     /* RW */
1851                 unsigned long   rsvd_48_62:15;
1852                 unsigned long   send:1;                         /* WP */
1853         } s;
1854 };
1855 
1856 /* ========================================================================= */
1857 /*                   UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST                     */
1858 /* ========================================================================= */
1859 #define UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST 0x320050UL
1860 #define UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST 0x320050UL
1861 #define UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST 0x320050UL
1862 #define UV4H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST uv_undefined("UV4H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST")
1863 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST (                           \
1864         is_uv1_hub() ? UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST :           \
1865         is_uv2_hub() ? UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST :           \
1866         is_uv3_hub() ? UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST :           \
1867         /*is_uv4_hub*/ UV4H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST)
1868 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_32 0x9c0
1869 
1870 
1871 #define UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_SHFT 4
1872 #define UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_NODE_ID_SHFT 49
1873 #define UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_MASK 0x000007fffffffff0UL
1874 #define UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_NODE_ID_MASK 0x7ffe000000000000UL
1875 
1876 
1877 #define UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_SHFT 4
1878 #define UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_NODE_ID_SHFT 49
1879 #define UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_MASK 0x000007fffffffff0UL
1880 #define UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_NODE_ID_MASK 0x7ffe000000000000UL
1881 
1882 #define UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_SHFT 4
1883 #define UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_NODE_ID_SHFT 49
1884 #define UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_MASK 0x000007fffffffff0UL
1885 #define UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_NODE_ID_MASK 0x7ffe000000000000UL
1886 
1887 
1888 union uvh_lb_bau_intd_payload_queue_first_u {
1889         unsigned long   v;
1890         struct uv1h_lb_bau_intd_payload_queue_first_s {
1891                 unsigned long   rsvd_0_3:4;
1892                 unsigned long   address:39;                     /* RW */
1893                 unsigned long   rsvd_43_48:6;
1894                 unsigned long   node_id:14;                     /* RW */
1895                 unsigned long   rsvd_63:1;
1896         } s1;
1897         struct uv2h_lb_bau_intd_payload_queue_first_s {
1898                 unsigned long   rsvd_0_3:4;
1899                 unsigned long   address:39;                     /* RW */
1900                 unsigned long   rsvd_43_48:6;
1901                 unsigned long   node_id:14;                     /* RW */
1902                 unsigned long   rsvd_63:1;
1903         } s2;
1904         struct uv3h_lb_bau_intd_payload_queue_first_s {
1905                 unsigned long   rsvd_0_3:4;
1906                 unsigned long   address:39;                     /* RW */
1907                 unsigned long   rsvd_43_48:6;
1908                 unsigned long   node_id:14;                     /* RW */
1909                 unsigned long   rsvd_63:1;
1910         } s3;
1911 };
1912 
1913 /* ========================================================================= */
1914 /*                    UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST                     */
1915 /* ========================================================================= */
1916 #define UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST 0x320060UL
1917 #define UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST 0x320060UL
1918 #define UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST 0x320060UL
1919 #define UV4H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST uv_undefined("UV4H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST")
1920 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST (                            \
1921         is_uv1_hub() ? UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST :            \
1922         is_uv2_hub() ? UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST :            \
1923         is_uv3_hub() ? UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST :            \
1924         /*is_uv4_hub*/ UV4H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST)
1925 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_32 0x9c8
1926 
1927 
1928 #define UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_SHFT 4
1929 #define UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_MASK 0x000007fffffffff0UL
1930 
1931 
1932 #define UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_SHFT 4
1933 #define UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_MASK 0x000007fffffffff0UL
1934 
1935 #define UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_SHFT 4
1936 #define UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_MASK 0x000007fffffffff0UL
1937 
1938 
1939 union uvh_lb_bau_intd_payload_queue_last_u {
1940         unsigned long   v;
1941         struct uv1h_lb_bau_intd_payload_queue_last_s {
1942                 unsigned long   rsvd_0_3:4;
1943                 unsigned long   address:39;                     /* RW */
1944                 unsigned long   rsvd_43_63:21;
1945         } s1;
1946         struct uv2h_lb_bau_intd_payload_queue_last_s {
1947                 unsigned long   rsvd_0_3:4;
1948                 unsigned long   address:39;                     /* RW */
1949                 unsigned long   rsvd_43_63:21;
1950         } s2;
1951         struct uv3h_lb_bau_intd_payload_queue_last_s {
1952                 unsigned long   rsvd_0_3:4;
1953                 unsigned long   address:39;                     /* RW */
1954                 unsigned long   rsvd_43_63:21;
1955         } s3;
1956 };
1957 
1958 /* ========================================================================= */
1959 /*                    UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL                     */
1960 /* ========================================================================= */
1961 #define UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL 0x320070UL
1962 #define UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL 0x320070UL
1963 #define UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL 0x320070UL
1964 #define UV4H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL uv_undefined("UV4H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL")
1965 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL (                            \
1966         is_uv1_hub() ? UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL :            \
1967         is_uv2_hub() ? UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL :            \
1968         is_uv3_hub() ? UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL :            \
1969         /*is_uv4_hub*/ UV4H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL)
1970 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_32 0x9d0
1971 
1972 
1973 #define UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_SHFT 4
1974 #define UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_MASK 0x000007fffffffff0UL
1975 
1976 
1977 #define UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_SHFT 4
1978 #define UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_MASK 0x000007fffffffff0UL
1979 
1980 #define UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_SHFT 4
1981 #define UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_MASK 0x000007fffffffff0UL
1982 
1983 
1984 union uvh_lb_bau_intd_payload_queue_tail_u {
1985         unsigned long   v;
1986         struct uv1h_lb_bau_intd_payload_queue_tail_s {
1987                 unsigned long   rsvd_0_3:4;
1988                 unsigned long   address:39;                     /* RW */
1989                 unsigned long   rsvd_43_63:21;
1990         } s1;
1991         struct uv2h_lb_bau_intd_payload_queue_tail_s {
1992                 unsigned long   rsvd_0_3:4;
1993                 unsigned long   address:39;                     /* RW */
1994                 unsigned long   rsvd_43_63:21;
1995         } s2;
1996         struct uv3h_lb_bau_intd_payload_queue_tail_s {
1997                 unsigned long   rsvd_0_3:4;
1998                 unsigned long   address:39;                     /* RW */
1999                 unsigned long   rsvd_43_63:21;
2000         } s3;
2001 };
2002 
2003 /* ========================================================================= */
2004 /*                   UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE                    */
2005 /* ========================================================================= */
2006 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE 0x320080UL
2007 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE 0x320080UL
2008 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE 0x320080UL
2009 #define UV4H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE uv_undefined("UV4H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE")
2010 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE (                          \
2011         is_uv1_hub() ? UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE :          \
2012         is_uv2_hub() ? UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE :          \
2013         is_uv3_hub() ? UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE :          \
2014         /*is_uv4_hub*/ UV4H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE)
2015 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_32 0xa68
2016 
2017 
2018 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_SHFT 0
2019 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_1_SHFT 1
2020 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_2_SHFT 2
2021 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_3_SHFT 3
2022 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_4_SHFT 4
2023 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_5_SHFT 5
2024 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_6_SHFT 6
2025 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_7_SHFT 7
2026 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_0_SHFT 8
2027 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_1_SHFT 9
2028 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_2_SHFT 10
2029 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_3_SHFT 11
2030 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_4_SHFT 12
2031 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_5_SHFT 13
2032 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_6_SHFT 14
2033 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_7_SHFT 15
2034 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_MASK 0x0000000000000001UL
2035 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_1_MASK 0x0000000000000002UL
2036 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_2_MASK 0x0000000000000004UL
2037 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_3_MASK 0x0000000000000008UL
2038 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_4_MASK 0x0000000000000010UL
2039 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_5_MASK 0x0000000000000020UL
2040 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_6_MASK 0x0000000000000040UL
2041 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_7_MASK 0x0000000000000080UL
2042 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_0_MASK 0x0000000000000100UL
2043 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_1_MASK 0x0000000000000200UL
2044 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_2_MASK 0x0000000000000400UL
2045 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_3_MASK 0x0000000000000800UL
2046 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_4_MASK 0x0000000000001000UL
2047 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_5_MASK 0x0000000000002000UL
2048 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_6_MASK 0x0000000000004000UL
2049 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_7_MASK 0x0000000000008000UL
2050 
2051 
2052 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_SHFT 0
2053 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_1_SHFT 1
2054 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_2_SHFT 2
2055 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_3_SHFT 3
2056 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_4_SHFT 4
2057 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_5_SHFT 5
2058 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_6_SHFT 6
2059 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_7_SHFT 7
2060 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_0_SHFT 8
2061 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_1_SHFT 9
2062 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_2_SHFT 10
2063 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_3_SHFT 11
2064 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_4_SHFT 12
2065 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_5_SHFT 13
2066 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_6_SHFT 14
2067 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_7_SHFT 15
2068 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_MASK 0x0000000000000001UL
2069 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_1_MASK 0x0000000000000002UL
2070 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_2_MASK 0x0000000000000004UL
2071 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_3_MASK 0x0000000000000008UL
2072 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_4_MASK 0x0000000000000010UL
2073 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_5_MASK 0x0000000000000020UL
2074 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_6_MASK 0x0000000000000040UL
2075 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_7_MASK 0x0000000000000080UL
2076 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_0_MASK 0x0000000000000100UL
2077 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_1_MASK 0x0000000000000200UL
2078 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_2_MASK 0x0000000000000400UL
2079 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_3_MASK 0x0000000000000800UL
2080 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_4_MASK 0x0000000000001000UL
2081 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_5_MASK 0x0000000000002000UL
2082 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_6_MASK 0x0000000000004000UL
2083 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_7_MASK 0x0000000000008000UL
2084 
2085 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_SHFT 0
2086 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_1_SHFT 1
2087 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_2_SHFT 2
2088 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_3_SHFT 3
2089 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_4_SHFT 4
2090 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_5_SHFT 5
2091 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_6_SHFT 6
2092 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_7_SHFT 7
2093 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_0_SHFT 8
2094 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_1_SHFT 9
2095 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_2_SHFT 10
2096 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_3_SHFT 11
2097 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_4_SHFT 12
2098 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_5_SHFT 13
2099 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_6_SHFT 14
2100 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_7_SHFT 15
2101 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_MASK 0x0000000000000001UL
2102 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_1_MASK 0x0000000000000002UL
2103 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_2_MASK 0x0000000000000004UL
2104 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_3_MASK 0x0000000000000008UL
2105 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_4_MASK 0x0000000000000010UL
2106 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_5_MASK 0x0000000000000020UL
2107 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_6_MASK 0x0000000000000040UL
2108 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_7_MASK 0x0000000000000080UL
2109 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_0_MASK 0x0000000000000100UL
2110 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_1_MASK 0x0000000000000200UL
2111 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_2_MASK 0x0000000000000400UL
2112 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_3_MASK 0x0000000000000800UL
2113 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_4_MASK 0x0000000000001000UL
2114 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_5_MASK 0x0000000000002000UL
2115 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_6_MASK 0x0000000000004000UL
2116 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_7_MASK 0x0000000000008000UL
2117 
2118 
2119 union uvh_lb_bau_intd_software_acknowledge_u {
2120         unsigned long   v;
2121         struct uv1h_lb_bau_intd_software_acknowledge_s {
2122                 unsigned long   pending_0:1;                    /* RW, W1C */
2123                 unsigned long   pending_1:1;                    /* RW, W1C */
2124                 unsigned long   pending_2:1;                    /* RW, W1C */
2125                 unsigned long   pending_3:1;                    /* RW, W1C */
2126                 unsigned long   pending_4:1;                    /* RW, W1C */
2127                 unsigned long   pending_5:1;                    /* RW, W1C */
2128                 unsigned long   pending_6:1;                    /* RW, W1C */
2129                 unsigned long   pending_7:1;                    /* RW, W1C */
2130                 unsigned long   timeout_0:1;                    /* RW, W1C */
2131                 unsigned long   timeout_1:1;                    /* RW, W1C */
2132                 unsigned long   timeout_2:1;                    /* RW, W1C */
2133                 unsigned long   timeout_3:1;                    /* RW, W1C */
2134                 unsigned long   timeout_4:1;                    /* RW, W1C */
2135                 unsigned long   timeout_5:1;                    /* RW, W1C */
2136                 unsigned long   timeout_6:1;                    /* RW, W1C */
2137                 unsigned long   timeout_7:1;                    /* RW, W1C */
2138                 unsigned long   rsvd_16_63:48;
2139         } s1;
2140         struct uv2h_lb_bau_intd_software_acknowledge_s {
2141                 unsigned long   pending_0:1;                    /* RW */
2142                 unsigned long   pending_1:1;                    /* RW */
2143                 unsigned long   pending_2:1;                    /* RW */
2144                 unsigned long   pending_3:1;                    /* RW */
2145                 unsigned long   pending_4:1;                    /* RW */
2146                 unsigned long   pending_5:1;                    /* RW */
2147                 unsigned long   pending_6:1;                    /* RW */
2148                 unsigned long   pending_7:1;                    /* RW */
2149                 unsigned long   timeout_0:1;                    /* RW */
2150                 unsigned long   timeout_1:1;                    /* RW */
2151                 unsigned long   timeout_2:1;                    /* RW */
2152                 unsigned long   timeout_3:1;                    /* RW */
2153                 unsigned long   timeout_4:1;                    /* RW */
2154                 unsigned long   timeout_5:1;                    /* RW */
2155                 unsigned long   timeout_6:1;                    /* RW */
2156                 unsigned long   timeout_7:1;                    /* RW */
2157                 unsigned long   rsvd_16_63:48;
2158         } s2;
2159         struct uv3h_lb_bau_intd_software_acknowledge_s {
2160                 unsigned long   pending_0:1;                    /* RW */
2161                 unsigned long   pending_1:1;                    /* RW */
2162                 unsigned long   pending_2:1;                    /* RW */
2163                 unsigned long   pending_3:1;                    /* RW */
2164                 unsigned long   pending_4:1;                    /* RW */
2165                 unsigned long   pending_5:1;                    /* RW */
2166                 unsigned long   pending_6:1;                    /* RW */
2167                 unsigned long   pending_7:1;                    /* RW */
2168                 unsigned long   timeout_0:1;                    /* RW */
2169                 unsigned long   timeout_1:1;                    /* RW */
2170                 unsigned long   timeout_2:1;                    /* RW */
2171                 unsigned long   timeout_3:1;                    /* RW */
2172                 unsigned long   timeout_4:1;                    /* RW */
2173                 unsigned long   timeout_5:1;                    /* RW */
2174                 unsigned long   timeout_6:1;                    /* RW */
2175                 unsigned long   timeout_7:1;                    /* RW */
2176                 unsigned long   rsvd_16_63:48;
2177         } s3;
2178 };
2179 
2180 /* ========================================================================= */
2181 /*                UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS                 */
2182 /* ========================================================================= */
2183 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS 0x320088UL
2184 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS 0x320088UL
2185 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS 0x320088UL
2186 #define UV4H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS uv_undefined("UV4H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS")
2187 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS (                    \
2188         is_uv1_hub() ? UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS :    \
2189         is_uv2_hub() ? UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS :    \
2190         is_uv3_hub() ? UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS :    \
2191         /*is_uv4_hub*/ UV4H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS)
2192 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS_32 0xa70
2193 
2194 
2195 /* ========================================================================= */
2196 /*                         UVH_LB_BAU_MISC_CONTROL                           */
2197 /* ========================================================================= */
2198 #define UV1H_LB_BAU_MISC_CONTROL 0x320170UL
2199 #define UV2H_LB_BAU_MISC_CONTROL 0x320170UL
2200 #define UV3H_LB_BAU_MISC_CONTROL 0x320170UL
2201 #define UV4H_LB_BAU_MISC_CONTROL 0xc8170UL
2202 #define UVH_LB_BAU_MISC_CONTROL (                                       \
2203         is_uv1_hub() ? UV1H_LB_BAU_MISC_CONTROL :                       \
2204         is_uv2_hub() ? UV2H_LB_BAU_MISC_CONTROL :                       \
2205         is_uv3_hub() ? UV3H_LB_BAU_MISC_CONTROL :                       \
2206         /*is_uv4_hub*/ UV4H_LB_BAU_MISC_CONTROL)
2207 
2208 #define UV1H_LB_BAU_MISC_CONTROL_32 0xa10
2209 #define UV2H_LB_BAU_MISC_CONTROL_32 0xa10
2210 #define UV3H_LB_BAU_MISC_CONTROL_32 0xa10
2211 #define UV4H_LB_BAU_MISC_CONTROL_32 0xa18
2212 #define UVH_LB_BAU_MISC_CONTROL_32 (                                    \
2213         is_uv1_hub() ? UV1H_LB_BAU_MISC_CONTROL_32 :                    \
2214         is_uv2_hub() ? UV2H_LB_BAU_MISC_CONTROL_32 :                    \
2215         is_uv3_hub() ? UV3H_LB_BAU_MISC_CONTROL_32 :                    \
2216         /*is_uv4_hub*/ UV4H_LB_BAU_MISC_CONTROL_32)
2217 
2218 #define UVH_LB_BAU_MISC_CONTROL_REJECTION_DELAY_SHFT    0
2219 #define UVH_LB_BAU_MISC_CONTROL_APIC_MODE_SHFT          8
2220 #define UVH_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_SHFT    9
2221 #define UVH_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_SHFT     10
2222 #define UVH_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_SHFT 11
2223 #define UVH_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_SHFT 14
2224 #define UVH_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_SHFT 20
2225 #define UVH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_SHFT 21
2226 #define UVH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_SHFT 22
2227 #define UVH_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_SHFT 23
2228 #define UVH_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_SHFT 24
2229 #define UVH_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_SHFT 27
2230 #define UVH_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_SHFT 28
2231 #define UVH_LB_BAU_MISC_CONTROL_FUN_SHFT                48
2232 #define UVH_LB_BAU_MISC_CONTROL_REJECTION_DELAY_MASK    0x00000000000000ffUL
2233 #define UVH_LB_BAU_MISC_CONTROL_APIC_MODE_MASK          0x0000000000000100UL
2234 #define UVH_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_MASK    0x0000000000000200UL
2235 #define UVH_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_MASK     0x0000000000000400UL
2236 #define UVH_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_MASK 0x0000000000003800UL
2237 #define UVH_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_MASK 0x0000000000004000UL
2238 #define UVH_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_MASK 0x0000000000100000UL
2239 #define UVH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_MASK 0x0000000000200000UL
2240 #define UVH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_MASK 0x0000000000400000UL
2241 #define UVH_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_MASK 0x0000000000800000UL
2242 #define UVH_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000007000000UL
2243 #define UVH_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_MASK 0x0000000008000000UL
2244 #define UVH_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000010000000UL
2245 #define UVH_LB_BAU_MISC_CONTROL_FUN_MASK                0xffff000000000000UL
2246 
2247 #define UV1H_LB_BAU_MISC_CONTROL_REJECTION_DELAY_SHFT   0
2248 #define UV1H_LB_BAU_MISC_CONTROL_APIC_MODE_SHFT         8
2249 #define UV1H_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_SHFT   9
2250 #define UV1H_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_SHFT    10
2251 #define UV1H_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_SHFT 11
2252 #define UV1H_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_SHFT 14
2253 #define UV1H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT 15
2254 #define UV1H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT 16
2255 #define UV1H_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_SHFT 20
2256 #define UV1H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_SHFT 21
2257 #define UV1H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_SHFT 22
2258 #define UV1H_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_SHFT 23
2259 #define UV1H_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_SHFT 24
2260 #define UV1H_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_SHFT 27
2261 #define UV1H_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_SHFT 28
2262 #define UV1H_LB_BAU_MISC_CONTROL_FUN_SHFT               48
2263 #define UV1H_LB_BAU_MISC_CONTROL_REJECTION_DELAY_MASK   0x00000000000000ffUL
2264 #define UV1H_LB_BAU_MISC_CONTROL_APIC_MODE_MASK         0x0000000000000100UL
2265 #define UV1H_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_MASK   0x0000000000000200UL
2266 #define UV1H_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_MASK    0x0000000000000400UL
2267 #define UV1H_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_MASK 0x0000000000003800UL
2268 #define UV1H_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_MASK 0x0000000000004000UL
2269 #define UV1H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_MASK 0x0000000000008000UL
2270 #define UV1H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK 0x00000000000f0000UL
2271 #define UV1H_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_MASK 0x0000000000100000UL
2272 #define UV1H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_MASK 0x0000000000200000UL
2273 #define UV1H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_MASK 0x0000000000400000UL
2274 #define UV1H_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_MASK 0x0000000000800000UL
2275 #define UV1H_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000007000000UL
2276 #define UV1H_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_MASK 0x0000000008000000UL
2277 #define UV1H_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000010000000UL
2278 #define UV1H_LB_BAU_MISC_CONTROL_FUN_MASK               0xffff000000000000UL
2279 
2280 #define UVXH_LB_BAU_MISC_CONTROL_REJECTION_DELAY_SHFT   0
2281 #define UVXH_LB_BAU_MISC_CONTROL_APIC_MODE_SHFT         8
2282 #define UVXH_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_SHFT   9
2283 #define UVXH_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_SHFT    10
2284 #define UVXH_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_SHFT 11
2285 #define UVXH_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_SHFT 14
2286 #define UVXH_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_SHFT 20
2287 #define UVXH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_SHFT 21
2288 #define UVXH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_SHFT 22
2289 #define UVXH_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_SHFT 23
2290 #define UVXH_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_SHFT 24
2291 #define UVXH_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_SHFT 27
2292 #define UVXH_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_SHFT 28
2293 #define UVXH_LB_BAU_MISC_CONTROL_ENABLE_AUTOMATIC_APIC_MODE_SELECTION_SHFT 29
2294 #define UVXH_LB_BAU_MISC_CONTROL_APIC_MODE_STATUS_SHFT  30
2295 #define UVXH_LB_BAU_MISC_CONTROL_SUPPRESS_INTERRUPTS_TO_SELF_SHFT 31
2296 #define UVXH_LB_BAU_MISC_CONTROL_ENABLE_LOCK_BASED_SYSTEM_FLUSH_SHFT 32
2297 #define UVXH_LB_BAU_MISC_CONTROL_ENABLE_EXTENDED_SB_STATUS_SHFT 33
2298 #define UVXH_LB_BAU_MISC_CONTROL_SUPPRESS_INT_PRIO_UDT_TO_SELF_SHFT 34
2299 #define UVXH_LB_BAU_MISC_CONTROL_USE_LEGACY_DESCRIPTOR_FORMATS_SHFT 35
2300 #define UVXH_LB_BAU_MISC_CONTROL_FUN_SHFT               48
2301 #define UVXH_LB_BAU_MISC_CONTROL_REJECTION_DELAY_MASK   0x00000000000000ffUL
2302 #define UVXH_LB_BAU_MISC_CONTROL_APIC_MODE_MASK         0x0000000000000100UL
2303 #define UVXH_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_MASK   0x0000000000000200UL
2304 #define UVXH_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_MASK    0x0000000000000400UL
2305 #define UVXH_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_MASK 0x0000000000003800UL
2306 #define UVXH_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_MASK 0x0000000000004000UL
2307 #define UVXH_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_MASK 0x0000000000100000UL
2308 #define UVXH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_MASK 0x0000000000200000UL
2309 #define UVXH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_MASK 0x0000000000400000UL
2310 #define UVXH_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_MASK 0x0000000000800000UL
2311 #define UVXH_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000007000000UL
2312 #define UVXH_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_MASK 0x0000000008000000UL
2313 #define UVXH_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000010000000UL
2314 #define UVXH_LB_BAU_MISC_CONTROL_ENABLE_AUTOMATIC_APIC_MODE_SELECTION_MASK 0x0000000020000000UL
2315 #define UVXH_LB_BAU_MISC_CONTROL_APIC_MODE_STATUS_MASK  0x0000000040000000UL
2316 #define UVXH_LB_BAU_MISC_CONTROL_SUPPRESS_INTERRUPTS_TO_SELF_MASK 0x0000000080000000UL
2317 #define UVXH_LB_BAU_MISC_CONTROL_ENABLE_LOCK_BASED_SYSTEM_FLUSH_MASK 0x0000000100000000UL
2318 #define UVXH_LB_BAU_MISC_CONTROL_ENABLE_EXTENDED_SB_STATUS_MASK 0x0000000200000000UL
2319 #define UVXH_LB_BAU_MISC_CONTROL_SUPPRESS_INT_PRIO_UDT_TO_SELF_MASK 0x0000000400000000UL
2320 #define UVXH_LB_BAU_MISC_CONTROL_USE_LEGACY_DESCRIPTOR_FORMATS_MASK 0x0000000800000000UL
2321 #define UVXH_LB_BAU_MISC_CONTROL_FUN_MASK               0xffff000000000000UL
2322 
2323 #define UV2H_LB_BAU_MISC_CONTROL_REJECTION_DELAY_SHFT   0
2324 #define UV2H_LB_BAU_MISC_CONTROL_APIC_MODE_SHFT         8
2325 #define UV2H_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_SHFT   9
2326 #define UV2H_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_SHFT    10
2327 #define UV2H_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_SHFT 11
2328 #define UV2H_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_SHFT 14
2329 #define UV2H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT 15
2330 #define UV2H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT 16
2331 #define UV2H_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_SHFT 20
2332 #define UV2H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_SHFT 21
2333 #define UV2H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_SHFT 22
2334 #define UV2H_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_SHFT 23
2335 #define UV2H_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_SHFT 24
2336 #define UV2H_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_SHFT 27
2337 #define UV2H_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_SHFT 28
2338 #define UV2H_LB_BAU_MISC_CONTROL_ENABLE_AUTOMATIC_APIC_MODE_SELECTION_SHFT 29
2339 #define UV2H_LB_BAU_MISC_CONTROL_APIC_MODE_STATUS_SHFT  30
2340 #define UV2H_LB_BAU_MISC_CONTROL_SUPPRESS_INTERRUPTS_TO_SELF_SHFT 31
2341 #define UV2H_LB_BAU_MISC_CONTROL_ENABLE_LOCK_BASED_SYSTEM_FLUSH_SHFT 32
2342 #define UV2H_LB_BAU_MISC_CONTROL_ENABLE_EXTENDED_SB_STATUS_SHFT 33
2343 #define UV2H_LB_BAU_MISC_CONTROL_SUPPRESS_INT_PRIO_UDT_TO_SELF_SHFT 34
2344 #define UV2H_LB_BAU_MISC_CONTROL_USE_LEGACY_DESCRIPTOR_FORMATS_SHFT 35
2345 #define UV2H_LB_BAU_MISC_CONTROL_FUN_SHFT               48
2346 #define UV2H_LB_BAU_MISC_CONTROL_REJECTION_DELAY_MASK   0x00000000000000ffUL
2347 #define UV2H_LB_BAU_MISC_CONTROL_APIC_MODE_MASK         0x0000000000000100UL
2348 #define UV2H_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_MASK   0x0000000000000200UL
2349 #define UV2H_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_MASK    0x0000000000000400UL
2350 #define UV2H_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_MASK 0x0000000000003800UL
2351 #define UV2H_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_MASK 0x0000000000004000UL
2352 #define UV2H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_MASK 0x0000000000008000UL
2353 #define UV2H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK 0x00000000000f0000UL
2354 #define UV2H_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_MASK 0x0000000000100000UL
2355 #define UV2H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_MASK 0x0000000000200000UL
2356 #define UV2H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_MASK 0x0000000000400000UL
2357 #define UV2H_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_MASK 0x0000000000800000UL
2358 #define UV2H_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000007000000UL
2359 #define UV2H_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_MASK 0x0000000008000000UL
2360 #define UV2H_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000010000000UL
2361 #define UV2H_LB_BAU_MISC_CONTROL_ENABLE_AUTOMATIC_APIC_MODE_SELECTION_MASK 0x0000000020000000UL
2362 #define UV2H_LB_BAU_MISC_CONTROL_APIC_MODE_STATUS_MASK  0x0000000040000000UL
2363 #define UV2H_LB_BAU_MISC_CONTROL_SUPPRESS_INTERRUPTS_TO_SELF_MASK 0x0000000080000000UL
2364 #define UV2H_LB_BAU_MISC_CONTROL_ENABLE_LOCK_BASED_SYSTEM_FLUSH_MASK 0x0000000100000000UL
2365 #define UV2H_LB_BAU_MISC_CONTROL_ENABLE_EXTENDED_SB_STATUS_MASK 0x0000000200000000UL
2366 #define UV2H_LB_BAU_MISC_CONTROL_SUPPRESS_INT_PRIO_UDT_TO_SELF_MASK 0x0000000400000000UL
2367 #define UV2H_LB_BAU_MISC_CONTROL_USE_LEGACY_DESCRIPTOR_FORMATS_MASK 0x0000000800000000UL
2368 #define UV2H_LB_BAU_MISC_CONTROL_FUN_MASK               0xffff000000000000UL
2369 
2370 #define UV3H_LB_BAU_MISC_CONTROL_REJECTION_DELAY_SHFT   0
2371 #define UV3H_LB_BAU_MISC_CONTROL_APIC_MODE_SHFT         8
2372 #define UV3H_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_SHFT   9
2373 #define UV3H_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_SHFT    10
2374 #define UV3H_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_SHFT 11
2375 #define UV3H_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_SHFT 14
2376 #define UV3H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT 15
2377 #define UV3H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT 16
2378 #define UV3H_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_SHFT 20
2379 #define UV3H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_SHFT 21
2380 #define UV3H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_SHFT 22
2381 #define UV3H_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_SHFT 23
2382 #define UV3H_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_SHFT 24
2383 #define UV3H_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_SHFT 27
2384 #define UV3H_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_SHFT 28
2385 #define UV3H_LB_BAU_MISC_CONTROL_ENABLE_AUTOMATIC_APIC_MODE_SELECTION_SHFT 29
2386 #define UV3H_LB_BAU_MISC_CONTROL_APIC_MODE_STATUS_SHFT  30
2387 #define UV3H_LB_BAU_MISC_CONTROL_SUPPRESS_INTERRUPTS_TO_SELF_SHFT 31
2388 #define UV3H_LB_BAU_MISC_CONTROL_ENABLE_LOCK_BASED_SYSTEM_FLUSH_SHFT 32
2389 #define UV3H_LB_BAU_MISC_CONTROL_ENABLE_EXTENDED_SB_STATUS_SHFT 33
2390 #define UV3H_LB_BAU_MISC_CONTROL_SUPPRESS_INT_PRIO_UDT_TO_SELF_SHFT 34
2391 #define UV3H_LB_BAU_MISC_CONTROL_USE_LEGACY_DESCRIPTOR_FORMATS_SHFT 35
2392 #define UV3H_LB_BAU_MISC_CONTROL_SUPPRESS_QUIESCE_MSGS_TO_QPI_SHFT 36
2393 #define UV3H_LB_BAU_MISC_CONTROL_ENABLE_INTD_PREFETCH_HINT_SHFT 37
2394 #define UV3H_LB_BAU_MISC_CONTROL_THREAD_KILL_TIMEBASE_SHFT 38
2395 #define UV3H_LB_BAU_MISC_CONTROL_FUN_SHFT               48
2396 #define UV3H_LB_BAU_MISC_CONTROL_REJECTION_DELAY_MASK   0x00000000000000ffUL
2397 #define UV3H_LB_BAU_MISC_CONTROL_APIC_MODE_MASK         0x0000000000000100UL
2398 #define UV3H_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_MASK   0x0000000000000200UL
2399 #define UV3H_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_MASK    0x0000000000000400UL
2400 #define UV3H_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_MASK 0x0000000000003800UL
2401 #define UV3H_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_MASK 0x0000000000004000UL
2402 #define UV3H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_MASK 0x0000000000008000UL
2403 #define UV3H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK 0x00000000000f0000UL
2404 #define UV3H_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_MASK 0x0000000000100000UL
2405 #define UV3H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_MASK 0x0000000000200000UL
2406 #define UV3H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_MASK 0x0000000000400000UL
2407 #define UV3H_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_MASK 0x0000000000800000UL
2408 #define UV3H_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000007000000UL
2409 #define UV3H_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_MASK 0x0000000008000000UL
2410 #define UV3H_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000010000000UL
2411 #define UV3H_LB_BAU_MISC_CONTROL_ENABLE_AUTOMATIC_APIC_MODE_SELECTION_MASK 0x0000000020000000UL
2412 #define UV3H_LB_BAU_MISC_CONTROL_APIC_MODE_STATUS_MASK  0x0000000040000000UL
2413 #define UV3H_LB_BAU_MISC_CONTROL_SUPPRESS_INTERRUPTS_TO_SELF_MASK 0x0000000080000000UL
2414 #define UV3H_LB_BAU_MISC_CONTROL_ENABLE_LOCK_BASED_SYSTEM_FLUSH_MASK 0x0000000100000000UL
2415 #define UV3H_LB_BAU_MISC_CONTROL_ENABLE_EXTENDED_SB_STATUS_MASK 0x0000000200000000UL
2416 #define UV3H_LB_BAU_MISC_CONTROL_SUPPRESS_INT_PRIO_UDT_TO_SELF_MASK 0x0000000400000000UL
2417 #define UV3H_LB_BAU_MISC_CONTROL_USE_LEGACY_DESCRIPTOR_FORMATS_MASK 0x0000000800000000UL
2418 #define UV3H_LB_BAU_MISC_CONTROL_SUPPRESS_QUIESCE_MSGS_TO_QPI_MASK 0x0000001000000000UL
2419 #define UV3H_LB_BAU_MISC_CONTROL_ENABLE_INTD_PREFETCH_HINT_MASK 0x0000002000000000UL
2420 #define UV3H_LB_BAU_MISC_CONTROL_THREAD_KILL_TIMEBASE_MASK 0x00003fc000000000UL
2421 #define UV3H_LB_BAU_MISC_CONTROL_FUN_MASK               0xffff000000000000UL
2422 
2423 #define UV4H_LB_BAU_MISC_CONTROL_REJECTION_DELAY_SHFT   0
2424 #define UV4H_LB_BAU_MISC_CONTROL_APIC_MODE_SHFT         8
2425 #define UV4H_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_SHFT   9
2426 #define UV4H_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_SHFT    10
2427 #define UV4H_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_SHFT 11
2428 #define UV4H_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_SHFT 14
2429 #define UV4H_LB_BAU_MISC_CONTROL_RESERVED_15_19_SHFT    15
2430 #define UV4H_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_SHFT 20
2431 #define UV4H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_SHFT 21
2432 #define UV4H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_SHFT 22
2433 #define UV4H_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_SHFT 23
2434 #define UV4H_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_SHFT 24
2435 #define UV4H_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_SHFT 27
2436 #define UV4H_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_SHFT 28
2437 #define UV4H_LB_BAU_MISC_CONTROL_ENABLE_AUTOMATIC_APIC_MODE_SELECTION_SHFT 29
2438 #define UV4H_LB_BAU_MISC_CONTROL_APIC_MODE_STATUS_SHFT  30
2439 #define UV4H_LB_BAU_MISC_CONTROL_SUPPRESS_INTERRUPTS_TO_SELF_SHFT 31
2440 #define UV4H_LB_BAU_MISC_CONTROL_ENABLE_LOCK_BASED_SYSTEM_FLUSH_SHFT 32
2441 #define UV4H_LB_BAU_MISC_CONTROL_ENABLE_EXTENDED_SB_STATUS_SHFT 33
2442 #define UV4H_LB_BAU_MISC_CONTROL_SUPPRESS_INT_PRIO_UDT_TO_SELF_SHFT 34
2443 #define UV4H_LB_BAU_MISC_CONTROL_USE_LEGACY_DESCRIPTOR_FORMATS_SHFT 35
2444 #define UV4H_LB_BAU_MISC_CONTROL_SUPPRESS_QUIESCE_MSGS_TO_QPI_SHFT 36
2445 #define UV4H_LB_BAU_MISC_CONTROL_RESERVED_37_SHFT       37
2446 #define UV4H_LB_BAU_MISC_CONTROL_THREAD_KILL_TIMEBASE_SHFT 38
2447 #define UV4H_LB_BAU_MISC_CONTROL_ADDRESS_INTERLEAVE_SELECT_SHFT 46
2448 #define UV4H_LB_BAU_MISC_CONTROL_FUN_SHFT               48
2449 #define UV4H_LB_BAU_MISC_CONTROL_REJECTION_DELAY_MASK   0x00000000000000ffUL
2450 #define UV4H_LB_BAU_MISC_CONTROL_APIC_MODE_MASK         0x0000000000000100UL
2451 #define UV4H_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_MASK   0x0000000000000200UL
2452 #define UV4H_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_MASK    0x0000000000000400UL
2453 #define UV4H_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_MASK 0x0000000000003800UL
2454 #define UV4H_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_MASK 0x0000000000004000UL
2455 #define UV4H_LB_BAU_MISC_CONTROL_RESERVED_15_19_MASK    0x00000000000f8000UL
2456 #define UV4H_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_MASK 0x0000000000100000UL
2457 #define UV4H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_MASK 0x0000000000200000UL
2458 #define UV4H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_MASK 0x0000000000400000UL
2459 #define UV4H_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_MASK 0x0000000000800000UL
2460 #define UV4H_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000007000000UL
2461 #define UV4H_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_MASK 0x0000000008000000UL
2462 #define UV4H_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000010000000UL
2463 #define UV4H_LB_BAU_MISC_CONTROL_ENABLE_AUTOMATIC_APIC_MODE_SELECTION_MASK 0x0000000020000000UL
2464 #define UV4H_LB_BAU_MISC_CONTROL_APIC_MODE_STATUS_MASK  0x0000000040000000UL
2465 #define UV4H_LB_BAU_MISC_CONTROL_SUPPRESS_INTERRUPTS_TO_SELF_MASK 0x0000000080000000UL
2466 #define UV4H_LB_BAU_MISC_CONTROL_ENABLE_LOCK_BASED_SYSTEM_FLUSH_MASK 0x0000000100000000UL
2467 #define UV4H_LB_BAU_MISC_CONTROL_ENABLE_EXTENDED_SB_STATUS_MASK 0x0000000200000000UL
2468 #define UV4H_LB_BAU_MISC_CONTROL_SUPPRESS_INT_PRIO_UDT_TO_SELF_MASK 0x0000000400000000UL
2469 #define UV4H_LB_BAU_MISC_CONTROL_USE_LEGACY_DESCRIPTOR_FORMATS_MASK 0x0000000800000000UL
2470 #define UV4H_LB_BAU_MISC_CONTROL_SUPPRESS_QUIESCE_MSGS_TO_QPI_MASK 0x0000001000000000UL
2471 #define UV4H_LB_BAU_MISC_CONTROL_RESERVED_37_MASK       0x0000002000000000UL
2472 #define UV4H_LB_BAU_MISC_CONTROL_THREAD_KILL_TIMEBASE_MASK 0x00003fc000000000UL
2473 #define UV4H_LB_BAU_MISC_CONTROL_ADDRESS_INTERLEAVE_SELECT_MASK 0x0000400000000000UL
2474 #define UV4H_LB_BAU_MISC_CONTROL_FUN_MASK               0xffff000000000000UL
2475 
2476 #define UV4H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_MASK \
2477         uv_undefined("UV4H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_MASK")
2478 #define UVH_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_MASK (        \
2479         is_uv1_hub() ? UV1H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_MASK : \
2480         is_uv2_hub() ? UV2H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_MASK : \
2481         is_uv3_hub() ? UV3H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_MASK : \
2482         /*is_uv4_hub*/ UV4H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_MASK)
2483 #define UV4H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT \
2484         uv_undefined("UV4H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT")
2485 #define UVH_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT (        \
2486         is_uv1_hub() ? UV1H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT : \
2487         is_uv2_hub() ? UV2H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT : \
2488         is_uv3_hub() ? UV3H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT : \
2489         /*is_uv4_hub*/ UV4H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT)
2490 #define UV4H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK      \
2491         uv_undefined("UV4H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK")
2492 #define UVH_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK (     \
2493         is_uv1_hub() ? UV1H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK : \
2494         is_uv2_hub() ? UV2H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK : \
2495         is_uv3_hub() ? UV3H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK : \
2496         /*is_uv4_hub*/ UV4H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK)
2497 #define UV4H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT      \
2498         uv_undefined("UV4H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT")
2499 #define UVH_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT (     \
2500         is_uv1_hub() ? UV1H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT : \
2501         is_uv2_hub() ? UV2H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT : \
2502         is_uv3_hub() ? UV3H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT : \
2503         /*is_uv4_hub*/ UV4H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT)
2504 
2505 union uvh_lb_bau_misc_control_u {
2506         unsigned long   v;
2507         struct uvh_lb_bau_misc_control_s {
2508                 unsigned long   rejection_delay:8;              /* RW */
2509                 unsigned long   apic_mode:1;                    /* RW */
2510                 unsigned long   force_broadcast:1;              /* RW */
2511                 unsigned long   force_lock_nop:1;               /* RW */
2512                 unsigned long   qpi_agent_presence_vector:3;    /* RW */
2513                 unsigned long   descriptor_fetch_mode:1;        /* RW */
2514                 unsigned long   rsvd_15_19:5;
2515                 unsigned long   enable_dual_mapping_mode:1;     /* RW */
2516                 unsigned long   vga_io_port_decode_enable:1;    /* RW */
2517                 unsigned long   vga_io_port_16_bit_decode:1;    /* RW */
2518                 unsigned long   suppress_dest_registration:1;   /* RW */
2519                 unsigned long   programmed_initial_priority:3;  /* RW */
2520                 unsigned long   use_incoming_priority:1;        /* RW */
2521                 unsigned long   enable_programmed_initial_priority:1;/* RW */
2522                 unsigned long   rsvd_29_47:19;
2523                 unsigned long   fun:16;                         /* RW */
2524         } s;
2525         struct uv1h_lb_bau_misc_control_s {
2526                 unsigned long   rejection_delay:8;              /* RW */
2527                 unsigned long   apic_mode:1;                    /* RW */
2528                 unsigned long   force_broadcast:1;              /* RW */
2529                 unsigned long   force_lock_nop:1;               /* RW */
2530                 unsigned long   qpi_agent_presence_vector:3;    /* RW */
2531                 unsigned long   descriptor_fetch_mode:1;        /* RW */
2532                 unsigned long   enable_intd_soft_ack_mode:1;    /* RW */
2533                 unsigned long   intd_soft_ack_timeout_period:4; /* RW */
2534                 unsigned long   enable_dual_mapping_mode:1;     /* RW */
2535                 unsigned long   vga_io_port_decode_enable:1;    /* RW */
2536                 unsigned long   vga_io_port_16_bit_decode:1;    /* RW */
2537                 unsigned long   suppress_dest_registration:1;   /* RW */
2538                 unsigned long   programmed_initial_priority:3;  /* RW */
2539                 unsigned long   use_incoming_priority:1;        /* RW */
2540                 unsigned long   enable_programmed_initial_priority:1;/* RW */
2541                 unsigned long   rsvd_29_47:19;
2542                 unsigned long   fun:16;                         /* RW */
2543         } s1;
2544         struct uvxh_lb_bau_misc_control_s {
2545                 unsigned long   rejection_delay:8;              /* RW */
2546                 unsigned long   apic_mode:1;                    /* RW */
2547                 unsigned long   force_broadcast:1;              /* RW */
2548                 unsigned long   force_lock_nop:1;               /* RW */
2549                 unsigned long   qpi_agent_presence_vector:3;    /* RW */
2550                 unsigned long   descriptor_fetch_mode:1;        /* RW */
2551                 unsigned long   rsvd_15_19:5;
2552                 unsigned long   enable_dual_mapping_mode:1;     /* RW */
2553                 unsigned long   vga_io_port_decode_enable:1;    /* RW */
2554                 unsigned long   vga_io_port_16_bit_decode:1;    /* RW */
2555                 unsigned long   suppress_dest_registration:1;   /* RW */
2556                 unsigned long   programmed_initial_priority:3;  /* RW */
2557                 unsigned long   use_incoming_priority:1;        /* RW */
2558                 unsigned long   enable_programmed_initial_priority:1;/* RW */
2559                 unsigned long   enable_automatic_apic_mode_selection:1;/* RW */
2560                 unsigned long   apic_mode_status:1;             /* RO */
2561                 unsigned long   suppress_interrupts_to_self:1;  /* RW */
2562                 unsigned long   enable_lock_based_system_flush:1;/* RW */
2563                 unsigned long   enable_extended_sb_status:1;    /* RW */
2564                 unsigned long   suppress_int_prio_udt_to_self:1;/* RW */
2565                 unsigned long   use_legacy_descriptor_formats:1;/* RW */
2566                 unsigned long   rsvd_36_47:12;
2567                 unsigned long   fun:16;                         /* RW */
2568         } sx;
2569         struct uv2h_lb_bau_misc_control_s {
2570                 unsigned long   rejection_delay:8;              /* RW */
2571                 unsigned long   apic_mode:1;                    /* RW */
2572                 unsigned long   force_broadcast:1;              /* RW */
2573                 unsigned long   force_lock_nop:1;               /* RW */
2574                 unsigned long   qpi_agent_presence_vector:3;    /* RW */
2575                 unsigned long   descriptor_fetch_mode:1;        /* RW */
2576                 unsigned long   enable_intd_soft_ack_mode:1;    /* RW */
2577                 unsigned long   intd_soft_ack_timeout_period:4; /* RW */
2578                 unsigned long   enable_dual_mapping_mode:1;     /* RW */
2579                 unsigned long   vga_io_port_decode_enable:1;    /* RW */
2580                 unsigned long   vga_io_port_16_bit_decode:1;    /* RW */
2581                 unsigned long   suppress_dest_registration:1;   /* RW */
2582                 unsigned long   programmed_initial_priority:3;  /* RW */
2583                 unsigned long   use_incoming_priority:1;        /* RW */
2584                 unsigned long   enable_programmed_initial_priority:1;/* RW */
2585                 unsigned long   enable_automatic_apic_mode_selection:1;/* RW */
2586                 unsigned long   apic_mode_status:1;             /* RO */
2587                 unsigned long   suppress_interrupts_to_self:1;  /* RW */
2588                 unsigned long   enable_lock_based_system_flush:1;/* RW */
2589                 unsigned long   enable_extended_sb_status:1;    /* RW */
2590                 unsigned long   suppress_int_prio_udt_to_self:1;/* RW */
2591                 unsigned long   use_legacy_descriptor_formats:1;/* RW */
2592                 unsigned long   rsvd_36_47:12;
2593                 unsigned long   fun:16;                         /* RW */
2594         } s2;
2595         struct uv3h_lb_bau_misc_control_s {
2596                 unsigned long   rejection_delay:8;              /* RW */
2597                 unsigned long   apic_mode:1;                    /* RW */
2598                 unsigned long   force_broadcast:1;              /* RW */
2599                 unsigned long   force_lock_nop:1;               /* RW */
2600                 unsigned long   qpi_agent_presence_vector:3;    /* RW */
2601                 unsigned long   descriptor_fetch_mode:1;        /* RW */
2602                 unsigned long   enable_intd_soft_ack_mode:1;    /* RW */
2603                 unsigned long   intd_soft_ack_timeout_period:4; /* RW */
2604                 unsigned long   enable_dual_mapping_mode:1;     /* RW */
2605                 unsigned long   vga_io_port_decode_enable:1;    /* RW */
2606                 unsigned long   vga_io_port_16_bit_decode:1;    /* RW */
2607                 unsigned long   suppress_dest_registration:1;   /* RW */
2608                 unsigned long   programmed_initial_priority:3;  /* RW */
2609                 unsigned long   use_incoming_priority:1;        /* RW */
2610                 unsigned long   enable_programmed_initial_priority:1;/* RW */
2611                 unsigned long   enable_automatic_apic_mode_selection:1;/* RW */
2612                 unsigned long   apic_mode_status:1;             /* RO */
2613                 unsigned long   suppress_interrupts_to_self:1;  /* RW */
2614                 unsigned long   enable_lock_based_system_flush:1;/* RW */
2615                 unsigned long   enable_extended_sb_status:1;    /* RW */
2616                 unsigned long   suppress_int_prio_udt_to_self:1;/* RW */
2617                 unsigned long   use_legacy_descriptor_formats:1;/* RW */
2618                 unsigned long   suppress_quiesce_msgs_to_qpi:1; /* RW */
2619                 unsigned long   enable_intd_prefetch_hint:1;    /* RW */
2620                 unsigned long   thread_kill_timebase:8;         /* RW */
2621                 unsigned long   rsvd_46_47:2;
2622                 unsigned long   fun:16;                         /* RW */
2623         } s3;
2624         struct uv4h_lb_bau_misc_control_s {
2625                 unsigned long   rejection_delay:8;              /* RW */
2626                 unsigned long   apic_mode:1;                    /* RW */
2627                 unsigned long   force_broadcast:1;              /* RW */
2628                 unsigned long   force_lock_nop:1;               /* RW */
2629                 unsigned long   qpi_agent_presence_vector:3;    /* RW */
2630                 unsigned long   descriptor_fetch_mode:1;        /* RW */
2631                 unsigned long   rsvd_15_19:5;
2632                 unsigned long   enable_dual_mapping_mode:1;     /* RW */
2633                 unsigned long   vga_io_port_decode_enable:1;    /* RW */
2634                 unsigned long   vga_io_port_16_bit_decode:1;    /* RW */
2635                 unsigned long   suppress_dest_registration:1;   /* RW */
2636                 unsigned long   programmed_initial_priority:3;  /* RW */
2637                 unsigned long   use_incoming_priority:1;        /* RW */
2638                 unsigned long   enable_programmed_initial_priority:1;/* RW */
2639                 unsigned long   enable_automatic_apic_mode_selection:1;/* RW */
2640                 unsigned long   apic_mode_status:1;             /* RO */
2641                 unsigned long   suppress_interrupts_to_self:1;  /* RW */
2642                 unsigned long   enable_lock_based_system_flush:1;/* RW */
2643                 unsigned long   enable_extended_sb_status:1;    /* RW */
2644                 unsigned long   suppress_int_prio_udt_to_self:1;/* RW */
2645                 unsigned long   use_legacy_descriptor_formats:1;/* RW */
2646                 unsigned long   suppress_quiesce_msgs_to_qpi:1; /* RW */
2647                 unsigned long   rsvd_37:1;
2648                 unsigned long   thread_kill_timebase:8;         /* RW */
2649                 unsigned long   address_interleave_select:1;    /* RW */
2650                 unsigned long   rsvd_47:1;
2651                 unsigned long   fun:16;                         /* RW */
2652         } s4;
2653 };
2654 
2655 /* ========================================================================= */
2656 /*                     UVH_LB_BAU_SB_ACTIVATION_CONTROL                      */
2657 /* ========================================================================= */
2658 #define UV1H_LB_BAU_SB_ACTIVATION_CONTROL 0x320020UL
2659 #define UV2H_LB_BAU_SB_ACTIVATION_CONTROL 0x320020UL
2660 #define UV3H_LB_BAU_SB_ACTIVATION_CONTROL 0x320020UL
2661 #define UV4H_LB_BAU_SB_ACTIVATION_CONTROL 0xc8020UL
2662 #define UVH_LB_BAU_SB_ACTIVATION_CONTROL (                              \
2663         is_uv1_hub() ? UV1H_LB_BAU_SB_ACTIVATION_CONTROL :              \
2664         is_uv2_hub() ? UV2H_LB_BAU_SB_ACTIVATION_CONTROL :              \
2665         is_uv3_hub() ? UV3H_LB_BAU_SB_ACTIVATION_CONTROL :              \
2666         /*is_uv4_hub*/ UV4H_LB_BAU_SB_ACTIVATION_CONTROL)
2667 
2668 #define UV1H_LB_BAU_SB_ACTIVATION_CONTROL_32 0x9a8
2669 #define UV2H_LB_BAU_SB_ACTIVATION_CONTROL_32 0x9a8
2670 #define UV3H_LB_BAU_SB_ACTIVATION_CONTROL_32 0x9a8
2671 #define UV4H_LB_BAU_SB_ACTIVATION_CONTROL_32 0x9c8
2672 #define UVH_LB_BAU_SB_ACTIVATION_CONTROL_32 (                           \
2673         is_uv1_hub() ? UV1H_LB_BAU_SB_ACTIVATION_CONTROL_32 :           \
2674         is_uv2_hub() ? UV2H_LB_BAU_SB_ACTIVATION_CONTROL_32 :           \
2675         is_uv3_hub() ? UV3H_LB_BAU_SB_ACTIVATION_CONTROL_32 :           \
2676         /*is_uv4_hub*/ UV4H_LB_BAU_SB_ACTIVATION_CONTROL_32)
2677 
2678 #define UVH_LB_BAU_SB_ACTIVATION_CONTROL_INDEX_SHFT     0
2679 #define UVH_LB_BAU_SB_ACTIVATION_CONTROL_PUSH_SHFT      62
2680 #define UVH_LB_BAU_SB_ACTIVATION_CONTROL_INIT_SHFT      63
2681 #define UVH_LB_BAU_SB_ACTIVATION_CONTROL_INDEX_MASK     0x000000000000003fUL
2682 #define UVH_LB_BAU_SB_ACTIVATION_CONTROL_PUSH_MASK      0x4000000000000000UL
2683 #define UVH_LB_BAU_SB_ACTIVATION_CONTROL_INIT_MASK      0x8000000000000000UL
2684 
2685 
2686 union uvh_lb_bau_sb_activation_control_u {
2687         unsigned long   v;
2688         struct uvh_lb_bau_sb_activation_control_s {
2689                 unsigned long   index:6;                        /* RW */
2690                 unsigned long   rsvd_6_61:56;
2691                 unsigned long   push:1;                         /* WP */
2692                 unsigned long   init:1;                         /* WP */
2693         } s;
2694 };
2695 
2696 /* ========================================================================= */
2697 /*                    UVH_LB_BAU_SB_ACTIVATION_STATUS_0                      */
2698 /* ========================================================================= */
2699 #define UV1H_LB_BAU_SB_ACTIVATION_STATUS_0 0x320030UL
2700 #define UV2H_LB_BAU_SB_ACTIVATION_STATUS_0 0x320030UL
2701 #define UV3H_LB_BAU_SB_ACTIVATION_STATUS_0 0x320030UL
2702 #define UV4H_LB_BAU_SB_ACTIVATION_STATUS_0 0xc8030UL
2703 #define UVH_LB_BAU_SB_ACTIVATION_STATUS_0 (                             \
2704         is_uv1_hub() ? UV1H_LB_BAU_SB_ACTIVATION_STATUS_0 :             \
2705         is_uv2_hub() ? UV2H_LB_BAU_SB_ACTIVATION_STATUS_0 :             \
2706         is_uv3_hub() ? UV3H_LB_BAU_SB_ACTIVATION_STATUS_0 :             \
2707         /*is_uv4_hub*/ UV4H_LB_BAU_SB_ACTIVATION_STATUS_0)
2708 
2709 #define UV1H_LB_BAU_SB_ACTIVATION_STATUS_0_32 0x9b0
2710 #define UV2H_LB_BAU_SB_ACTIVATION_STATUS_0_32 0x9b0
2711 #define UV3H_LB_BAU_SB_ACTIVATION_STATUS_0_32 0x9b0
2712 #define UV4H_LB_BAU_SB_ACTIVATION_STATUS_0_32 0x9d0
2713 #define UVH_LB_BAU_SB_ACTIVATION_STATUS_0_32 (                          \
2714         is_uv1_hub() ? UV1H_LB_BAU_SB_ACTIVATION_STATUS_0_32 :          \
2715         is_uv2_hub() ? UV2H_LB_BAU_SB_ACTIVATION_STATUS_0_32 :          \
2716         is_uv3_hub() ? UV3H_LB_BAU_SB_ACTIVATION_STATUS_0_32 :          \
2717         /*is_uv4_hub*/ UV4H_LB_BAU_SB_ACTIVATION_STATUS_0_32)
2718 
2719 #define UVH_LB_BAU_SB_ACTIVATION_STATUS_0_STATUS_SHFT   0
2720 #define UVH_LB_BAU_SB_ACTIVATION_STATUS_0_STATUS_MASK   0xffffffffffffffffUL
2721 
2722 
2723 union uvh_lb_bau_sb_activation_status_0_u {
2724         unsigned long   v;
2725         struct uvh_lb_bau_sb_activation_status_0_s {
2726                 unsigned long   status:64;                      /* RW */
2727         } s;
2728 };
2729 
2730 /* ========================================================================= */
2731 /*                    UVH_LB_BAU_SB_ACTIVATION_STATUS_1                      */
2732 /* ========================================================================= */
2733 #define UV1H_LB_BAU_SB_ACTIVATION_STATUS_1 0x320040UL
2734 #define UV2H_LB_BAU_SB_ACTIVATION_STATUS_1 0x320040UL
2735 #define UV3H_LB_BAU_SB_ACTIVATION_STATUS_1 0x320040UL
2736 #define UV4H_LB_BAU_SB_ACTIVATION_STATUS_1 0xc8040UL
2737 #define UVH_LB_BAU_SB_ACTIVATION_STATUS_1 (                             \
2738         is_uv1_hub() ? UV1H_LB_BAU_SB_ACTIVATION_STATUS_1 :             \
2739         is_uv2_hub() ? UV2H_LB_BAU_SB_ACTIVATION_STATUS_1 :             \
2740         is_uv3_hub() ? UV3H_LB_BAU_SB_ACTIVATION_STATUS_1 :             \
2741         /*is_uv4_hub*/ UV4H_LB_BAU_SB_ACTIVATION_STATUS_1)
2742 
2743 #define UV1H_LB_BAU_SB_ACTIVATION_STATUS_1_32 0x9b8
2744 #define UV2H_LB_BAU_SB_ACTIVATION_STATUS_1_32 0x9b8
2745 #define UV3H_LB_BAU_SB_ACTIVATION_STATUS_1_32 0x9b8
2746 #define UV4H_LB_BAU_SB_ACTIVATION_STATUS_1_32 0x9d8
2747 #define UVH_LB_BAU_SB_ACTIVATION_STATUS_1_32 (                          \
2748         is_uv1_hub() ? UV1H_LB_BAU_SB_ACTIVATION_STATUS_1_32 :          \
2749         is_uv2_hub() ? UV2H_LB_BAU_SB_ACTIVATION_STATUS_1_32 :          \
2750         is_uv3_hub() ? UV3H_LB_BAU_SB_ACTIVATION_STATUS_1_32 :          \
2751         /*is_uv4_hub*/ UV4H_LB_BAU_SB_ACTIVATION_STATUS_1_32)
2752 
2753 #define UVH_LB_BAU_SB_ACTIVATION_STATUS_1_STATUS_SHFT   0
2754 #define UVH_LB_BAU_SB_ACTIVATION_STATUS_1_STATUS_MASK   0xffffffffffffffffUL
2755 
2756 
2757 union uvh_lb_bau_sb_activation_status_1_u {
2758         unsigned long   v;
2759         struct uvh_lb_bau_sb_activation_status_1_s {
2760                 unsigned long   status:64;                      /* RW */
2761         } s;
2762 };
2763 
2764 /* ========================================================================= */
2765 /*                      UVH_LB_BAU_SB_DESCRIPTOR_BASE                        */
2766 /* ========================================================================= */
2767 #define UV1H_LB_BAU_SB_DESCRIPTOR_BASE 0x320010UL
2768 #define UV2H_LB_BAU_SB_DESCRIPTOR_BASE 0x320010UL
2769 #define UV3H_LB_BAU_SB_DESCRIPTOR_BASE 0x320010UL
2770 #define UV4H_LB_BAU_SB_DESCRIPTOR_BASE 0xc8010UL
2771 #define UVH_LB_BAU_SB_DESCRIPTOR_BASE (                                 \
2772         is_uv1_hub() ? UV1H_LB_BAU_SB_DESCRIPTOR_BASE :                 \
2773         is_uv2_hub() ? UV2H_LB_BAU_SB_DESCRIPTOR_BASE :                 \
2774         is_uv3_hub() ? UV3H_LB_BAU_SB_DESCRIPTOR_BASE :                 \
2775         /*is_uv4_hub*/ UV4H_LB_BAU_SB_DESCRIPTOR_BASE)
2776 
2777 #define UV1H_LB_BAU_SB_DESCRIPTOR_BASE_32 0x9a0
2778 #define UV2H_LB_BAU_SB_DESCRIPTOR_BASE_32 0x9a0
2779 #define UV3H_LB_BAU_SB_DESCRIPTOR_BASE_32 0x9a0
2780 #define UV4H_LB_BAU_SB_DESCRIPTOR_BASE_32 0x9c0
2781 #define UVH_LB_BAU_SB_DESCRIPTOR_BASE_32 (                              \
2782         is_uv1_hub() ? UV1H_LB_BAU_SB_DESCRIPTOR_BASE_32 :              \
2783         is_uv2_hub() ? UV2H_LB_BAU_SB_DESCRIPTOR_BASE_32 :              \
2784         is_uv3_hub() ? UV3H_LB_BAU_SB_DESCRIPTOR_BASE_32 :              \
2785         /*is_uv4_hub*/ UV4H_LB_BAU_SB_DESCRIPTOR_BASE_32)
2786 
2787 #define UVH_LB_BAU_SB_DESCRIPTOR_BASE_PAGE_ADDRESS_SHFT 12
2788 
2789 #define UV1H_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_SHFT     49
2790 #define UV1H_LB_BAU_SB_DESCRIPTOR_BASE_PAGE_ADDRESS_MASK 0x000007fffffff000UL
2791 #define UV1H_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_MASK     0x7ffe000000000000UL
2792 
2793 #define UV2H_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_SHFT     49
2794 #define UV2H_LB_BAU_SB_DESCRIPTOR_BASE_PAGE_ADDRESS_MASK 0x000007fffffff000UL
2795 #define UV2H_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_MASK     0x7ffe000000000000UL
2796 
2797 #define UV3H_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_SHFT     49
2798 #define UV3H_LB_BAU_SB_DESCRIPTOR_BASE_PAGE_ADDRESS_MASK 0x000007fffffff000UL
2799 #define UV3H_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_MASK     0x7ffe000000000000UL
2800 
2801 #define UV4H_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_SHFT     49
2802 #define UV4H_LB_BAU_SB_DESCRIPTOR_BASE_PAGE_ADDRESS_MASK 0x00003ffffffff000UL
2803 #define UV4H_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_MASK     0x7ffe000000000000UL
2804 
2805 #define UV4AH_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_SHFT    53
2806 #define UV4AH_LB_BAU_SB_DESCRIPTOR_BASE_PAGE_ADDRESS_MASK 0x000ffffffffff000UL
2807 #define UV4AH_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_MASK    0xffe0000000000000UL
2808 
2809 #define UVH_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_SHFT (                    \
2810         is_uv1_hub() ? UV1H_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_SHFT :    \
2811         is_uv2_hub() ? UV2H_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_SHFT :    \
2812         is_uv3_hub() ? UV3H_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_SHFT :    \
2813         is_uv4a_hub() ? UV4AH_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_SHFT :  \
2814         /*is_uv4_hub*/ UV4H_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_SHFT)
2815 
2816 #define UVH_LB_BAU_SB_DESCRIPTOR_PAGE_ADDRESS_MASK (                    \
2817         is_uv1_hub() ? UV1H_LB_BAU_SB_DESCRIPTOR_PAGE_ADDRESS_MASK :    \
2818         is_uv2_hub() ? UV2H_LB_BAU_SB_DESCRIPTOR_PAGE_ADDRESS_MASK :    \
2819         is_uv3_hub() ? UV3H_LB_BAU_SB_DESCRIPTOR_PAGE_ADDRESS_MASK :    \
2820         is_uv4a_hub() ? UV4AH_LB_BAU_SB_DESCRIPTOR_PAGE_ADDRESS_MASK :  \
2821         /*is_uv4_hub*/ UV4H_LB_BAU_SB_DESCRIPTOR_PAGE_ADDRESS_MASK)
2822 
2823 #define UVH_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_MASK (                    \
2824         is_uv1_hub() ? UV1H_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_MASK :    \
2825         is_uv2_hub() ? UV2H_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_MASK :    \
2826         is_uv3_hub() ? UV3H_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_MASK :    \
2827         is_uv4a_hub() ? UV4AH_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_MASK :  \
2828         /*is_uv4_hub*/ UV4H_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_MASK)
2829 
2830 /* ========================================================================= */
2831 /*                               UVH_NODE_ID                                 */
2832 /* ========================================================================= */
2833 #define UVH_NODE_ID 0x0UL
2834 #define UV1H_NODE_ID 0x0UL
2835 #define UV2H_NODE_ID 0x0UL
2836 #define UV3H_NODE_ID 0x0UL
2837 #define UV4H_NODE_ID 0x0UL
2838 
2839 #define UVH_NODE_ID_FORCE1_SHFT                         0
2840 #define UVH_NODE_ID_MANUFACTURER_SHFT                   1
2841 #define UVH_NODE_ID_PART_NUMBER_SHFT                    12
2842 #define UVH_NODE_ID_REVISION_SHFT                       28
2843 #define UVH_NODE_ID_NODE_ID_SHFT                        32
2844 #define UVH_NODE_ID_FORCE1_MASK                         0x0000000000000001UL
2845 #define UVH_NODE_ID_MANUFACTURER_MASK                   0x0000000000000ffeUL
2846 #define UVH_NODE_ID_PART_NUMBER_MASK                    0x000000000ffff000UL
2847 #define UVH_NODE_ID_REVISION_MASK                       0x00000000f0000000UL
2848 #define UVH_NODE_ID_NODE_ID_MASK                        0x00007fff00000000UL
2849 
2850 #define UV1H_NODE_ID_FORCE1_SHFT                        0
2851 #define UV1H_NODE_ID_MANUFACTURER_SHFT                  1
2852 #define UV1H_NODE_ID_PART_NUMBER_SHFT                   12
2853 #define UV1H_NODE_ID_REVISION_SHFT                      28
2854 #define UV1H_NODE_ID_NODE_ID_SHFT                       32
2855 #define UV1H_NODE_ID_NODES_PER_BIT_SHFT                 48
2856 #define UV1H_NODE_ID_NI_PORT_SHFT                       56
2857 #define UV1H_NODE_ID_FORCE1_MASK                        0x0000000000000001UL
2858 #define UV1H_NODE_ID_MANUFACTURER_MASK                  0x0000000000000ffeUL
2859 #define UV1H_NODE_ID_PART_NUMBER_MASK                   0x000000000ffff000UL
2860 #define UV1H_NODE_ID_REVISION_MASK                      0x00000000f0000000UL
2861 #define UV1H_NODE_ID_NODE_ID_MASK                       0x00007fff00000000UL
2862 #define UV1H_NODE_ID_NODES_PER_BIT_MASK                 0x007f000000000000UL
2863 #define UV1H_NODE_ID_NI_PORT_MASK                       0x0f00000000000000UL
2864 
2865 #define UVXH_NODE_ID_FORCE1_SHFT                        0
2866 #define UVXH_NODE_ID_MANUFACTURER_SHFT                  1
2867 #define UVXH_NODE_ID_PART_NUMBER_SHFT                   12
2868 #define UVXH_NODE_ID_REVISION_SHFT                      28
2869 #define UVXH_NODE_ID_NODE_ID_SHFT                       32
2870 #define UVXH_NODE_ID_NODES_PER_BIT_SHFT                 50
2871 #define UVXH_NODE_ID_NI_PORT_SHFT                       57
2872 #define UVXH_NODE_ID_FORCE1_MASK                        0x0000000000000001UL
2873 #define UVXH_NODE_ID_MANUFACTURER_MASK                  0x0000000000000ffeUL
2874 #define UVXH_NODE_ID_PART_NUMBER_MASK                   0x000000000ffff000UL
2875 #define UVXH_NODE_ID_REVISION_MASK                      0x00000000f0000000UL
2876 #define UVXH_NODE_ID_NODE_ID_MASK                       0x00007fff00000000UL
2877 #define UVXH_NODE_ID_NODES_PER_BIT_MASK                 0x01fc000000000000UL
2878 #define UVXH_NODE_ID_NI_PORT_MASK                       0x3e00000000000000UL
2879 
2880 #define UV2H_NODE_ID_FORCE1_SHFT                        0
2881 #define UV2H_NODE_ID_MANUFACTURER_SHFT                  1
2882 #define UV2H_NODE_ID_PART_NUMBER_SHFT                   12
2883 #define UV2H_NODE_ID_REVISION_SHFT                      28
2884 #define UV2H_NODE_ID_NODE_ID_SHFT                       32
2885 #define UV2H_NODE_ID_NODES_PER_BIT_SHFT                 50
2886 #define UV2H_NODE_ID_NI_PORT_SHFT                       57
2887 #define UV2H_NODE_ID_FORCE1_MASK                        0x0000000000000001UL
2888 #define UV2H_NODE_ID_MANUFACTURER_MASK                  0x0000000000000ffeUL
2889 #define UV2H_NODE_ID_PART_NUMBER_MASK                   0x000000000ffff000UL
2890 #define UV2H_NODE_ID_REVISION_MASK                      0x00000000f0000000UL
2891 #define UV2H_NODE_ID_NODE_ID_MASK                       0x00007fff00000000UL
2892 #define UV2H_NODE_ID_NODES_PER_BIT_MASK                 0x01fc000000000000UL
2893 #define UV2H_NODE_ID_NI_PORT_MASK                       0x3e00000000000000UL
2894 
2895 #define UV3H_NODE_ID_FORCE1_SHFT                        0
2896 #define UV3H_NODE_ID_MANUFACTURER_SHFT                  1
2897 #define UV3H_NODE_ID_PART_NUMBER_SHFT                   12
2898 #define UV3H_NODE_ID_REVISION_SHFT                      28
2899 #define UV3H_NODE_ID_NODE_ID_SHFT                       32
2900 #define UV3H_NODE_ID_ROUTER_SELECT_SHFT                 48
2901 #define UV3H_NODE_ID_RESERVED_2_SHFT                    49
2902 #define UV3H_NODE_ID_NODES_PER_BIT_SHFT                 50
2903 #define UV3H_NODE_ID_NI_PORT_SHFT                       57
2904 #define UV3H_NODE_ID_FORCE1_MASK                        0x0000000000000001UL
2905 #define UV3H_NODE_ID_MANUFACTURER_MASK                  0x0000000000000ffeUL
2906 #define UV3H_NODE_ID_PART_NUMBER_MASK                   0x000000000ffff000UL
2907 #define UV3H_NODE_ID_REVISION_MASK                      0x00000000f0000000UL
2908 #define UV3H_NODE_ID_NODE_ID_MASK                       0x00007fff00000000UL
2909 #define UV3H_NODE_ID_ROUTER_SELECT_MASK                 0x0001000000000000UL
2910 #define UV3H_NODE_ID_RESERVED_2_MASK                    0x0002000000000000UL
2911 #define UV3H_NODE_ID_NODES_PER_BIT_MASK                 0x01fc000000000000UL
2912 #define UV3H_NODE_ID_NI_PORT_MASK                       0x3e00000000000000UL
2913 
2914 #define UV4H_NODE_ID_FORCE1_SHFT                        0
2915 #define UV4H_NODE_ID_MANUFACTURER_SHFT                  1
2916 #define UV4H_NODE_ID_PART_NUMBER_SHFT                   12
2917 #define UV4H_NODE_ID_REVISION_SHFT                      28
2918 #define UV4H_NODE_ID_NODE_ID_SHFT                       32
2919 #define UV4H_NODE_ID_ROUTER_SELECT_SHFT                 48
2920 #define UV4H_NODE_ID_RESERVED_2_SHFT                    49
2921 #define UV4H_NODE_ID_NODES_PER_BIT_SHFT                 50
2922 #define UV4H_NODE_ID_NI_PORT_SHFT                       57
2923 #define UV4H_NODE_ID_FORCE1_MASK                        0x0000000000000001UL
2924 #define UV4H_NODE_ID_MANUFACTURER_MASK                  0x0000000000000ffeUL
2925 #define UV4H_NODE_ID_PART_NUMBER_MASK                   0x000000000ffff000UL
2926 #define UV4H_NODE_ID_REVISION_MASK                      0x00000000f0000000UL
2927 #define UV4H_NODE_ID_NODE_ID_MASK                       0x00007fff00000000UL
2928 #define UV4H_NODE_ID_ROUTER_SELECT_MASK                 0x0001000000000000UL
2929 #define UV4H_NODE_ID_RESERVED_2_MASK                    0x0002000000000000UL
2930 #define UV4H_NODE_ID_NODES_PER_BIT_MASK                 0x01fc000000000000UL
2931 #define UV4H_NODE_ID_NI_PORT_MASK                       0x3e00000000000000UL
2932 
2933 
2934 union uvh_node_id_u {
2935         unsigned long   v;
2936         struct uvh_node_id_s {
2937                 unsigned long   force1:1;                       /* RO */
2938                 unsigned long   manufacturer:11;                /* RO */
2939                 unsigned long   part_number:16;                 /* RO */
2940                 unsigned long   revision:4;                     /* RO */
2941                 unsigned long   node_id:15;                     /* RW */
2942                 unsigned long   rsvd_47_63:17;
2943         } s;
2944         struct uv1h_node_id_s {
2945                 unsigned long   force1:1;                       /* RO */
2946                 unsigned long   manufacturer:11;                /* RO */
2947                 unsigned long   part_number:16;                 /* RO */
2948                 unsigned long   revision:4;                     /* RO */
2949                 unsigned long   node_id:15;                     /* RW */
2950                 unsigned long   rsvd_47:1;
2951                 unsigned long   nodes_per_bit:7;                /* RW */
2952                 unsigned long   rsvd_55:1;
2953                 unsigned long   ni_port:4;                      /* RO */
2954                 unsigned long   rsvd_60_63:4;
2955         } s1;
2956         struct uvxh_node_id_s {
2957                 unsigned long   force1:1;                       /* RO */
2958                 unsigned long   manufacturer:11;                /* RO */
2959                 unsigned long   part_number:16;                 /* RO */
2960                 unsigned long   revision:4;                     /* RO */
2961                 unsigned long   node_id:15;                     /* RW */
2962                 unsigned long   rsvd_47_49:3;
2963                 unsigned long   nodes_per_bit:7;                /* RO */
2964                 unsigned long   ni_port:5;                      /* RO */
2965                 unsigned long   rsvd_62_63:2;
2966         } sx;
2967         struct uv2h_node_id_s {
2968                 unsigned long   force1:1;                       /* RO */
2969                 unsigned long   manufacturer:11;                /* RO */
2970                 unsigned long   part_number:16;                 /* RO */
2971                 unsigned long   revision:4;                     /* RO */
2972                 unsigned long   node_id:15;                     /* RW */
2973                 unsigned long   rsvd_47_49:3;
2974                 unsigned long   nodes_per_bit:7;                /* RO */
2975                 unsigned long   ni_port:5;                      /* RO */
2976                 unsigned long   rsvd_62_63:2;
2977         } s2;
2978         struct uv3h_node_id_s {
2979                 unsigned long   force1:1;                       /* RO */
2980                 unsigned long   manufacturer:11;                /* RO */
2981                 unsigned long   part_number:16;                 /* RO */
2982                 unsigned long   revision:4;                     /* RO */
2983                 unsigned long   node_id:15;                     /* RW */
2984                 unsigned long   rsvd_47:1;
2985                 unsigned long   router_select:1;                /* RO */
2986                 unsigned long   rsvd_49:1;
2987                 unsigned long   nodes_per_bit:7;                /* RO */
2988                 unsigned long   ni_port:5;                      /* RO */
2989                 unsigned long   rsvd_62_63:2;
2990         } s3;
2991         struct uv4h_node_id_s {
2992                 unsigned long   force1:1;                       /* RO */
2993                 unsigned long   manufacturer:11;                /* RO */
2994                 unsigned long   part_number:16;                 /* RO */
2995                 unsigned long   revision:4;                     /* RO */
2996                 unsigned long   node_id:15;                     /* RW */
2997                 unsigned long   rsvd_47:1;
2998                 unsigned long   router_select:1;                /* RO */
2999                 unsigned long   rsvd_49:1;
3000                 unsigned long   nodes_per_bit:7;                /* RO */
3001                 unsigned long   ni_port:5;                      /* RO */
3002                 unsigned long   rsvd_62_63:2;
3003         } s4;
3004 };
3005 
3006 /* ========================================================================= */
3007 /*                          UVH_NODE_PRESENT_TABLE                           */
3008 /* ========================================================================= */
3009 #define UVH_NODE_PRESENT_TABLE 0x1400UL
3010 
3011 #define UV1H_NODE_PRESENT_TABLE_DEPTH 16
3012 #define UV2H_NODE_PRESENT_TABLE_DEPTH 16
3013 #define UV3H_NODE_PRESENT_TABLE_DEPTH 16
3014 #define UV4H_NODE_PRESENT_TABLE_DEPTH 4
3015 #define UVH_NODE_PRESENT_TABLE_DEPTH (                                  \
3016         is_uv1_hub() ? UV1H_NODE_PRESENT_TABLE_DEPTH :                  \
3017         is_uv2_hub() ? UV2H_NODE_PRESENT_TABLE_DEPTH :                  \
3018         is_uv3_hub() ? UV3H_NODE_PRESENT_TABLE_DEPTH :                  \
3019         /*is_uv4_hub*/ UV4H_NODE_PRESENT_TABLE_DEPTH)
3020 
3021 #define UVH_NODE_PRESENT_TABLE_NODES_SHFT               0
3022 #define UVH_NODE_PRESENT_TABLE_NODES_MASK               0xffffffffffffffffUL
3023 
3024 
3025 union uvh_node_present_table_u {
3026         unsigned long   v;
3027         struct uvh_node_present_table_s {
3028                 unsigned long   nodes:64;                       /* RW */
3029         } s;
3030 };
3031 
3032 /* ========================================================================= */
3033 /*                 UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR                  */
3034 /* ========================================================================= */
3035 #define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR 0x16000c8UL
3036 #define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR 0x16000c8UL
3037 #define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR 0x16000c8UL
3038 #define UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR 0x4800c8UL
3039 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR (                      \
3040         is_uv1_hub() ? UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR :      \
3041         is_uv2_hub() ? UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR :      \
3042         is_uv3_hub() ? UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR :      \
3043         /*is_uv4_hub*/ UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR)
3044 
3045 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_BASE_SHFT 24
3046 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_M_ALIAS_SHFT 48
3047 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_ENABLE_SHFT 63
3048 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_BASE_MASK 0x00000000ff000000UL
3049 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_M_ALIAS_MASK 0x001f000000000000UL
3050 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_ENABLE_MASK 0x8000000000000000UL
3051 
3052 #define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_BASE_SHFT 24
3053 #define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_M_ALIAS_SHFT 48
3054 #define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_ENABLE_SHFT 63
3055 #define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_BASE_MASK 0x00000000ff000000UL
3056 #define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_M_ALIAS_MASK 0x001f000000000000UL
3057 #define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_ENABLE_MASK 0x8000000000000000UL
3058 
3059 #define UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_BASE_SHFT 24
3060 #define UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_M_ALIAS_SHFT 48
3061 #define UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_ENABLE_SHFT 63
3062 #define UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_BASE_MASK 0x00000000ff000000UL
3063 #define UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_M_ALIAS_MASK 0x001f000000000000UL
3064 #define UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_ENABLE_MASK 0x8000000000000000UL
3065 
3066 #define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_BASE_SHFT 24
3067 #define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_M_ALIAS_SHFT 48
3068 #define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_ENABLE_SHFT 63
3069 #define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_BASE_MASK 0x00000000ff000000UL
3070 #define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_M_ALIAS_MASK 0x001f000000000000UL
3071 #define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_ENABLE_MASK 0x8000000000000000UL
3072 
3073 #define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_BASE_SHFT 24
3074 #define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_M_ALIAS_SHFT 48
3075 #define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_ENABLE_SHFT 63
3076 #define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_BASE_MASK 0x00000000ff000000UL
3077 #define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_M_ALIAS_MASK 0x001f000000000000UL
3078 #define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_ENABLE_MASK 0x8000000000000000UL
3079 
3080 #define UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_BASE_SHFT 24
3081 #define UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_M_ALIAS_SHFT 48
3082 #define UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_ENABLE_SHFT 63
3083 #define UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_BASE_MASK 0x00000000ff000000UL
3084 #define UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_M_ALIAS_MASK 0x001f000000000000UL
3085 #define UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_ENABLE_MASK 0x8000000000000000UL
3086 
3087 
3088 union uvh_rh_gam_alias210_overlay_config_0_mmr_u {
3089         unsigned long   v;
3090         struct uvh_rh_gam_alias210_overlay_config_0_mmr_s {
3091                 unsigned long   rsvd_0_23:24;
3092                 unsigned long   base:8;                         /* RW */
3093                 unsigned long   rsvd_32_47:16;
3094                 unsigned long   m_alias:5;                      /* RW */
3095                 unsigned long   rsvd_53_62:10;
3096                 unsigned long   enable:1;                       /* RW */
3097         } s;
3098         struct uv1h_rh_gam_alias210_overlay_config_0_mmr_s {
3099                 unsigned long   rsvd_0_23:24;
3100                 unsigned long   base:8;                         /* RW */
3101                 unsigned long   rsvd_32_47:16;
3102                 unsigned long   m_alias:5;                      /* RW */
3103                 unsigned long   rsvd_53_62:10;
3104                 unsigned long   enable:1;                       /* RW */
3105         } s1;
3106         struct uvxh_rh_gam_alias210_overlay_config_0_mmr_s {
3107                 unsigned long   rsvd_0_23:24;
3108                 unsigned long   base:8;                         /* RW */
3109                 unsigned long   rsvd_32_47:16;
3110                 unsigned long   m_alias:5;                      /* RW */
3111                 unsigned long   rsvd_53_62:10;
3112                 unsigned long   enable:1;                       /* RW */
3113         } sx;
3114         struct uv2h_rh_gam_alias210_overlay_config_0_mmr_s {
3115                 unsigned long   rsvd_0_23:24;
3116                 unsigned long   base:8;                         /* RW */
3117                 unsigned long   rsvd_32_47:16;
3118                 unsigned long   m_alias:5;                      /* RW */
3119                 unsigned long   rsvd_53_62:10;
3120                 unsigned long   enable:1;                       /* RW */
3121         } s2;
3122         struct uv3h_rh_gam_alias210_overlay_config_0_mmr_s {
3123                 unsigned long   rsvd_0_23:24;
3124                 unsigned long   base:8;                         /* RW */
3125                 unsigned long   rsvd_32_47:16;
3126                 unsigned long   m_alias:5;                      /* RW */
3127                 unsigned long   rsvd_53_62:10;
3128                 unsigned long   enable:1;                       /* RW */
3129         } s3;
3130         struct uv4h_rh_gam_alias210_overlay_config_0_mmr_s {
3131                 unsigned long   rsvd_0_23:24;
3132                 unsigned long   base:8;                         /* RW */
3133                 unsigned long   rsvd_32_47:16;
3134                 unsigned long   m_alias:5;                      /* RW */
3135                 unsigned long   rsvd_53_62:10;
3136                 unsigned long   enable:1;                       /* RW */
3137         } s4;
3138 };
3139 
3140 /* ========================================================================= */
3141 /*                 UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR                  */
3142 /* ========================================================================= */
3143 #define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR 0x16000d8UL
3144 #define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR 0x16000d8UL
3145 #define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR 0x16000d8UL
3146 #define UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR 0x4800d8UL
3147 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR (                      \
3148         is_uv1_hub() ? UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR :      \
3149         is_uv2_hub() ? UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR :      \
3150         is_uv3_hub() ? UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR :      \
3151         /*is_uv4_hub*/ UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR)
3152 
3153 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_BASE_SHFT 24
3154 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_M_ALIAS_SHFT 48
3155 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_ENABLE_SHFT 63
3156 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_BASE_MASK 0x00000000ff000000UL
3157 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_M_ALIAS_MASK 0x001f000000000000UL
3158 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_ENABLE_MASK 0x8000000000000000UL
3159 
3160 #define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_BASE_SHFT 24
3161 #define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_M_ALIAS_SHFT 48
3162 #define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_ENABLE_SHFT 63
3163 #define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_BASE_MASK 0x00000000ff000000UL
3164 #define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_M_ALIAS_MASK 0x001f000000000000UL
3165 #define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_ENABLE_MASK 0x8000000000000000UL
3166 
3167 #define UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_BASE_SHFT 24
3168 #define UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_M_ALIAS_SHFT 48
3169 #define UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_ENABLE_SHFT 63
3170 #define UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_BASE_MASK 0x00000000ff000000UL
3171 #define UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_M_ALIAS_MASK 0x001f000000000000UL
3172 #define UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_ENABLE_MASK 0x8000000000000000UL
3173 
3174 #define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_BASE_SHFT 24
3175 #define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_M_ALIAS_SHFT 48
3176 #define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_ENABLE_SHFT 63
3177 #define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_BASE_MASK 0x00000000ff000000UL
3178 #define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_M_ALIAS_MASK 0x001f000000000000UL
3179 #define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_ENABLE_MASK 0x8000000000000000UL
3180 
3181 #define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_BASE_SHFT 24
3182 #define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_M_ALIAS_SHFT 48
3183 #define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_ENABLE_SHFT 63
3184 #define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_BASE_MASK 0x00000000ff000000UL
3185 #define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_M_ALIAS_MASK 0x001f000000000000UL
3186 #define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_ENABLE_MASK 0x8000000000000000UL
3187 
3188 #define UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_BASE_SHFT 24
3189 #define UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_M_ALIAS_SHFT 48
3190 #define UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_ENABLE_SHFT 63
3191 #define UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_BASE_MASK 0x00000000ff000000UL
3192 #define UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_M_ALIAS_MASK 0x001f000000000000UL
3193 #define UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_ENABLE_MASK 0x8000000000000000UL
3194 
3195 
3196 union uvh_rh_gam_alias210_overlay_config_1_mmr_u {
3197         unsigned long   v;
3198         struct uvh_rh_gam_alias210_overlay_config_1_mmr_s {
3199                 unsigned long   rsvd_0_23:24;
3200                 unsigned long   base:8;                         /* RW */
3201                 unsigned long   rsvd_32_47:16;
3202                 unsigned long   m_alias:5;                      /* RW */
3203                 unsigned long   rsvd_53_62:10;
3204                 unsigned long   enable:1;                       /* RW */
3205         } s;
3206         struct uv1h_rh_gam_alias210_overlay_config_1_mmr_s {
3207                 unsigned long   rsvd_0_23:24;
3208                 unsigned long   base:8;                         /* RW */
3209                 unsigned long   rsvd_32_47:16;
3210                 unsigned long   m_alias:5;                      /* RW */
3211                 unsigned long   rsvd_53_62:10;
3212                 unsigned long   enable:1;                       /* RW */
3213         } s1;
3214         struct uvxh_rh_gam_alias210_overlay_config_1_mmr_s {
3215                 unsigned long   rsvd_0_23:24;
3216                 unsigned long   base:8;                         /* RW */
3217                 unsigned long   rsvd_32_47:16;
3218                 unsigned long   m_alias:5;                      /* RW */
3219                 unsigned long   rsvd_53_62:10;
3220                 unsigned long   enable:1;                       /* RW */
3221         } sx;
3222         struct uv2h_rh_gam_alias210_overlay_config_1_mmr_s {
3223                 unsigned long   rsvd_0_23:24;
3224                 unsigned long   base:8;                         /* RW */
3225                 unsigned long   rsvd_32_47:16;
3226                 unsigned long   m_alias:5;                      /* RW */
3227                 unsigned long   rsvd_53_62:10;
3228                 unsigned long   enable:1;                       /* RW */
3229         } s2;
3230         struct uv3h_rh_gam_alias210_overlay_config_1_mmr_s {
3231                 unsigned long   rsvd_0_23:24;
3232                 unsigned long   base:8;                         /* RW */
3233                 unsigned long   rsvd_32_47:16;
3234                 unsigned long   m_alias:5;                      /* RW */
3235                 unsigned long   rsvd_53_62:10;
3236                 unsigned long   enable:1;                       /* RW */
3237         } s3;
3238         struct uv4h_rh_gam_alias210_overlay_config_1_mmr_s {
3239                 unsigned long   rsvd_0_23:24;
3240                 unsigned long   base:8;                         /* RW */
3241                 unsigned long   rsvd_32_47:16;
3242                 unsigned long   m_alias:5;                      /* RW */
3243                 unsigned long   rsvd_53_62:10;
3244                 unsigned long   enable:1;                       /* RW */
3245         } s4;
3246 };
3247 
3248 /* ========================================================================= */
3249 /*                 UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR                  */
3250 /* ========================================================================= */
3251 #define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR 0x16000e8UL
3252 #define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR 0x16000e8UL
3253 #define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR 0x16000e8UL
3254 #define UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR 0x4800e8UL
3255 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR (                      \
3256         is_uv1_hub() ? UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR :      \
3257         is_uv2_hub() ? UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR :      \
3258         is_uv3_hub() ? UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR :      \
3259         /*is_uv4_hub*/ UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR)
3260 
3261 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_BASE_SHFT 24
3262 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_M_ALIAS_SHFT 48
3263 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_ENABLE_SHFT 63
3264 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_BASE_MASK 0x00000000ff000000UL
3265 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_M_ALIAS_MASK 0x001f000000000000UL
3266 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_ENABLE_MASK 0x8000000000000000UL
3267 
3268 #define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_BASE_SHFT 24
3269 #define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_M_ALIAS_SHFT 48
3270 #define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_ENABLE_SHFT 63
3271 #define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_BASE_MASK 0x00000000ff000000UL
3272 #define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_M_ALIAS_MASK 0x001f000000000000UL
3273 #define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_ENABLE_MASK 0x8000000000000000UL
3274 
3275 #define UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_BASE_SHFT 24
3276 #define UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_M_ALIAS_SHFT 48
3277 #define UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_ENABLE_SHFT 63
3278 #define UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_BASE_MASK 0x00000000ff000000UL
3279 #define UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_M_ALIAS_MASK 0x001f000000000000UL
3280 #define UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_ENABLE_MASK 0x8000000000000000UL
3281 
3282 #define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_BASE_SHFT 24
3283 #define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_M_ALIAS_SHFT 48
3284 #define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_ENABLE_SHFT 63
3285 #define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_BASE_MASK 0x00000000ff000000UL
3286 #define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_M_ALIAS_MASK 0x001f000000000000UL
3287 #define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_ENABLE_MASK 0x8000000000000000UL
3288 
3289 #define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_BASE_SHFT 24
3290 #define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_M_ALIAS_SHFT 48
3291 #define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_ENABLE_SHFT 63
3292 #define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_BASE_MASK 0x00000000ff000000UL
3293 #define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_M_ALIAS_MASK 0x001f000000000000UL
3294 #define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_ENABLE_MASK 0x8000000000000000UL
3295 
3296 #define UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_BASE_SHFT 24
3297 #define UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_M_ALIAS_SHFT 48
3298 #define UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_ENABLE_SHFT 63
3299 #define UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_BASE_MASK 0x00000000ff000000UL
3300 #define UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_M_ALIAS_MASK 0x001f000000000000UL
3301 #define UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_ENABLE_MASK 0x8000000000000000UL
3302 
3303 
3304 union uvh_rh_gam_alias210_overlay_config_2_mmr_u {
3305         unsigned long   v;
3306         struct uvh_rh_gam_alias210_overlay_config_2_mmr_s {
3307                 unsigned long   rsvd_0_23:24;
3308                 unsigned long   base:8;                         /* RW */
3309                 unsigned long   rsvd_32_47:16;
3310                 unsigned long   m_alias:5;                      /* RW */
3311                 unsigned long   rsvd_53_62:10;
3312                 unsigned long   enable:1;                       /* RW */
3313         } s;
3314         struct uv1h_rh_gam_alias210_overlay_config_2_mmr_s {
3315                 unsigned long   rsvd_0_23:24;
3316                 unsigned long   base:8;                         /* RW */
3317                 unsigned long   rsvd_32_47:16;
3318                 unsigned long   m_alias:5;                      /* RW */
3319                 unsigned long   rsvd_53_62:10;
3320                 unsigned long   enable:1;                       /* RW */
3321         } s1;
3322         struct uvxh_rh_gam_alias210_overlay_config_2_mmr_s {
3323                 unsigned long   rsvd_0_23:24;
3324                 unsigned long   base:8;                         /* RW */
3325                 unsigned long   rsvd_32_47:16;
3326                 unsigned long   m_alias:5;                      /* RW */
3327                 unsigned long   rsvd_53_62:10;
3328                 unsigned long   enable:1;                       /* RW */
3329         } sx;
3330         struct uv2h_rh_gam_alias210_overlay_config_2_mmr_s {
3331                 unsigned long   rsvd_0_23:24;
3332                 unsigned long   base:8;                         /* RW */
3333                 unsigned long   rsvd_32_47:16;
3334                 unsigned long   m_alias:5;                      /* RW */
3335                 unsigned long   rsvd_53_62:10;
3336                 unsigned long   enable:1;                       /* RW */
3337         } s2;
3338         struct uv3h_rh_gam_alias210_overlay_config_2_mmr_s {
3339                 unsigned long   rsvd_0_23:24;
3340                 unsigned long   base:8;                         /* RW */
3341                 unsigned long   rsvd_32_47:16;
3342                 unsigned long   m_alias:5;                      /* RW */
3343                 unsigned long   rsvd_53_62:10;
3344                 unsigned long   enable:1;                       /* RW */
3345         } s3;
3346         struct uv4h_rh_gam_alias210_overlay_config_2_mmr_s {
3347                 unsigned long   rsvd_0_23:24;
3348                 unsigned long   base:8;                         /* RW */
3349                 unsigned long   rsvd_32_47:16;
3350                 unsigned long   m_alias:5;                      /* RW */
3351                 unsigned long   rsvd_53_62:10;
3352                 unsigned long   enable:1;                       /* RW */
3353         } s4;
3354 };
3355 
3356 /* ========================================================================= */
3357 /*                UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR                  */
3358 /* ========================================================================= */
3359 #define UV1H_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR 0x16000d0UL
3360 #define UV2H_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR 0x16000d0UL
3361 #define UV3H_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR 0x16000d0UL
3362 #define UV4H_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR 0x4800d0UL
3363 #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR (                     \
3364         is_uv1_hub() ? UV1H_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR :     \
3365         is_uv2_hub() ? UV2H_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR :     \
3366         is_uv3_hub() ? UV3H_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR :     \
3367         /*is_uv4_hub*/ UV4H_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR)
3368 
3369 #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT 24
3370 #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_MASK 0x00003fffff000000UL
3371 
3372 #define UV1H_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT 24
3373 #define UV1H_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_MASK 0x00003fffff000000UL
3374 
3375 #define UVXH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT 24
3376 #define UVXH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_MASK 0x00003fffff000000UL
3377 
3378 #define UV2H_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT 24
3379 #define UV2H_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_MASK 0x00003fffff000000UL
3380 
3381 #define UV3H_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT 24
3382 #define UV3H_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_MASK 0x00003fffff000000UL
3383 
3384 #define UV4H_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT 24
3385 #define UV4H_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_MASK 0x00003fffff000000UL
3386 
3387 
3388 union uvh_rh_gam_alias210_redirect_config_0_mmr_u {
3389         unsigned long   v;
3390         struct uvh_rh_gam_alias210_redirect_config_0_mmr_s {
3391                 unsigned long   rsvd_0_23:24;
3392                 unsigned long   dest_base:22;                   /* RW */
3393                 unsigned long   rsvd_46_63:18;
3394         } s;
3395         struct uv1h_rh_gam_alias210_redirect_config_0_mmr_s {
3396                 unsigned long   rsvd_0_23:24;
3397                 unsigned long   dest_base:22;                   /* RW */
3398                 unsigned long   rsvd_46_63:18;
3399         } s1;
3400         struct uvxh_rh_gam_alias210_redirect_config_0_mmr_s {
3401                 unsigned long   rsvd_0_23:24;
3402                 unsigned long   dest_base:22;                   /* RW */
3403                 unsigned long   rsvd_46_63:18;
3404         } sx;
3405         struct uv2h_rh_gam_alias210_redirect_config_0_mmr_s {
3406                 unsigned long   rsvd_0_23:24;
3407                 unsigned long   dest_base:22;                   /* RW */
3408                 unsigned long   rsvd_46_63:18;
3409         } s2;
3410         struct uv3h_rh_gam_alias210_redirect_config_0_mmr_s {
3411                 unsigned long   rsvd_0_23:24;
3412                 unsigned long   dest_base:22;                   /* RW */
3413                 unsigned long   rsvd_46_63:18;
3414         } s3;
3415         struct uv4h_rh_gam_alias210_redirect_config_0_mmr_s {
3416                 unsigned long   rsvd_0_23:24;
3417                 unsigned long   dest_base:22;                   /* RW */
3418                 unsigned long   rsvd_46_63:18;
3419         } s4;
3420 };
3421 
3422 /* ========================================================================= */
3423 /*                UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR                  */
3424 /* ========================================================================= */
3425 #define UV1H_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR 0x16000e0UL
3426 #define UV2H_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR 0x16000e0UL
3427 #define UV3H_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR 0x16000e0UL
3428 #define UV4H_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR 0x4800e0UL
3429 #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR (                     \
3430         is_uv1_hub() ? UV1H_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR :     \
3431         is_uv2_hub() ? UV2H_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR :     \
3432         is_uv3_hub() ? UV3H_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR :     \
3433         /*is_uv4_hub*/ UV4H_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR)
3434 
3435 #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_SHFT 24
3436 #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_MASK 0x00003fffff000000UL
3437 
3438 #define UV1H_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_SHFT 24
3439 #define UV1H_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_MASK 0x00003fffff000000UL
3440 
3441 #define UVXH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_SHFT 24
3442 #define UVXH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_MASK 0x00003fffff000000UL
3443 
3444 #define UV2H_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_SHFT 24
3445 #define UV2H_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_MASK 0x00003fffff000000UL
3446 
3447 #define UV3H_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_SHFT 24
3448 #define UV3H_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_MASK 0x00003fffff000000UL
3449 
3450 #define UV4H_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_SHFT 24
3451 #define UV4H_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_MASK 0x00003fffff000000UL
3452 
3453 
3454 union uvh_rh_gam_alias210_redirect_config_1_mmr_u {
3455         unsigned long   v;
3456         struct uvh_rh_gam_alias210_redirect_config_1_mmr_s {
3457                 unsigned long   rsvd_0_23:24;
3458                 unsigned long   dest_base:22;                   /* RW */
3459                 unsigned long   rsvd_46_63:18;
3460         } s;
3461         struct uv1h_rh_gam_alias210_redirect_config_1_mmr_s {
3462                 unsigned long   rsvd_0_23:24;
3463                 unsigned long   dest_base:22;                   /* RW */
3464                 unsigned long   rsvd_46_63:18;
3465         } s1;
3466         struct uvxh_rh_gam_alias210_redirect_config_1_mmr_s {
3467                 unsigned long   rsvd_0_23:24;
3468                 unsigned long   dest_base:22;                   /* RW */
3469                 unsigned long   rsvd_46_63:18;
3470         } sx;
3471         struct uv2h_rh_gam_alias210_redirect_config_1_mmr_s {
3472                 unsigned long   rsvd_0_23:24;
3473                 unsigned long   dest_base:22;                   /* RW */
3474                 unsigned long   rsvd_46_63:18;
3475         } s2;
3476         struct uv3h_rh_gam_alias210_redirect_config_1_mmr_s {
3477                 unsigned long   rsvd_0_23:24;
3478                 unsigned long   dest_base:22;                   /* RW */
3479                 unsigned long   rsvd_46_63:18;
3480         } s3;
3481         struct uv4h_rh_gam_alias210_redirect_config_1_mmr_s {
3482                 unsigned long   rsvd_0_23:24;
3483                 unsigned long   dest_base:22;                   /* RW */
3484                 unsigned long   rsvd_46_63:18;
3485         } s4;
3486 };
3487 
3488 /* ========================================================================= */
3489 /*                UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR                  */
3490 /* ========================================================================= */
3491 #define UV1H_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR 0x16000f0UL
3492 #define UV2H_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR 0x16000f0UL
3493 #define UV3H_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR 0x16000f0UL
3494 #define UV4H_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR 0x4800f0UL
3495 #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR (                     \
3496         is_uv1_hub() ? UV1H_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR :     \
3497         is_uv2_hub() ? UV2H_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR :     \
3498         is_uv3_hub() ? UV3H_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR :     \
3499         /*is_uv4_hub*/ UV4H_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR)
3500 
3501 #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_SHFT 24
3502 #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_MASK 0x00003fffff000000UL
3503 
3504 #define UV1H_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_SHFT 24
3505 #define UV1H_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_MASK 0x00003fffff000000UL
3506 
3507 #define UVXH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_SHFT 24
3508 #define UVXH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_MASK 0x00003fffff000000UL
3509 
3510 #define UV2H_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_SHFT 24
3511 #define UV2H_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_MASK 0x00003fffff000000UL
3512 
3513 #define UV3H_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_SHFT 24
3514 #define UV3H_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_MASK 0x00003fffff000000UL
3515 
3516 #define UV4H_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_SHFT 24
3517 #define UV4H_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_MASK 0x00003fffff000000UL
3518 
3519 
3520 union uvh_rh_gam_alias210_redirect_config_2_mmr_u {
3521         unsigned long   v;
3522         struct uvh_rh_gam_alias210_redirect_config_2_mmr_s {
3523                 unsigned long   rsvd_0_23:24;
3524                 unsigned long   dest_base:22;                   /* RW */
3525                 unsigned long   rsvd_46_63:18;
3526         } s;
3527         struct uv1h_rh_gam_alias210_redirect_config_2_mmr_s {
3528                 unsigned long   rsvd_0_23:24;
3529                 unsigned long   dest_base:22;                   /* RW */
3530                 unsigned long   rsvd_46_63:18;
3531         } s1;
3532         struct uvxh_rh_gam_alias210_redirect_config_2_mmr_s {
3533                 unsigned long   rsvd_0_23:24;
3534                 unsigned long   dest_base:22;                   /* RW */
3535                 unsigned long   rsvd_46_63:18;
3536         } sx;
3537         struct uv2h_rh_gam_alias210_redirect_config_2_mmr_s {
3538                 unsigned long   rsvd_0_23:24;
3539                 unsigned long   dest_base:22;                   /* RW */
3540                 unsigned long   rsvd_46_63:18;
3541         } s2;
3542         struct uv3h_rh_gam_alias210_redirect_config_2_mmr_s {
3543                 unsigned long   rsvd_0_23:24;
3544                 unsigned long   dest_base:22;                   /* RW */
3545                 unsigned long   rsvd_46_63:18;
3546         } s3;
3547         struct uv4h_rh_gam_alias210_redirect_config_2_mmr_s {
3548                 unsigned long   rsvd_0_23:24;
3549                 unsigned long   dest_base:22;                   /* RW */
3550                 unsigned long   rsvd_46_63:18;
3551         } s4;
3552 };
3553 
3554 /* ========================================================================= */
3555 /*                          UVH_RH_GAM_CONFIG_MMR                            */
3556 /* ========================================================================= */
3557 #define UV1H_RH_GAM_CONFIG_MMR 0x1600000UL
3558 #define UV2H_RH_GAM_CONFIG_MMR 0x1600000UL
3559 #define UV3H_RH_GAM_CONFIG_MMR 0x1600000UL
3560 #define UV4H_RH_GAM_CONFIG_MMR 0x480000UL
3561 #define UVH_RH_GAM_CONFIG_MMR (                                         \
3562         is_uv1_hub() ? UV1H_RH_GAM_CONFIG_MMR :                         \
3563         is_uv2_hub() ? UV2H_RH_GAM_CONFIG_MMR :                         \
3564         is_uv3_hub() ? UV3H_RH_GAM_CONFIG_MMR :                         \
3565         /*is_uv4_hub*/ UV4H_RH_GAM_CONFIG_MMR)
3566 
3567 #define UVH_RH_GAM_CONFIG_MMR_N_SKT_SHFT                6
3568 #define UVH_RH_GAM_CONFIG_MMR_N_SKT_MASK                0x00000000000003c0UL
3569 
3570 #define UV1H_RH_GAM_CONFIG_MMR_M_SKT_SHFT               0
3571 #define UV1H_RH_GAM_CONFIG_MMR_N_SKT_SHFT               6
3572 #define UV1H_RH_GAM_CONFIG_MMR_MMIOL_CFG_SHFT           12
3573 #define UV1H_RH_GAM_CONFIG_MMR_M_SKT_MASK               0x000000000000003fUL
3574 #define UV1H_RH_GAM_CONFIG_MMR_N_SKT_MASK               0x00000000000003c0UL
3575 #define UV1H_RH_GAM_CONFIG_MMR_MMIOL_CFG_MASK           0x0000000000001000UL
3576 
3577 #define UVXH_RH_GAM_CONFIG_MMR_N_SKT_SHFT               6
3578 #define UVXH_RH_GAM_CONFIG_MMR_N_SKT_MASK               0x00000000000003c0UL
3579 
3580 #define UV2H_RH_GAM_CONFIG_MMR_M_SKT_SHFT               0
3581 #define UV2H_RH_GAM_CONFIG_MMR_N_SKT_SHFT               6
3582 #define UV2H_RH_GAM_CONFIG_MMR_M_SKT_MASK               0x000000000000003fUL
3583 #define UV2H_RH_GAM_CONFIG_MMR_N_SKT_MASK               0x00000000000003c0UL
3584 
3585 #define UV3H_RH_GAM_CONFIG_MMR_M_SKT_SHFT               0
3586 #define UV3H_RH_GAM_CONFIG_MMR_N_SKT_SHFT               6
3587 #define UV3H_RH_GAM_CONFIG_MMR_M_SKT_MASK               0x000000000000003fUL
3588 #define UV3H_RH_GAM_CONFIG_MMR_N_SKT_MASK               0x00000000000003c0UL
3589 
3590 #define UV4H_RH_GAM_CONFIG_MMR_N_SKT_SHFT               6
3591 #define UV4H_RH_GAM_CONFIG_MMR_N_SKT_MASK               0x00000000000003c0UL
3592 
3593 
3594 union uvh_rh_gam_config_mmr_u {
3595         unsigned long   v;
3596         struct uvh_rh_gam_config_mmr_s {
3597                 unsigned long   rsvd_0_5:6;
3598                 unsigned long   n_skt:4;                        /* RW */
3599                 unsigned long   rsvd_10_63:54;
3600         } s;
3601         struct uv1h_rh_gam_config_mmr_s {
3602                 unsigned long   m_skt:6;                        /* RW */
3603                 unsigned long   n_skt:4;                        /* RW */
3604                 unsigned long   rsvd_10_11:2;
3605                 unsigned long   mmiol_cfg:1;                    /* RW */
3606                 unsigned long   rsvd_13_63:51;
3607         } s1;
3608         struct uvxh_rh_gam_config_mmr_s {
3609                 unsigned long   rsvd_0_5:6;
3610                 unsigned long   n_skt:4;                        /* RW */
3611                 unsigned long   rsvd_10_63:54;
3612         } sx;
3613         struct uv2h_rh_gam_config_mmr_s {
3614                 unsigned long   m_skt:6;                        /* RW */
3615                 unsigned long   n_skt:4;                        /* RW */
3616                 unsigned long   rsvd_10_63:54;
3617         } s2;
3618         struct uv3h_rh_gam_config_mmr_s {
3619                 unsigned long   m_skt:6;                        /* RW */
3620                 unsigned long   n_skt:4;                        /* RW */
3621                 unsigned long   rsvd_10_63:54;
3622         } s3;
3623         struct uv4h_rh_gam_config_mmr_s {
3624                 unsigned long   rsvd_0_5:6;
3625                 unsigned long   n_skt:4;                        /* RW */
3626                 unsigned long   rsvd_10_63:54;
3627         } s4;
3628 };
3629 
3630 /* ========================================================================= */
3631 /*                    UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR                      */
3632 /* ========================================================================= */
3633 #define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR 0x1600010UL
3634 #define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR 0x1600010UL
3635 #define UV3H_RH_GAM_GRU_OVERLAY_CONFIG_MMR 0x1600010UL
3636 #define UV4H_RH_GAM_GRU_OVERLAY_CONFIG_MMR 0x480010UL
3637 #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR (                             \
3638         is_uv1_hub() ? UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR :             \
3639         is_uv2_hub() ? UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR :             \
3640         is_uv3_hub() ? UV3H_RH_GAM_GRU_OVERLAY_CONFIG_MMR :             \
3641         /*is_uv4_hub*/ UV4H_RH_GAM_GRU_OVERLAY_CONFIG_MMR)
3642 
3643 #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_SHFT    52
3644 #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_SHFT   63
3645 #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_MASK    0x00f0000000000000UL
3646 #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_MASK   0x8000000000000000UL
3647 
3648 #define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT    28
3649 #define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_GR4_SHFT     48
3650 #define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_SHFT   52
3651 #define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_SHFT  63
3652 #define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK    0x00003ffff0000000UL
3653 #define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_GR4_MASK     0x0001000000000000UL
3654 #define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_MASK   0x00f0000000000000UL
3655 #define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_MASK  0x8000000000000000UL
3656 
3657 #define UVXH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_SHFT   52
3658 #define UVXH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_SHFT  63
3659 #define UVXH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_MASK   0x00f0000000000000UL
3660 #define UVXH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_MASK  0x8000000000000000UL
3661 
3662 #define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT    28
3663 #define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_SHFT   52
3664 #define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_SHFT  63
3665 #define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK    0x00003ffff0000000UL
3666 #define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_MASK   0x00f0000000000000UL
3667 #define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_MASK  0x8000000000000000UL
3668 
3669 #define UV3H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT    28
3670 #define UV3H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_SHFT   52
3671 #define UV3H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_MODE_SHFT    62
3672 #define UV3H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_SHFT  63
3673 #define UV3H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK    0x00003ffff0000000UL
3674 #define UV3H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_MASK   0x00f0000000000000UL
3675 #define UV3H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_MODE_MASK    0x4000000000000000UL
3676 #define UV3H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_MASK  0x8000000000000000UL
3677 
3678 #define UV4H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT    26
3679 #define UV4H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_SHFT   52
3680 #define UV4H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_SHFT  63
3681 #define UV4H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK    0x00003ffffc000000UL
3682 #define UV4H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_MASK   0x00f0000000000000UL
3683 #define UV4H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_MASK  0x8000000000000000UL
3684 
3685 #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK (                   \
3686         is_uv1_hub() ? UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK :   \
3687         is_uv2_hub() ? UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK :   \
3688         is_uv3_hub() ? UV3H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK :   \
3689         /*is_uv4_hub*/ UV4H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK)
3690 #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT (                   \
3691         is_uv1_hub() ? UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT :   \
3692         is_uv2_hub() ? UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT :   \
3693         is_uv3_hub() ? UV3H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT :   \
3694         /*is_uv4_hub*/ UV4H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT)
3695 
3696 union uvh_rh_gam_gru_overlay_config_mmr_u {
3697         unsigned long   v;
3698         struct uvh_rh_gam_gru_overlay_config_mmr_s {
3699                 unsigned long   rsvd_0_51:52;
3700                 unsigned long   n_gru:4;                        /* RW */
3701                 unsigned long   rsvd_56_62:7;
3702                 unsigned long   enable:1;                       /* RW */
3703         } s;
3704         struct uv1h_rh_gam_gru_overlay_config_mmr_s {
3705                 unsigned long   rsvd_0_27:28;
3706                 unsigned long   base:18;                        /* RW */
3707                 unsigned long   rsvd_46_47:2;
3708                 unsigned long   gr4:1;                          /* RW */
3709                 unsigned long   rsvd_49_51:3;
3710                 unsigned long   n_gru:4;                        /* RW */
3711                 unsigned long   rsvd_56_62:7;
3712                 unsigned long   enable:1;                       /* RW */
3713         } s1;
3714         struct uvxh_rh_gam_gru_overlay_config_mmr_s {
3715                 unsigned long   rsvd_0_45:46;
3716                 unsigned long   rsvd_46_51:6;
3717                 unsigned long   n_gru:4;                        /* RW */
3718                 unsigned long   rsvd_56_62:7;
3719                 unsigned long   enable:1;                       /* RW */
3720         } sx;
3721         struct uv2h_rh_gam_gru_overlay_config_mmr_s {
3722                 unsigned long   rsvd_0_27:28;
3723                 unsigned long   base:18;                        /* RW */
3724                 unsigned long   rsvd_46_51:6;
3725                 unsigned long   n_gru:4;                        /* RW */
3726                 unsigned long   rsvd_56_62:7;
3727                 unsigned long   enable:1;                       /* RW */
3728         } s2;
3729         struct uv3h_rh_gam_gru_overlay_config_mmr_s {
3730                 unsigned long   rsvd_0_27:28;
3731                 unsigned long   base:18;                        /* RW */
3732                 unsigned long   rsvd_46_51:6;
3733                 unsigned long   n_gru:4;                        /* RW */
3734                 unsigned long   rsvd_56_61:6;
3735                 unsigned long   mode:1;                         /* RW */
3736                 unsigned long   enable:1;                       /* RW */
3737         } s3;
3738         struct uv4h_rh_gam_gru_overlay_config_mmr_s {
3739                 unsigned long   rsvd_0_24:25;
3740                 unsigned long   undef_25:1;                     /* Undefined */
3741                 unsigned long   base:20;                        /* RW */
3742                 unsigned long   rsvd_46_51:6;
3743                 unsigned long   n_gru:4;                        /* RW */
3744                 unsigned long   rsvd_56_62:7;
3745                 unsigned long   enable:1;                       /* RW */
3746         } s4;
3747 };
3748 
3749 /* ========================================================================= */
3750 /*                   UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR                    */
3751 /* ========================================================================= */
3752 #define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR uv_undefined("UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR")
3753 #define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR uv_undefined("UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR")
3754 #define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR 0x1603000UL
3755 #define UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR 0x483000UL
3756 #define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR (                          \
3757         is_uv1_hub() ? UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR :          \
3758         is_uv2_hub() ? UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR :          \
3759         is_uv3_hub() ? UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR :          \
3760         /*is_uv4_hub*/ UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR)
3761 
3762 
3763 #define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_BASE_SHFT 26
3764 #define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_M_IO_SHFT 46
3765 #define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_ENABLE_SHFT 63
3766 #define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_BASE_MASK 0x00003ffffc000000UL
3767 #define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_M_IO_MASK 0x000fc00000000000UL
3768 #define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_ENABLE_MASK 0x8000000000000000UL
3769 
3770 #define UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_BASE_SHFT 26
3771 #define UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_M_IO_SHFT 46
3772 #define UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_ENABLE_SHFT 63
3773 #define UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_BASE_MASK 0x00003ffffc000000UL
3774 #define UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_M_IO_MASK 0x000fc00000000000UL
3775 #define UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_ENABLE_MASK 0x8000000000000000UL
3776 
3777 #define UV4AH_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_M_IO_SHFT 52
3778 #define UV4AH_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_BASE_MASK 0x000ffffffc000000UL
3779 #define UV4AH_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_M_IO_MASK 0x03f0000000000000UL
3780 #define UV4AH_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_ENABLE_MASK 0x8000000000000000UL
3781 
3782 #define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_M_IO_SHFT (                \
3783         is_uv3_hub() ? UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_M_IO_SHFT : \
3784         is_uv4a_hub() ? UV4AH_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_M_IO_SHFT : \
3785         /*is_uv4_hub*/ UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_M_IO_SHFT)
3786 
3787 #define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_BASE_MASK (                \
3788         is_uv3_hub() ? UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_BASE_MASK : \
3789         is_uv4a_hub() ? UV4AH_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_BASE_MASK : \
3790         /*is_uv4_hub*/ UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_BASE_MASK)
3791 
3792 #define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_M_IO_MASK (                \
3793         is_uv3_hub() ? UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_M_IO_MASK : \
3794         is_uv4a_hub() ? UV4AH_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_M_IO_MASK : \
3795         /*is_uv4_hub*/ UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_M_IO_MASK)
3796 
3797 #define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_ENABLE_MASK (              \
3798         is_uv3_hub() ? UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_ENABLE_MASK : \
3799         is_uv4a_hub() ? UV4AH_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_ENABLE_MASK : \
3800         /*is_uv4_hub*/ UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_ENABLE_MASK)
3801 
3802 union uvh_rh_gam_mmioh_overlay_config0_mmr_u {
3803         unsigned long   v;
3804         struct uv3h_rh_gam_mmioh_overlay_config0_mmr_s {
3805                 unsigned long   rsvd_0_25:26;
3806                 unsigned long   base:20;                        /* RW */
3807                 unsigned long   m_io:6;                         /* RW */
3808                 unsigned long   n_io:4;
3809                 unsigned long   rsvd_56_62:7;
3810                 unsigned long   enable:1;                       /* RW */
3811         } s3;
3812         struct uv4h_rh_gam_mmioh_overlay_config0_mmr_s {
3813                 unsigned long   rsvd_0_25:26;
3814                 unsigned long   base:20;                        /* RW */
3815                 unsigned long   m_io:6;                         /* RW */
3816                 unsigned long   n_io:4;
3817                 unsigned long   rsvd_56_62:7;
3818                 unsigned long   enable:1;                       /* RW */
3819         } s4;
3820         struct uv4ah_rh_gam_mmioh_overlay_config0_mmr_s {
3821                 unsigned long   rsvd_0_25:26;
3822                 unsigned long   base:26;                        /* RW */
3823                 unsigned long   m_io:6;                         /* RW */
3824                 unsigned long   n_io:4;
3825                 unsigned long   undef_62:1;                     /* Undefined */
3826                 unsigned long   enable:1;                       /* RW */
3827         } s4a;
3828 };
3829 
3830 /* ========================================================================= */
3831 /*                   UVH_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR                    */
3832 /* ========================================================================= */
3833 #define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR uv_undefined("UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR")
3834 #define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR uv_undefined("UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR")
3835 #define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR 0x1603000UL
3836 #define UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR 0x484000UL
3837 #define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR (                          \
3838         is_uv1_hub() ? UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR :          \
3839         is_uv2_hub() ? UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR :          \
3840         is_uv3_hub() ? UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR :          \
3841         /*is_uv4_hub*/ UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR)
3842 
3843 
3844 #define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_BASE_SHFT 26
3845 #define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_M_IO_SHFT 46
3846 #define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_ENABLE_SHFT 63
3847 #define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_BASE_MASK 0x00003ffffc000000UL
3848 #define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_M_IO_MASK 0x000fc00000000000UL
3849 #define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_ENABLE_MASK 0x8000000000000000UL
3850 
3851 #define UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_BASE_SHFT 26
3852 #define UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_M_IO_SHFT 46
3853 #define UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_ENABLE_SHFT 63
3854 #define UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_BASE_MASK 0x00003ffffc000000UL
3855 #define UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_M_IO_MASK 0x000fc00000000000UL
3856 #define UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_ENABLE_MASK 0x8000000000000000UL
3857 
3858 #define UV4AH_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_M_IO_SHFT 52
3859 #define UV4AH_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_BASE_MASK 0x000ffffffc000000UL
3860 #define UV4AH_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_M_IO_MASK 0x03f0000000000000UL
3861 
3862 #define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_M_IO_SHFT (                \
3863         is_uv3_hub() ? UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_M_IO_SHFT : \
3864         is_uv4a_hub() ? UV4AH_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_M_IO_SHFT : \
3865         /*is_uv4_hub*/ UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_M_IO_SHFT)
3866 
3867 #define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_BASE_MASK (                \
3868         is_uv3_hub() ? UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_BASE_MASK : \
3869         is_uv4a_hub() ? UV4AH_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_BASE_MASK : \
3870         /*is_uv4_hub*/ UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_BASE_MASK)
3871 
3872 #define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_M_IO_MASK (                \
3873         is_uv3_hub() ? UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_M_IO_MASK : \
3874         is_uv4a_hub() ? UV4AH_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_M_IO_MASK : \
3875         /*is_uv4_hub*/ UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_M_IO_MASK)
3876 
3877 union uvh_rh_gam_mmioh_overlay_config1_mmr_u {
3878         unsigned long   v;
3879         struct uv3h_rh_gam_mmioh_overlay_config1_mmr_s {
3880                 unsigned long   rsvd_0_25:26;
3881                 unsigned long   base:20;                        /* RW */
3882                 unsigned long   m_io:6;                         /* RW */
3883                 unsigned long   n_io:4;
3884                 unsigned long   rsvd_56_62:7;
3885                 unsigned long   enable:1;                       /* RW */
3886         } s3;
3887         struct uv4h_rh_gam_mmioh_overlay_config1_mmr_s {
3888                 unsigned long   rsvd_0_25:26;
3889                 unsigned long   base:20;                        /* RW */
3890                 unsigned long   m_io:6;                         /* RW */
3891                 unsigned long   n_io:4;
3892                 unsigned long   rsvd_56_62:7;
3893                 unsigned long   enable:1;                       /* RW */
3894         } s4;
3895         struct uv4ah_rh_gam_mmioh_overlay_config1_mmr_s {
3896                 unsigned long   rsvd_0_25:26;
3897                 unsigned long   base:26;                        /* RW */
3898                 unsigned long   m_io:6;                         /* RW */
3899                 unsigned long   n_io:4;
3900                 unsigned long   undef_62:1;                     /* Undefined */
3901                 unsigned long   enable:1;                       /* RW */
3902         } s4a;
3903 };
3904 
3905 /* ========================================================================= */
3906 /*                   UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR                     */
3907 /* ========================================================================= */
3908 #define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR 0x1600030UL
3909 #define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR 0x1600030UL
3910 #define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR uv_undefined("UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR")
3911 #define UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR uv_undefined("UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR")
3912 #define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR (                           \
3913         is_uv1_hub() ? UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR :           \
3914         is_uv2_hub() ? UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR :           \
3915         is_uv3_hub() ? UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR :           \
3916         /*is_uv4_hub*/ UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR)
3917 
3918 
3919 #define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT  30
3920 #define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_M_IO_SHFT  46
3921 #define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_N_IO_SHFT  52
3922 #define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63
3923 #define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_MASK  0x00003fffc0000000UL
3924 #define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_M_IO_MASK  0x000fc00000000000UL
3925 #define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_N_IO_MASK  0x00f0000000000000UL
3926 #define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL
3927 
3928 
3929 #define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT  27
3930 #define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_M_IO_SHFT  46
3931 #define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_N_IO_SHFT  52
3932 #define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63
3933 #define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_MASK  0x00003ffff8000000UL
3934 #define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_M_IO_MASK  0x000fc00000000000UL
3935 #define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_N_IO_MASK  0x00f0000000000000UL
3936 #define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL
3937 
3938 
3939 union uvh_rh_gam_mmioh_overlay_config_mmr_u {
3940         unsigned long   v;
3941         struct uv1h_rh_gam_mmioh_overlay_config_mmr_s {
3942                 unsigned long   rsvd_0_29:30;
3943                 unsigned long   base:16;                        /* RW */
3944                 unsigned long   m_io:6;                         /* RW */
3945                 unsigned long   n_io:4;                         /* RW */
3946                 unsigned long   rsvd_56_62:7;
3947                 unsigned long   enable:1;                       /* RW */
3948         } s1;
3949         struct uv2h_rh_gam_mmioh_overlay_config_mmr_s {
3950                 unsigned long   rsvd_0_26:27;
3951                 unsigned long   base:19;                        /* RW */
3952                 unsigned long   m_io:6;                         /* RW */
3953                 unsigned long   n_io:4;                         /* RW */
3954                 unsigned long   rsvd_56_62:7;
3955                 unsigned long   enable:1;                       /* RW */
3956         } s2;
3957 };
3958 
3959 /* ========================================================================= */
3960 /*                  UVH_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR                    */
3961 /* ========================================================================= */
3962 #define UV1H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR uv_undefined("UV1H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR")
3963 #define UV2H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR uv_undefined("UV2H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR")
3964 #define UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR 0x1603800UL
3965 #define UV4H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR 0x483800UL
3966 #define UVH_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR (                         \
3967         is_uv1_hub() ? UV1H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR :         \
3968         is_uv2_hub() ? UV2H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR :         \
3969         is_uv3_hub() ? UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR :         \
3970         /*is_uv4_hub*/ UV4H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR)
3971 
3972 #define UV1H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_DEPTH uv_undefined("UV1H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_DEPTH")
3973 #define UV2H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_DEPTH uv_undefined("UV2H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_DEPTH")
3974 #define UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_DEPTH 128
3975 #define UV4H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_DEPTH 128
3976 #define UVH_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_DEPTH (                   \
3977         is_uv1_hub() ? UV1H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_DEPTH :   \
3978         is_uv2_hub() ? UV2H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_DEPTH :   \
3979         is_uv3_hub() ? UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_DEPTH :   \
3980         /*is_uv4_hub*/ UV4H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_DEPTH)
3981 
3982 
3983 #define UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_NASID_SHFT 0
3984 #define UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_NASID_MASK 0x0000000000007fffUL
3985 
3986 #define UV4H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_NASID_SHFT 0
3987 #define UV4H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_NASID_MASK 0x0000000000007fffUL
3988 
3989 #define UV4AH_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_NASID_MASK 0x0000000000000fffUL
3990 
3991 #define UVH_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_NASID_MASK (              \
3992         is_uv3_hub() ? UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_NASID_MASK : \
3993         is_uv4a_hub() ? UV4AH_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_NASID_MASK : \
3994         /*is_uv4_hub*/ UV4H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_NASID_MASK)
3995 
3996 union uvh_rh_gam_mmioh_redirect_config0_mmr_u {
3997         unsigned long   v;
3998         struct uv3h_rh_gam_mmioh_redirect_config0_mmr_s {
3999                 unsigned long   nasid:15;                       /* RW */
4000                 unsigned long   rsvd_15_63:49;
4001         } s3;
4002         struct uv4h_rh_gam_mmioh_redirect_config0_mmr_s {
4003                 unsigned long   nasid:15;                       /* RW */
4004                 unsigned long   rsvd_15_63:49;
4005         } s4;
4006         struct uv4ah_rh_gam_mmioh_redirect_config0_mmr_s {
4007                 unsigned long   nasid:12;                       /* RW */
4008                 unsigned long   rsvd_12_63:52;
4009         } s4a;
4010 };
4011 
4012 /* ========================================================================= */
4013 /*                  UVH_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR                    */
4014 /* ========================================================================= */
4015 #define UV1H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR uv_undefined("UV1H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR")
4016 #define UV2H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR uv_undefined("UV2H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR")
4017 #define UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR 0x1604800UL
4018 #define UV4H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR 0x484800UL
4019 #define UVH_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR (                         \
4020         is_uv1_hub() ? UV1H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR :         \
4021         is_uv2_hub() ? UV2H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR :         \
4022         is_uv3_hub() ? UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR :         \
4023         /*is_uv4_hub*/ UV4H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR)
4024 
4025 #define UV1H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_DEPTH uv_undefined("UV1H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_DEPTH")
4026 #define UV2H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_DEPTH uv_undefined("UV2H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_DEPTH")
4027 #define UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_DEPTH 128
4028 #define UV4H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_DEPTH 128
4029 #define UVH_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_DEPTH (                   \
4030         is_uv1_hub() ? UV1H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_DEPTH :   \
4031         is_uv2_hub() ? UV2H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_DEPTH :   \
4032         is_uv3_hub() ? UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_DEPTH :   \
4033         /*is_uv4_hub*/ UV4H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_DEPTH)
4034 
4035 
4036 #define UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_NASID_SHFT 0
4037 #define UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_NASID_MASK 0x0000000000007fffUL
4038 
4039 #define UV4H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_NASID_SHFT 0
4040 #define UV4H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_NASID_MASK 0x0000000000007fffUL
4041 
4042 #define UV4AH_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_NASID_MASK 0x0000000000000fffUL
4043 
4044 #define UVH_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_NASID_MASK (              \
4045         is_uv3_hub() ? UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_NASID_MASK : \
4046         is_uv4a_hub() ? UV4AH_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_NASID_MASK : \
4047         /*is_uv4_hub*/ UV4H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_NASID_MASK)
4048 
4049 union uvh_rh_gam_mmioh_redirect_config1_mmr_u {
4050         unsigned long   v;
4051         struct uv3h_rh_gam_mmioh_redirect_config1_mmr_s {
4052                 unsigned long   nasid:15;                       /* RW */
4053                 unsigned long   rsvd_15_63:49;
4054         } s3;
4055         struct uv4h_rh_gam_mmioh_redirect_config1_mmr_s {
4056                 unsigned long   nasid:15;                       /* RW */
4057                 unsigned long   rsvd_15_63:49;
4058         } s4;
4059         struct uv4ah_rh_gam_mmioh_redirect_config1_mmr_s {
4060                 unsigned long   nasid:12;                       /* RW */
4061                 unsigned long   rsvd_12_63:52;
4062         } s4a;
4063 };
4064 
4065 /* ========================================================================= */
4066 /*                    UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR                      */
4067 /* ========================================================================= */
4068 #define UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR 0x1600028UL
4069 #define UV2H_RH_GAM_MMR_OVERLAY_CONFIG_MMR 0x1600028UL
4070 #define UV3H_RH_GAM_MMR_OVERLAY_CONFIG_MMR 0x1600028UL
4071 #define UV4H_RH_GAM_MMR_OVERLAY_CONFIG_MMR 0x480028UL
4072 #define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR (                             \
4073         is_uv1_hub() ? UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR :             \
4074         is_uv2_hub() ? UV2H_RH_GAM_MMR_OVERLAY_CONFIG_MMR :             \
4075         is_uv3_hub() ? UV3H_RH_GAM_MMR_OVERLAY_CONFIG_MMR :             \
4076         /*is_uv4_hub*/ UV4H_RH_GAM_MMR_OVERLAY_CONFIG_MMR)
4077 
4078 #define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT     26
4079 #define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_SHFT   63
4080 #define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_MASK     0x00003ffffc000000UL
4081 #define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_MASK   0x8000000000000000UL
4082 
4083 #define UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT    26
4084 #define UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_DUAL_HUB_SHFT 46
4085 #define UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_SHFT  63
4086 #define UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_MASK    0x00003ffffc000000UL
4087 #define UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_DUAL_HUB_MASK 0x0000400000000000UL
4088 #define UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_MASK  0x8000000000000000UL
4089 
4090 #define UVXH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT    26
4091 #define UVXH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_SHFT  63
4092 #define UVXH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_MASK    0x00003ffffc000000UL
4093 #define UVXH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_MASK  0x8000000000000000UL
4094 
4095 #define UV2H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT    26
4096 #define UV2H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_SHFT  63
4097 #define UV2H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_MASK    0x00003ffffc000000UL
4098 #define UV2H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_MASK  0x8000000000000000UL
4099 
4100 #define UV3H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT    26
4101 #define UV3H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_SHFT  63
4102 #define UV3H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_MASK    0x00003ffffc000000UL
4103 #define UV3H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_MASK  0x8000000000000000UL
4104 
4105 #define UV4H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT    26
4106 #define UV4H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_SHFT  63
4107 #define UV4H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_MASK    0x00003ffffc000000UL
4108 #define UV4H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_MASK  0x8000000000000000UL
4109 
4110 
4111 union uvh_rh_gam_mmr_overlay_config_mmr_u {
4112         unsigned long   v;
4113         struct uvh_rh_gam_mmr_overlay_config_mmr_s {
4114                 unsigned long   rsvd_0_25:26;
4115                 unsigned long   base:20;                        /* RW */
4116                 unsigned long   rsvd_46_62:17;
4117                 unsigned long   enable:1;                       /* RW */
4118         } s;
4119         struct uv1h_rh_gam_mmr_overlay_config_mmr_s {
4120                 unsigned long   rsvd_0_25:26;
4121                 unsigned long   base:20;                        /* RW */
4122                 unsigned long   dual_hub:1;                     /* RW */
4123                 unsigned long   rsvd_47_62:16;
4124                 unsigned long   enable:1;                       /* RW */
4125         } s1;
4126         struct uvxh_rh_gam_mmr_overlay_config_mmr_s {
4127                 unsigned long   rsvd_0_25:26;
4128                 unsigned long   base:20;                        /* RW */
4129                 unsigned long   rsvd_46_62:17;
4130                 unsigned long   enable:1;                       /* RW */
4131         } sx;
4132         struct uv2h_rh_gam_mmr_overlay_config_mmr_s {
4133                 unsigned long   rsvd_0_25:26;
4134                 unsigned long   base:20;                        /* RW */
4135                 unsigned long   rsvd_46_62:17;
4136                 unsigned long   enable:1;                       /* RW */
4137         } s2;
4138         struct uv3h_rh_gam_mmr_overlay_config_mmr_s {
4139                 unsigned long   rsvd_0_25:26;
4140                 unsigned long   base:20;                        /* RW */
4141                 unsigned long   rsvd_46_62:17;
4142                 unsigned long   enable:1;                       /* RW */
4143         } s3;
4144         struct uv4h_rh_gam_mmr_overlay_config_mmr_s {
4145                 unsigned long   rsvd_0_25:26;
4146                 unsigned long   base:20;                        /* RW */
4147                 unsigned long   rsvd_46_62:17;
4148                 unsigned long   enable:1;                       /* RW */
4149         } s4;
4150 };
4151 
4152 /* ========================================================================= */
4153 /*                                 UVH_RTC                                   */
4154 /* ========================================================================= */
4155 #define UV1H_RTC 0x340000UL
4156 #define UV2H_RTC 0x340000UL
4157 #define UV3H_RTC 0x340000UL
4158 #define UV4H_RTC 0xe0000UL
4159 #define UVH_RTC (                                                       \
4160         is_uv1_hub() ? UV1H_RTC :                                       \
4161         is_uv2_hub() ? UV2H_RTC :                                       \
4162         is_uv3_hub() ? UV3H_RTC :                                       \
4163         /*is_uv4_hub*/ UV4H_RTC)
4164 
4165 #define UVH_RTC_REAL_TIME_CLOCK_SHFT                    0
4166 #define UVH_RTC_REAL_TIME_CLOCK_MASK                    0x00ffffffffffffffUL
4167 
4168 
4169 union uvh_rtc_u {
4170         unsigned long   v;
4171         struct uvh_rtc_s {
4172                 unsigned long   real_time_clock:56;             /* RW */
4173                 unsigned long   rsvd_56_63:8;
4174         } s;
4175 };
4176 
4177 /* ========================================================================= */
4178 /*                           UVH_RTC1_INT_CONFIG                             */
4179 /* ========================================================================= */
4180 #define UVH_RTC1_INT_CONFIG 0x615c0UL
4181 
4182 #define UVH_RTC1_INT_CONFIG_VECTOR_SHFT                 0
4183 #define UVH_RTC1_INT_CONFIG_DM_SHFT                     8
4184 #define UVH_RTC1_INT_CONFIG_DESTMODE_SHFT               11
4185 #define UVH_RTC1_INT_CONFIG_STATUS_SHFT                 12
4186 #define UVH_RTC1_INT_CONFIG_P_SHFT                      13
4187 #define UVH_RTC1_INT_CONFIG_T_SHFT                      15
4188 #define UVH_RTC1_INT_CONFIG_M_SHFT                      16
4189 #define UVH_RTC1_INT_CONFIG_APIC_ID_SHFT                32
4190 #define UVH_RTC1_INT_CONFIG_VECTOR_MASK                 0x00000000000000ffUL
4191 #define UVH_RTC1_INT_CONFIG_DM_MASK                     0x0000000000000700UL
4192 #define UVH_RTC1_INT_CONFIG_DESTMODE_MASK               0x0000000000000800UL
4193 #define UVH_RTC1_INT_CONFIG_STATUS_MASK                 0x0000000000001000UL
4194 #define UVH_RTC1_INT_CONFIG_P_MASK                      0x0000000000002000UL
4195 #define UVH_RTC1_INT_CONFIG_T_MASK                      0x0000000000008000UL
4196 #define UVH_RTC1_INT_CONFIG_M_MASK                      0x0000000000010000UL
4197 #define UVH_RTC1_INT_CONFIG_APIC_ID_MASK                0xffffffff00000000UL
4198 
4199 
4200 union uvh_rtc1_int_config_u {
4201         unsigned long   v;
4202         struct uvh_rtc1_int_config_s {
4203                 unsigned long   vector_:8;                      /* RW */
4204                 unsigned long   dm:3;                           /* RW */
4205                 unsigned long   destmode:1;                     /* RW */
4206                 unsigned long   status:1;                       /* RO */
4207                 unsigned long   p:1;                            /* RO */
4208                 unsigned long   rsvd_14:1;
4209                 unsigned long   t:1;                            /* RO */
4210                 unsigned long   m:1;                            /* RW */
4211                 unsigned long   rsvd_17_31:15;
4212                 unsigned long   apic_id:32;                     /* RW */
4213         } s;
4214 };
4215 
4216 /* ========================================================================= */
4217 /*                               UVH_SCRATCH5                                */
4218 /* ========================================================================= */
4219 #define UV1H_SCRATCH5 0x2d0200UL
4220 #define UV2H_SCRATCH5 0x2d0200UL
4221 #define UV3H_SCRATCH5 0x2d0200UL
4222 #define UV4H_SCRATCH5 0xb0200UL
4223 #define UVH_SCRATCH5 (                                                  \
4224         is_uv1_hub() ? UV1H_SCRATCH5 :                                  \
4225         is_uv2_hub() ? UV2H_SCRATCH5 :                                  \
4226         is_uv3_hub() ? UV3H_SCRATCH5 :                                  \
4227         /*is_uv4_hub*/ UV4H_SCRATCH5)
4228 
4229 #define UV1H_SCRATCH5_32 0x778
4230 #define UV2H_SCRATCH5_32 0x778
4231 #define UV3H_SCRATCH5_32 0x778
4232 #define UV4H_SCRATCH5_32 0x798
4233 #define UVH_SCRATCH5_32 (                                               \
4234         is_uv1_hub() ? UV1H_SCRATCH5_32 :                               \
4235         is_uv2_hub() ? UV2H_SCRATCH5_32 :                               \
4236         is_uv3_hub() ? UV3H_SCRATCH5_32 :                               \
4237         /*is_uv4_hub*/ UV4H_SCRATCH5_32)
4238 
4239 #define UVH_SCRATCH5_SCRATCH5_SHFT                      0
4240 #define UVH_SCRATCH5_SCRATCH5_MASK                      0xffffffffffffffffUL
4241 
4242 
4243 union uvh_scratch5_u {
4244         unsigned long   v;
4245         struct uvh_scratch5_s {
4246                 unsigned long   scratch5:64;                    /* RW, W1CS */
4247         } s;
4248 };
4249 
4250 /* ========================================================================= */
4251 /*                            UVH_SCRATCH5_ALIAS                             */
4252 /* ========================================================================= */
4253 #define UV1H_SCRATCH5_ALIAS 0x2d0208UL
4254 #define UV2H_SCRATCH5_ALIAS 0x2d0208UL
4255 #define UV3H_SCRATCH5_ALIAS 0x2d0208UL
4256 #define UV4H_SCRATCH5_ALIAS 0xb0208UL
4257 #define UVH_SCRATCH5_ALIAS (                                            \
4258         is_uv1_hub() ? UV1H_SCRATCH5_ALIAS :                            \
4259         is_uv2_hub() ? UV2H_SCRATCH5_ALIAS :                            \
4260         is_uv3_hub() ? UV3H_SCRATCH5_ALIAS :                            \
4261         /*is_uv4_hub*/ UV4H_SCRATCH5_ALIAS)
4262 
4263 #define UV1H_SCRATCH5_ALIAS_32 0x780
4264 #define UV2H_SCRATCH5_ALIAS_32 0x780
4265 #define UV3H_SCRATCH5_ALIAS_32 0x780
4266 #define UV4H_SCRATCH5_ALIAS_32 0x7a0
4267 #define UVH_SCRATCH5_ALIAS_32 (                                         \
4268         is_uv1_hub() ? UV1H_SCRATCH5_ALIAS_32 :                         \
4269         is_uv2_hub() ? UV2H_SCRATCH5_ALIAS_32 :                         \
4270         is_uv3_hub() ? UV3H_SCRATCH5_ALIAS_32 :                         \
4271         /*is_uv4_hub*/ UV4H_SCRATCH5_ALIAS_32)
4272 
4273 
4274 /* ========================================================================= */
4275 /*                           UVH_SCRATCH5_ALIAS_2                            */
4276 /* ========================================================================= */
4277 #define UV1H_SCRATCH5_ALIAS_2 0x2d0210UL
4278 #define UV2H_SCRATCH5_ALIAS_2 0x2d0210UL
4279 #define UV3H_SCRATCH5_ALIAS_2 0x2d0210UL
4280 #define UV4H_SCRATCH5_ALIAS_2 0xb0210UL
4281 #define UVH_SCRATCH5_ALIAS_2 (                                          \
4282         is_uv1_hub() ? UV1H_SCRATCH5_ALIAS_2 :                          \
4283         is_uv2_hub() ? UV2H_SCRATCH5_ALIAS_2 :                          \
4284         is_uv3_hub() ? UV3H_SCRATCH5_ALIAS_2 :                          \
4285         /*is_uv4_hub*/ UV4H_SCRATCH5_ALIAS_2)
4286 #define UVH_SCRATCH5_ALIAS_2_32 0x788
4287 
4288 
4289 /* ========================================================================= */
4290 /*                          UVXH_EVENT_OCCURRED2                             */
4291 /* ========================================================================= */
4292 #define UVXH_EVENT_OCCURRED2 0x70100UL
4293 
4294 #define UV2H_EVENT_OCCURRED2_32 0xb68
4295 #define UV3H_EVENT_OCCURRED2_32 0xb68
4296 #define UV4H_EVENT_OCCURRED2_32 0x608
4297 #define UVH_EVENT_OCCURRED2_32 (                                        \
4298         is_uv2_hub() ? UV2H_EVENT_OCCURRED2_32 :                        \
4299         is_uv3_hub() ? UV3H_EVENT_OCCURRED2_32 :                        \
4300         /*is_uv4_hub*/ UV4H_EVENT_OCCURRED2_32)
4301 
4302 
4303 #define UV2H_EVENT_OCCURRED2_RTC_0_SHFT                 0
4304 #define UV2H_EVENT_OCCURRED2_RTC_1_SHFT                 1
4305 #define UV2H_EVENT_OCCURRED2_RTC_2_SHFT                 2
4306 #define UV2H_EVENT_OCCURRED2_RTC_3_SHFT                 3
4307 #define UV2H_EVENT_OCCURRED2_RTC_4_SHFT                 4
4308 #define UV2H_EVENT_OCCURRED2_RTC_5_SHFT                 5
4309 #define UV2H_EVENT_OCCURRED2_RTC_6_SHFT                 6
4310 #define UV2H_EVENT_OCCURRED2_RTC_7_SHFT                 7
4311 #define UV2H_EVENT_OCCURRED2_RTC_8_SHFT                 8
4312 #define UV2H_EVENT_OCCURRED2_RTC_9_SHFT                 9
4313 #define UV2H_EVENT_OCCURRED2_RTC_10_SHFT                10
4314 #define UV2H_EVENT_OCCURRED2_RTC_11_SHFT                11
4315 #define UV2H_EVENT_OCCURRED2_RTC_12_SHFT                12
4316 #define UV2H_EVENT_OCCURRED2_RTC_13_SHFT                13
4317 #define UV2H_EVENT_OCCURRED2_RTC_14_SHFT                14
4318 #define UV2H_EVENT_OCCURRED2_RTC_15_SHFT                15
4319 #define UV2H_EVENT_OCCURRED2_RTC_16_SHFT                16
4320 #define UV2H_EVENT_OCCURRED2_RTC_17_SHFT                17
4321 #define UV2H_EVENT_OCCURRED2_RTC_18_SHFT                18
4322 #define UV2H_EVENT_OCCURRED2_RTC_19_SHFT                19
4323 #define UV2H_EVENT_OCCURRED2_RTC_20_SHFT                20
4324 #define UV2H_EVENT_OCCURRED2_RTC_21_SHFT                21
4325 #define UV2H_EVENT_OCCURRED2_RTC_22_SHFT                22
4326 #define UV2H_EVENT_OCCURRED2_RTC_23_SHFT                23
4327 #define UV2H_EVENT_OCCURRED2_RTC_24_SHFT                24
4328 #define UV2H_EVENT_OCCURRED2_RTC_25_SHFT                25
4329 #define UV2H_EVENT_OCCURRED2_RTC_26_SHFT                26
4330 #define UV2H_EVENT_OCCURRED2_RTC_27_SHFT                27
4331 #define UV2H_EVENT_OCCURRED2_RTC_28_SHFT                28
4332 #define UV2H_EVENT_OCCURRED2_RTC_29_SHFT                29
4333 #define UV2H_EVENT_OCCURRED2_RTC_30_SHFT                30
4334 #define UV2H_EVENT_OCCURRED2_RTC_31_SHFT                31
4335 #define UV2H_EVENT_OCCURRED2_RTC_0_MASK                 0x0000000000000001UL
4336 #define UV2H_EVENT_OCCURRED2_RTC_1_MASK                 0x0000000000000002UL
4337 #define UV2H_EVENT_OCCURRED2_RTC_2_MASK                 0x0000000000000004UL
4338 #define UV2H_EVENT_OCCURRED2_RTC_3_MASK                 0x0000000000000008UL
4339 #define UV2H_EVENT_OCCURRED2_RTC_4_MASK                 0x0000000000000010UL
4340 #define UV2H_EVENT_OCCURRED2_RTC_5_MASK                 0x0000000000000020UL
4341 #define UV2H_EVENT_OCCURRED2_RTC_6_MASK                 0x0000000000000040UL
4342 #define UV2H_EVENT_OCCURRED2_RTC_7_MASK                 0x0000000000000080UL
4343 #define UV2H_EVENT_OCCURRED2_RTC_8_MASK                 0x0000000000000100UL
4344 #define UV2H_EVENT_OCCURRED2_RTC_9_MASK                 0x0000000000000200UL
4345 #define UV2H_EVENT_OCCURRED2_RTC_10_MASK                0x0000000000000400UL
4346 #define UV2H_EVENT_OCCURRED2_RTC_11_MASK                0x0000000000000800UL
4347 #define UV2H_EVENT_OCCURRED2_RTC_12_MASK                0x0000000000001000UL
4348 #define UV2H_EVENT_OCCURRED2_RTC_13_MASK                0x0000000000002000UL
4349 #define UV2H_EVENT_OCCURRED2_RTC_14_MASK                0x0000000000004000UL
4350 #define UV2H_EVENT_OCCURRED2_RTC_15_MASK                0x0000000000008000UL
4351 #define UV2H_EVENT_OCCURRED2_RTC_16_MASK                0x0000000000010000UL
4352 #define UV2H_EVENT_OCCURRED2_RTC_17_MASK                0x0000000000020000UL
4353 #define UV2H_EVENT_OCCURRED2_RTC_18_MASK                0x0000000000040000UL
4354 #define UV2H_EVENT_OCCURRED2_RTC_19_MASK                0x0000000000080000UL
4355 #define UV2H_EVENT_OCCURRED2_RTC_20_MASK                0x0000000000100000UL
4356 #define UV2H_EVENT_OCCURRED2_RTC_21_MASK                0x0000000000200000UL
4357 #define UV2H_EVENT_OCCURRED2_RTC_22_MASK                0x0000000000400000UL
4358 #define UV2H_EVENT_OCCURRED2_RTC_23_MASK                0x0000000000800000UL
4359 #define UV2H_EVENT_OCCURRED2_RTC_24_MASK                0x0000000001000000UL
4360 #define UV2H_EVENT_OCCURRED2_RTC_25_MASK                0x0000000002000000UL
4361 #define UV2H_EVENT_OCCURRED2_RTC_26_MASK                0x0000000004000000UL
4362 #define UV2H_EVENT_OCCURRED2_RTC_27_MASK                0x0000000008000000UL
4363 #define UV2H_EVENT_OCCURRED2_RTC_28_MASK                0x0000000010000000UL
4364 #define UV2H_EVENT_OCCURRED2_RTC_29_MASK                0x0000000020000000UL
4365 #define UV2H_EVENT_OCCURRED2_RTC_30_MASK                0x0000000040000000UL
4366 #define UV2H_EVENT_OCCURRED2_RTC_31_MASK                0x0000000080000000UL
4367 
4368 #define UV3H_EVENT_OCCURRED2_RTC_0_SHFT                 0
4369 #define UV3H_EVENT_OCCURRED2_RTC_1_SHFT                 1
4370 #define UV3H_EVENT_OCCURRED2_RTC_2_SHFT                 2
4371 #define UV3H_EVENT_OCCURRED2_RTC_3_SHFT                 3
4372 #define UV3H_EVENT_OCCURRED2_RTC_4_SHFT                 4
4373 #define UV3H_EVENT_OCCURRED2_RTC_5_SHFT                 5
4374 #define UV3H_EVENT_OCCURRED2_RTC_6_SHFT                 6
4375 #define UV3H_EVENT_OCCURRED2_RTC_7_SHFT                 7
4376 #define UV3H_EVENT_OCCURRED2_RTC_8_SHFT                 8
4377 #define UV3H_EVENT_OCCURRED2_RTC_9_SHFT                 9
4378 #define UV3H_EVENT_OCCURRED2_RTC_10_SHFT                10
4379 #define UV3H_EVENT_OCCURRED2_RTC_11_SHFT                11
4380 #define UV3H_EVENT_OCCURRED2_RTC_12_SHFT                12
4381 #define UV3H_EVENT_OCCURRED2_RTC_13_SHFT                13
4382 #define UV3H_EVENT_OCCURRED2_RTC_14_SHFT                14
4383 #define UV3H_EVENT_OCCURRED2_RTC_15_SHFT                15
4384 #define UV3H_EVENT_OCCURRED2_RTC_16_SHFT                16
4385 #define UV3H_EVENT_OCCURRED2_RTC_17_SHFT                17
4386 #define UV3H_EVENT_OCCURRED2_RTC_18_SHFT                18
4387 #define UV3H_EVENT_OCCURRED2_RTC_19_SHFT                19
4388 #define UV3H_EVENT_OCCURRED2_RTC_20_SHFT                20
4389 #define UV3H_EVENT_OCCURRED2_RTC_21_SHFT                21
4390 #define UV3H_EVENT_OCCURRED2_RTC_22_SHFT                22
4391 #define UV3H_EVENT_OCCURRED2_RTC_23_SHFT                23
4392 #define UV3H_EVENT_OCCURRED2_RTC_24_SHFT                24
4393 #define UV3H_EVENT_OCCURRED2_RTC_25_SHFT                25
4394 #define UV3H_EVENT_OCCURRED2_RTC_26_SHFT                26
4395 #define UV3H_EVENT_OCCURRED2_RTC_27_SHFT                27
4396 #define UV3H_EVENT_OCCURRED2_RTC_28_SHFT                28
4397 #define UV3H_EVENT_OCCURRED2_RTC_29_SHFT                29
4398 #define UV3H_EVENT_OCCURRED2_RTC_30_SHFT                30
4399 #define UV3H_EVENT_OCCURRED2_RTC_31_SHFT                31
4400 #define UV3H_EVENT_OCCURRED2_RTC_0_MASK                 0x0000000000000001UL
4401 #define UV3H_EVENT_OCCURRED2_RTC_1_MASK                 0x0000000000000002UL
4402 #define UV3H_EVENT_OCCURRED2_RTC_2_MASK                 0x0000000000000004UL
4403 #define UV3H_EVENT_OCCURRED2_RTC_3_MASK                 0x0000000000000008UL
4404 #define UV3H_EVENT_OCCURRED2_RTC_4_MASK                 0x0000000000000010UL
4405 #define UV3H_EVENT_OCCURRED2_RTC_5_MASK                 0x0000000000000020UL
4406 #define UV3H_EVENT_OCCURRED2_RTC_6_MASK                 0x0000000000000040UL
4407 #define UV3H_EVENT_OCCURRED2_RTC_7_MASK                 0x0000000000000080UL
4408 #define UV3H_EVENT_OCCURRED2_RTC_8_MASK                 0x0000000000000100UL
4409 #define UV3H_EVENT_OCCURRED2_RTC_9_MASK                 0x0000000000000200UL
4410 #define UV3H_EVENT_OCCURRED2_RTC_10_MASK                0x0000000000000400UL
4411 #define UV3H_EVENT_OCCURRED2_RTC_11_MASK                0x0000000000000800UL
4412 #define UV3H_EVENT_OCCURRED2_RTC_12_MASK                0x0000000000001000UL
4413 #define UV3H_EVENT_OCCURRED2_RTC_13_MASK                0x0000000000002000UL
4414 #define UV3H_EVENT_OCCURRED2_RTC_14_MASK                0x0000000000004000UL
4415 #define UV3H_EVENT_OCCURRED2_RTC_15_MASK                0x0000000000008000UL
4416 #define UV3H_EVENT_OCCURRED2_RTC_16_MASK                0x0000000000010000UL
4417 #define UV3H_EVENT_OCCURRED2_RTC_17_MASK                0x0000000000020000UL
4418 #define UV3H_EVENT_OCCURRED2_RTC_18_MASK                0x0000000000040000UL
4419 #define UV3H_EVENT_OCCURRED2_RTC_19_MASK                0x0000000000080000UL
4420 #define UV3H_EVENT_OCCURRED2_RTC_20_MASK                0x0000000000100000UL
4421 #define UV3H_EVENT_OCCURRED2_RTC_21_MASK                0x0000000000200000UL
4422 #define UV3H_EVENT_OCCURRED2_RTC_22_MASK                0x0000000000400000UL
4423 #define UV3H_EVENT_OCCURRED2_RTC_23_MASK                0x0000000000800000UL
4424 #define UV3H_EVENT_OCCURRED2_RTC_24_MASK                0x0000000001000000UL
4425 #define UV3H_EVENT_OCCURRED2_RTC_25_MASK                0x0000000002000000UL
4426 #define UV3H_EVENT_OCCURRED2_RTC_26_MASK                0x0000000004000000UL
4427 #define UV3H_EVENT_OCCURRED2_RTC_27_MASK                0x0000000008000000UL
4428 #define UV3H_EVENT_OCCURRED2_RTC_28_MASK                0x0000000010000000UL
4429 #define UV3H_EVENT_OCCURRED2_RTC_29_MASK                0x0000000020000000UL
4430 #define UV3H_EVENT_OCCURRED2_RTC_30_MASK                0x0000000040000000UL
4431 #define UV3H_EVENT_OCCURRED2_RTC_31_MASK                0x0000000080000000UL
4432 
4433 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT0_SHFT 0
4434 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT1_SHFT 1
4435 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT2_SHFT 2
4436 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT3_SHFT 3
4437 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT4_SHFT 4
4438 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT5_SHFT 5
4439 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT6_SHFT 6
4440 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT7_SHFT 7
4441 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT8_SHFT 8
4442 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT9_SHFT 9
4443 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT10_SHFT 10
4444 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT11_SHFT 11
4445 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT12_SHFT 12
4446 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT13_SHFT 13
4447 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT14_SHFT 14
4448 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT15_SHFT 15
4449 #define UV4H_EVENT_OCCURRED2_RTC_INTERVAL_INT_SHFT      16
4450 #define UV4H_EVENT_OCCURRED2_BAU_DASHBOARD_INT_SHFT     17
4451 #define UV4H_EVENT_OCCURRED2_RTC_0_SHFT                 18
4452 #define UV4H_EVENT_OCCURRED2_RTC_1_SHFT                 19
4453 #define UV4H_EVENT_OCCURRED2_RTC_2_SHFT                 20
4454 #define UV4H_EVENT_OCCURRED2_RTC_3_SHFT                 21
4455 #define UV4H_EVENT_OCCURRED2_RTC_4_SHFT                 22
4456 #define UV4H_EVENT_OCCURRED2_RTC_5_SHFT                 23
4457 #define UV4H_EVENT_OCCURRED2_RTC_6_SHFT                 24
4458 #define UV4H_EVENT_OCCURRED2_RTC_7_SHFT                 25
4459 #define UV4H_EVENT_OCCURRED2_RTC_8_SHFT                 26
4460 #define UV4H_EVENT_OCCURRED2_RTC_9_SHFT                 27
4461 #define UV4H_EVENT_OCCURRED2_RTC_10_SHFT                28
4462 #define UV4H_EVENT_OCCURRED2_RTC_11_SHFT                29
4463 #define UV4H_EVENT_OCCURRED2_RTC_12_SHFT                30
4464 #define UV4H_EVENT_OCCURRED2_RTC_13_SHFT                31
4465 #define UV4H_EVENT_OCCURRED2_RTC_14_SHFT                32
4466 #define UV4H_EVENT_OCCURRED2_RTC_15_SHFT                33
4467 #define UV4H_EVENT_OCCURRED2_RTC_16_SHFT                34
4468 #define UV4H_EVENT_OCCURRED2_RTC_17_SHFT                35
4469 #define UV4H_EVENT_OCCURRED2_RTC_18_SHFT                36
4470 #define UV4H_EVENT_OCCURRED2_RTC_19_SHFT                37
4471 #define UV4H_EVENT_OCCURRED2_RTC_20_SHFT                38
4472 #define UV4H_EVENT_OCCURRED2_RTC_21_SHFT                39
4473 #define UV4H_EVENT_OCCURRED2_RTC_22_SHFT                40
4474 #define UV4H_EVENT_OCCURRED2_RTC_23_SHFT                41
4475 #define UV4H_EVENT_OCCURRED2_RTC_24_SHFT                42
4476 #define UV4H_EVENT_OCCURRED2_RTC_25_SHFT                43
4477 #define UV4H_EVENT_OCCURRED2_RTC_26_SHFT                44
4478 #define UV4H_EVENT_OCCURRED2_RTC_27_SHFT                45
4479 #define UV4H_EVENT_OCCURRED2_RTC_28_SHFT                46
4480 #define UV4H_EVENT_OCCURRED2_RTC_29_SHFT                47
4481 #define UV4H_EVENT_OCCURRED2_RTC_30_SHFT                48
4482 #define UV4H_EVENT_OCCURRED2_RTC_31_SHFT                49
4483 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT0_MASK 0x0000000000000001UL
4484 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT1_MASK 0x0000000000000002UL
4485 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT2_MASK 0x0000000000000004UL
4486 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT3_MASK 0x0000000000000008UL
4487 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT4_MASK 0x0000000000000010UL
4488 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT5_MASK 0x0000000000000020UL
4489 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT6_MASK 0x0000000000000040UL
4490 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT7_MASK 0x0000000000000080UL
4491 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT8_MASK 0x0000000000000100UL
4492 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT9_MASK 0x0000000000000200UL
4493 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT10_MASK 0x0000000000000400UL
4494 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT11_MASK 0x0000000000000800UL
4495 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT12_MASK 0x0000000000001000UL
4496 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT13_MASK 0x0000000000002000UL
4497 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT14_MASK 0x0000000000004000UL
4498 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT15_MASK 0x0000000000008000UL
4499 #define UV4H_EVENT_OCCURRED2_RTC_INTERVAL_INT_MASK      0x0000000000010000UL
4500 #define UV4H_EVENT_OCCURRED2_BAU_DASHBOARD_INT_MASK     0x0000000000020000UL
4501 #define UV4H_EVENT_OCCURRED2_RTC_0_MASK                 0x0000000000040000UL
4502 #define UV4H_EVENT_OCCURRED2_RTC_1_MASK                 0x0000000000080000UL
4503 #define UV4H_EVENT_OCCURRED2_RTC_2_MASK                 0x0000000000100000UL
4504 #define UV4H_EVENT_OCCURRED2_RTC_3_MASK                 0x0000000000200000UL
4505 #define UV4H_EVENT_OCCURRED2_RTC_4_MASK                 0x0000000000400000UL
4506 #define UV4H_EVENT_OCCURRED2_RTC_5_MASK                 0x0000000000800000UL
4507 #define UV4H_EVENT_OCCURRED2_RTC_6_MASK                 0x0000000001000000UL
4508 #define UV4H_EVENT_OCCURRED2_RTC_7_MASK                 0x0000000002000000UL
4509 #define UV4H_EVENT_OCCURRED2_RTC_8_MASK                 0x0000000004000000UL
4510 #define UV4H_EVENT_OCCURRED2_RTC_9_MASK                 0x0000000008000000UL
4511 #define UV4H_EVENT_OCCURRED2_RTC_10_MASK                0x0000000010000000UL
4512 #define UV4H_EVENT_OCCURRED2_RTC_11_MASK                0x0000000020000000UL
4513 #define UV4H_EVENT_OCCURRED2_RTC_12_MASK                0x0000000040000000UL
4514 #define UV4H_EVENT_OCCURRED2_RTC_13_MASK                0x0000000080000000UL
4515 #define UV4H_EVENT_OCCURRED2_RTC_14_MASK                0x0000000100000000UL
4516 #define UV4H_EVENT_OCCURRED2_RTC_15_MASK                0x0000000200000000UL
4517 #define UV4H_EVENT_OCCURRED2_RTC_16_MASK                0x0000000400000000UL
4518 #define UV4H_EVENT_OCCURRED2_RTC_17_MASK                0x0000000800000000UL
4519 #define UV4H_EVENT_OCCURRED2_RTC_18_MASK                0x0000001000000000UL
4520 #define UV4H_EVENT_OCCURRED2_RTC_19_MASK                0x0000002000000000UL
4521 #define UV4H_EVENT_OCCURRED2_RTC_20_MASK                0x0000004000000000UL
4522 #define UV4H_EVENT_OCCURRED2_RTC_21_MASK                0x0000008000000000UL
4523 #define UV4H_EVENT_OCCURRED2_RTC_22_MASK                0x0000010000000000UL
4524 #define UV4H_EVENT_OCCURRED2_RTC_23_MASK                0x0000020000000000UL
4525 #define UV4H_EVENT_OCCURRED2_RTC_24_MASK                0x0000040000000000UL
4526 #define UV4H_EVENT_OCCURRED2_RTC_25_MASK                0x0000080000000000UL
4527 #define UV4H_EVENT_OCCURRED2_RTC_26_MASK                0x0000100000000000UL
4528 #define UV4H_EVENT_OCCURRED2_RTC_27_MASK                0x0000200000000000UL
4529 #define UV4H_EVENT_OCCURRED2_RTC_28_MASK                0x0000400000000000UL
4530 #define UV4H_EVENT_OCCURRED2_RTC_29_MASK                0x0000800000000000UL
4531 #define UV4H_EVENT_OCCURRED2_RTC_30_MASK                0x0001000000000000UL
4532 #define UV4H_EVENT_OCCURRED2_RTC_31_MASK                0x0002000000000000UL
4533 
4534 #define UVXH_EVENT_OCCURRED2_RTC_1_MASK (                               \
4535         is_uv2_hub() ? UV2H_EVENT_OCCURRED2_RTC_1_MASK :                \
4536         is_uv3_hub() ? UV3H_EVENT_OCCURRED2_RTC_1_MASK :                \
4537         /*is_uv4_hub*/ UV4H_EVENT_OCCURRED2_RTC_1_MASK)
4538 
4539 union uvh_event_occurred2_u {
4540         unsigned long   v;
4541         struct uv2h_event_occurred2_s {
4542                 unsigned long   rtc_0:1;                        /* RW */
4543                 unsigned long   rtc_1:1;                        /* RW */
4544                 unsigned long   rtc_2:1;                        /* RW */
4545                 unsigned long   rtc_3:1;                        /* RW */
4546                 unsigned long   rtc_4:1;                        /* RW */
4547                 unsigned long   rtc_5:1;                        /* RW */
4548                 unsigned long   rtc_6:1;                        /* RW */
4549                 unsigned long   rtc_7:1;                        /* RW */
4550                 unsigned long   rtc_8:1;                        /* RW */
4551                 unsigned long   rtc_9:1;                        /* RW */
4552                 unsigned long   rtc_10:1;                       /* RW */
4553                 unsigned long   rtc_11:1;                       /* RW */
4554                 unsigned long   rtc_12:1;                       /* RW */
4555                 unsigned long   rtc_13:1;                       /* RW */
4556                 unsigned long   rtc_14:1;                       /* RW */
4557                 unsigned long   rtc_15:1;                       /* RW */
4558                 unsigned long   rtc_16:1;                       /* RW */
4559                 unsigned long   rtc_17:1;                       /* RW */
4560                 unsigned long   rtc_18:1;                       /* RW */
4561                 unsigned long   rtc_19:1;                       /* RW */
4562                 unsigned long   rtc_20:1;                       /* RW */
4563                 unsigned long   rtc_21:1;                       /* RW */
4564                 unsigned long   rtc_22:1;                       /* RW */
4565                 unsigned long   rtc_23:1;                       /* RW */
4566                 unsigned long   rtc_24:1;                       /* RW */
4567                 unsigned long   rtc_25:1;                       /* RW */
4568                 unsigned long   rtc_26:1;                       /* RW */
4569                 unsigned long   rtc_27:1;                       /* RW */
4570                 unsigned long   rtc_28:1;                       /* RW */
4571                 unsigned long   rtc_29:1;                       /* RW */
4572                 unsigned long   rtc_30:1;                       /* RW */
4573                 unsigned long   rtc_31:1;                       /* RW */
4574                 unsigned long   rsvd_32_63:32;
4575         } s2;
4576         struct uv3h_event_occurred2_s {
4577                 unsigned long   rtc_0:1;                        /* RW */
4578                 unsigned long   rtc_1:1;                        /* RW */
4579                 unsigned long   rtc_2:1;                        /* RW */
4580                 unsigned long   rtc_3:1;                        /* RW */
4581                 unsigned long   rtc_4:1;                        /* RW */
4582                 unsigned long   rtc_5:1;                        /* RW */
4583                 unsigned long   rtc_6:1;                        /* RW */
4584                 unsigned long   rtc_7:1;                        /* RW */
4585                 unsigned long   rtc_8:1;                        /* RW */
4586                 unsigned long   rtc_9:1;                        /* RW */
4587                 unsigned long   rtc_10:1;                       /* RW */
4588                 unsigned long   rtc_11:1;                       /* RW */
4589                 unsigned long   rtc_12:1;                       /* RW */
4590                 unsigned long   rtc_13:1;                       /* RW */
4591                 unsigned long   rtc_14:1;                       /* RW */
4592                 unsigned long   rtc_15:1;                       /* RW */
4593                 unsigned long   rtc_16:1;                       /* RW */
4594                 unsigned long   rtc_17:1;                       /* RW */
4595                 unsigned long   rtc_18:1;                       /* RW */
4596                 unsigned long   rtc_19:1;                       /* RW */
4597                 unsigned long   rtc_20:1;                       /* RW */
4598                 unsigned long   rtc_21:1;                       /* RW */
4599                 unsigned long   rtc_22:1;                       /* RW */
4600                 unsigned long   rtc_23:1;                       /* RW */
4601                 unsigned long   rtc_24:1;                       /* RW */
4602                 unsigned long   rtc_25:1;                       /* RW */
4603                 unsigned long   rtc_26:1;                       /* RW */
4604                 unsigned long   rtc_27:1;                       /* RW */
4605                 unsigned long   rtc_28:1;                       /* RW */
4606                 unsigned long   rtc_29:1;                       /* RW */
4607                 unsigned long   rtc_30:1;                       /* RW */
4608                 unsigned long   rtc_31:1;                       /* RW */
4609                 unsigned long   rsvd_32_63:32;
4610         } s3;
4611         struct uv4h_event_occurred2_s {
4612                 unsigned long   message_accelerator_int0:1;     /* RW */
4613                 unsigned long   message_accelerator_int1:1;     /* RW */
4614                 unsigned long   message_accelerator_int2:1;     /* RW */
4615                 unsigned long   message_accelerator_int3:1;     /* RW */
4616                 unsigned long   message_accelerator_int4:1;     /* RW */
4617                 unsigned long   message_accelerator_int5:1;     /* RW */
4618                 unsigned long   message_accelerator_int6:1;     /* RW */
4619                 unsigned long   message_accelerator_int7:1;     /* RW */
4620                 unsigned long   message_accelerator_int8:1;     /* RW */
4621                 unsigned long   message_accelerator_int9:1;     /* RW */
4622                 unsigned long   message_accelerator_int10:1;    /* RW */
4623                 unsigned long   message_accelerator_int11:1;    /* RW */
4624                 unsigned long   message_accelerator_int12:1;    /* RW */
4625                 unsigned long   message_accelerator_int13:1;    /* RW */
4626                 unsigned long   message_accelerator_int14:1;    /* RW */
4627                 unsigned long   message_accelerator_int15:1;    /* RW */
4628                 unsigned long   rtc_interval_int:1;             /* RW */
4629                 unsigned long   bau_dashboard_int:1;            /* RW */
4630                 unsigned long   rtc_0:1;                        /* RW */
4631                 unsigned long   rtc_1:1;                        /* RW */
4632                 unsigned long   rtc_2:1;                        /* RW */
4633                 unsigned long   rtc_3:1;                        /* RW */
4634                 unsigned long   rtc_4:1;                        /* RW */
4635                 unsigned long   rtc_5:1;                        /* RW */
4636                 unsigned long   rtc_6:1;                        /* RW */
4637                 unsigned long   rtc_7:1;                        /* RW */
4638                 unsigned long   rtc_8:1;                        /* RW */
4639                 unsigned long   rtc_9:1;                        /* RW */
4640                 unsigned long   rtc_10:1;                       /* RW */
4641                 unsigned long   rtc_11:1;                       /* RW */
4642                 unsigned long   rtc_12:1;                       /* RW */
4643                 unsigned long   rtc_13:1;                       /* RW */
4644                 unsigned long   rtc_14:1;                       /* RW */
4645                 unsigned long   rtc_15:1;                       /* RW */
4646                 unsigned long   rtc_16:1;                       /* RW */
4647                 unsigned long   rtc_17:1;                       /* RW */
4648                 unsigned long   rtc_18:1;                       /* RW */
4649                 unsigned long   rtc_19:1;                       /* RW */
4650                 unsigned long   rtc_20:1;                       /* RW */
4651                 unsigned long   rtc_21:1;                       /* RW */
4652                 unsigned long   rtc_22:1;                       /* RW */
4653                 unsigned long   rtc_23:1;                       /* RW */
4654                 unsigned long   rtc_24:1;                       /* RW */
4655                 unsigned long   rtc_25:1;                       /* RW */
4656                 unsigned long   rtc_26:1;                       /* RW */
4657                 unsigned long   rtc_27:1;                       /* RW */
4658                 unsigned long   rtc_28:1;                       /* RW */
4659                 unsigned long   rtc_29:1;                       /* RW */
4660                 unsigned long   rtc_30:1;                       /* RW */
4661                 unsigned long   rtc_31:1;                       /* RW */
4662                 unsigned long   rsvd_50_63:14;
4663         } s4;
4664 };
4665 
4666 /* ========================================================================= */
4667 /*                       UVXH_EVENT_OCCURRED2_ALIAS                          */
4668 /* ========================================================================= */
4669 #define UVXH_EVENT_OCCURRED2_ALIAS 0x70108UL
4670 
4671 #define UV2H_EVENT_OCCURRED2_ALIAS_32 0xb70
4672 #define UV3H_EVENT_OCCURRED2_ALIAS_32 0xb70
4673 #define UV4H_EVENT_OCCURRED2_ALIAS_32 0x610
4674 #define UVH_EVENT_OCCURRED2_ALIAS_32 (                                  \
4675         is_uv2_hub() ? UV2H_EVENT_OCCURRED2_ALIAS_32 :                  \
4676         is_uv3_hub() ? UV3H_EVENT_OCCURRED2_ALIAS_32 :                  \
4677         /*is_uv4_hub*/ UV4H_EVENT_OCCURRED2_ALIAS_32)
4678 
4679 
4680 /* ========================================================================= */
4681 /*                   UVXH_LB_BAU_SB_ACTIVATION_STATUS_2                      */
4682 /* ========================================================================= */
4683 #define UV2H_LB_BAU_SB_ACTIVATION_STATUS_2 0x320130UL
4684 #define UV3H_LB_BAU_SB_ACTIVATION_STATUS_2 0x320130UL
4685 #define UV4H_LB_BAU_SB_ACTIVATION_STATUS_2 0xc8130UL
4686 #define UVH_LB_BAU_SB_ACTIVATION_STATUS_2 (                             \
4687         is_uv2_hub() ? UV2H_LB_BAU_SB_ACTIVATION_STATUS_2 :             \
4688         is_uv3_hub() ? UV3H_LB_BAU_SB_ACTIVATION_STATUS_2 :             \
4689         /*is_uv4_hub*/ UV4H_LB_BAU_SB_ACTIVATION_STATUS_2)
4690 
4691 #define UV2H_LB_BAU_SB_ACTIVATION_STATUS_2_32 0x9f0
4692 #define UV3H_LB_BAU_SB_ACTIVATION_STATUS_2_32 0x9f0
4693 #define UV4H_LB_BAU_SB_ACTIVATION_STATUS_2_32 0xa10
4694 #define UVH_LB_BAU_SB_ACTIVATION_STATUS_2_32 (                          \
4695         is_uv2_hub() ? UV2H_LB_BAU_SB_ACTIVATION_STATUS_2_32 :          \
4696         is_uv3_hub() ? UV3H_LB_BAU_SB_ACTIVATION_STATUS_2_32 :          \
4697         /*is_uv4_hub*/ UV4H_LB_BAU_SB_ACTIVATION_STATUS_2_32)
4698 
4699 #define UVXH_LB_BAU_SB_ACTIVATION_STATUS_2_AUX_ERROR_SHFT 0
4700 #define UVXH_LB_BAU_SB_ACTIVATION_STATUS_2_AUX_ERROR_MASK 0xffffffffffffffffUL
4701 
4702 #define UV2H_LB_BAU_SB_ACTIVATION_STATUS_2_AUX_ERROR_SHFT 0
4703 #define UV2H_LB_BAU_SB_ACTIVATION_STATUS_2_AUX_ERROR_MASK 0xffffffffffffffffUL
4704 
4705 #define UV3H_LB_BAU_SB_ACTIVATION_STATUS_2_AUX_ERROR_SHFT 0
4706 #define UV3H_LB_BAU_SB_ACTIVATION_STATUS_2_AUX_ERROR_MASK 0xffffffffffffffffUL
4707 
4708 #define UV4H_LB_BAU_SB_ACTIVATION_STATUS_2_AUX_ERROR_SHFT 0
4709 #define UV4H_LB_BAU_SB_ACTIVATION_STATUS_2_AUX_ERROR_MASK 0xffffffffffffffffUL
4710 
4711 
4712 union uvxh_lb_bau_sb_activation_status_2_u {
4713         unsigned long   v;
4714         struct uvxh_lb_bau_sb_activation_status_2_s {
4715                 unsigned long   aux_error:64;                   /* RW */
4716         } sx;
4717         struct uv2h_lb_bau_sb_activation_status_2_s {
4718                 unsigned long   aux_error:64;                   /* RW */
4719         } s2;
4720         struct uv3h_lb_bau_sb_activation_status_2_s {
4721                 unsigned long   aux_error:64;                   /* RW */
4722         } s3;
4723         struct uv4h_lb_bau_sb_activation_status_2_s {
4724                 unsigned long   aux_error:64;                   /* RW */
4725         } s4;
4726 };
4727 
4728 /* ========================================================================= */
4729 /*                   UV1H_LB_TARGET_PHYSICAL_APIC_ID_MASK                    */
4730 /* ========================================================================= */
4731 #define UV1H_LB_TARGET_PHYSICAL_APIC_ID_MASK            0x320130UL
4732 #define UV1H_LB_TARGET_PHYSICAL_APIC_ID_MASK_32         0x9f0
4733 
4734 #define UV1H_LB_TARGET_PHYSICAL_APIC_ID_MASK_BIT_ENABLES_SHFT 0
4735 #define UV1H_LB_TARGET_PHYSICAL_APIC_ID_MASK_BIT_ENABLES_MASK 0x00000000ffffffffUL
4736 
4737 union uv1h_lb_target_physical_apic_id_mask_u {
4738         unsigned long   v;
4739         struct uv1h_lb_target_physical_apic_id_mask_s {
4740                 unsigned long   bit_enables:32;                 /* RW */
4741                 unsigned long   rsvd_32_63:32;
4742         } s1;
4743 };
4744 
4745 /* ========================================================================= */
4746 /*                          UV3H_GR0_GAM_GR_CONFIG                           */
4747 /* ========================================================================= */
4748 #define UV3H_GR0_GAM_GR_CONFIG                          0xc00028UL
4749 
4750 #define UV3H_GR0_GAM_GR_CONFIG_M_SKT_SHFT               0
4751 #define UV3H_GR0_GAM_GR_CONFIG_SUBSPACE_SHFT            10
4752 #define UV3H_GR0_GAM_GR_CONFIG_M_SKT_MASK               0x000000000000003fUL
4753 #define UV3H_GR0_GAM_GR_CONFIG_SUBSPACE_MASK            0x0000000000000400UL
4754 
4755 union uv3h_gr0_gam_gr_config_u {
4756         unsigned long   v;
4757         struct uv3h_gr0_gam_gr_config_s {
4758                 unsigned long   m_skt:6;                        /* RW */
4759                 unsigned long   undef_6_9:4;                    /* Undefined */
4760                 unsigned long   subspace:1;                     /* RW */
4761                 unsigned long   reserved:53;
4762         } s3;
4763 };
4764 
4765 /* ========================================================================= */
4766 /*                       UV4H_LB_PROC_INTD_QUEUE_FIRST                       */
4767 /* ========================================================================= */
4768 #define UV4H_LB_PROC_INTD_QUEUE_FIRST                   0xa4100UL
4769 
4770 #define UV4H_LB_PROC_INTD_QUEUE_FIRST_FIRST_PAYLOAD_ADDRESS_SHFT 6
4771 #define UV4H_LB_PROC_INTD_QUEUE_FIRST_FIRST_PAYLOAD_ADDRESS_MASK 0x00003fffffffffc0UL
4772 
4773 union uv4h_lb_proc_intd_queue_first_u {
4774         unsigned long   v;
4775         struct uv4h_lb_proc_intd_queue_first_s {
4776                 unsigned long   undef_0_5:6;                    /* Undefined */
4777                 unsigned long   first_payload_address:40;       /* RW */
4778         } s4;
4779 };
4780 
4781 /* ========================================================================= */
4782 /*                       UV4H_LB_PROC_INTD_QUEUE_LAST                        */
4783 /* ========================================================================= */
4784 #define UV4H_LB_PROC_INTD_QUEUE_LAST                    0xa4108UL
4785 
4786 #define UV4H_LB_PROC_INTD_QUEUE_LAST_LAST_PAYLOAD_ADDRESS_SHFT 5
4787 #define UV4H_LB_PROC_INTD_QUEUE_LAST_LAST_PAYLOAD_ADDRESS_MASK 0x00003fffffffffe0UL
4788 
4789 union uv4h_lb_proc_intd_queue_last_u {
4790         unsigned long   v;
4791         struct uv4h_lb_proc_intd_queue_last_s {
4792                 unsigned long   undef_0_4:5;                    /* Undefined */
4793                 unsigned long   last_payload_address:41;        /* RW */
4794         } s4;
4795 };
4796 
4797 /* ========================================================================= */
4798 /*                     UV4H_LB_PROC_INTD_SOFT_ACK_CLEAR                      */
4799 /* ========================================================================= */
4800 #define UV4H_LB_PROC_INTD_SOFT_ACK_CLEAR                0xa4118UL
4801 
4802 #define UV4H_LB_PROC_INTD_SOFT_ACK_CLEAR_SOFT_ACK_PENDING_FLAGS_SHFT 0
4803 #define UV4H_LB_PROC_INTD_SOFT_ACK_CLEAR_SOFT_ACK_PENDING_FLAGS_MASK 0x00000000000000ffUL
4804 
4805 union uv4h_lb_proc_intd_soft_ack_clear_u {
4806         unsigned long   v;
4807         struct uv4h_lb_proc_intd_soft_ack_clear_s {
4808                 unsigned long   soft_ack_pending_flags:8;       /* WP */
4809         } s4;
4810 };
4811 
4812 /* ========================================================================= */
4813 /*                    UV4H_LB_PROC_INTD_SOFT_ACK_PENDING                     */
4814 /* ========================================================================= */
4815 #define UV4H_LB_PROC_INTD_SOFT_ACK_PENDING              0xa4110UL
4816 
4817 #define UV4H_LB_PROC_INTD_SOFT_ACK_PENDING_SOFT_ACK_FLAGS_SHFT 0
4818 #define UV4H_LB_PROC_INTD_SOFT_ACK_PENDING_SOFT_ACK_FLAGS_MASK 0x00000000000000ffUL
4819 
4820 union uv4h_lb_proc_intd_soft_ack_pending_u {
4821         unsigned long   v;
4822         struct uv4h_lb_proc_intd_soft_ack_pending_s {
4823                 unsigned long   soft_ack_flags:8;               /* RW */
4824         } s4;
4825 };
4826 
4827 
4828 #endif /* _ASM_X86_UV_UV_MMRS_H */