This source file includes following definitions.
- write_mmr_data_broadcast
- write_mmr_descriptor_base
- write_mmr_activation
- write_gmmr_activation
- write_mmr_proc_payload_first
- write_mmr_proc_payload_last
- write_mmr_payload_first
- write_mmr_payload_tail
- write_mmr_payload_last
- write_mmr_misc_control
- read_mmr_misc_control
- write_mmr_sw_ack
- write_gmmr_sw_ack
- read_mmr_sw_ack
- read_gmmr_sw_ack
- write_mmr_proc_sw_ack
- write_gmmr_proc_sw_ack
- read_mmr_proc_sw_ack
- read_gmmr_proc_sw_ack
- write_mmr_data_config
- bau_uvhub_isset
- bau_uvhub_set
- bau_uvhubs_clear
- bau_uvhub_weight
- bau_cpubits_clear
- atomic_read_short
- atom_asr
- atomic_inc_unless_ge
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11 #ifndef _ASM_X86_UV_UV_BAU_H
12 #define _ASM_X86_UV_UV_BAU_H
13
14 #include <linux/bitmap.h>
15 #define BITSPERBYTE 8
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35
36 #define MAX_CPUS_PER_UVHUB 128
37 #define MAX_CPUS_PER_SOCKET 64
38 #define ADP_SZ 64
39 #define UV_CPUS_PER_AS 32
40 #define ITEMS_PER_DESC 8
41
42 #define MAX_BAU_CONCURRENT 3
43 #define UV_ACT_STATUS_MASK 0x3
44 #define UV_ACT_STATUS_SIZE 2
45 #define UV_DISTRIBUTION_SIZE 256
46 #define UV_SW_ACK_NPENDING 8
47 #define UV1_NET_ENDPOINT_INTD 0x38
48 #define UV2_NET_ENDPOINT_INTD 0x28
49 #define UV_NET_ENDPOINT_INTD (is_uv1_hub() ? \
50 UV1_NET_ENDPOINT_INTD : UV2_NET_ENDPOINT_INTD)
51 #define UV_PAYLOADQ_GNODE_SHIFT 49
52 #define UV_PTC_BASENAME "sgi_uv/ptc_statistics"
53 #define UV_BAU_BASENAME "sgi_uv/bau_tunables"
54 #define UV_BAU_TUNABLES_DIR "sgi_uv"
55 #define UV_BAU_TUNABLES_FILE "bau_tunables"
56 #define WHITESPACE " \t\n"
57 #define cpubit_isset(cpu, bau_local_cpumask) \
58 test_bit((cpu), (bau_local_cpumask).bits)
59
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62
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64
65
66
67 #define UV1_INTD_SOFT_ACK_TIMEOUT_PERIOD (9UL)
68 #define UV2_INTD_SOFT_ACK_TIMEOUT_PERIOD (15UL)
69
70 #define UV_INTD_SOFT_ACK_TIMEOUT_PERIOD (is_uv1_hub() ? \
71 UV1_INTD_SOFT_ACK_TIMEOUT_PERIOD : \
72 UV2_INTD_SOFT_ACK_TIMEOUT_PERIOD)
73
74
75 #define BAU_MISC_CONTROL_MULT_MASK 3
76
77 #define UVH_AGING_PRESCALE_SEL 0x000000b000UL
78
79 #define BAU_URGENCY_7_SHIFT 28
80 #define BAU_URGENCY_7_MASK 7
81
82 #define UVH_TRANSACTION_TIMEOUT 0x000000b200UL
83
84 #define BAU_TRANS_SHIFT 40
85 #define BAU_TRANS_MASK 0x3f
86
87
88
89
90 #define AS_PUSH_SHIFT UVH_LB_BAU_SB_ACTIVATION_CONTROL_PUSH_SHFT
91 #define SOFTACK_MSHIFT UVH_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT
92 #define SOFTACK_PSHIFT UVH_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT
93 #define SOFTACK_TIMEOUT_PERIOD UV_INTD_SOFT_ACK_TIMEOUT_PERIOD
94 #define PREFETCH_HINT_SHFT UV3H_LB_BAU_MISC_CONTROL_ENABLE_INTD_PREFETCH_HINT_SHFT
95 #define SB_STATUS_SHFT UV3H_LB_BAU_MISC_CONTROL_ENABLE_EXTENDED_SB_STATUS_SHFT
96 #define write_gmmr uv_write_global_mmr64
97 #define write_lmmr uv_write_local_mmr
98 #define read_lmmr uv_read_local_mmr
99 #define read_gmmr uv_read_global_mmr64
100
101
102
103
104 #define DS_IDLE 0
105 #define DS_ACTIVE 1
106 #define DS_DESTINATION_TIMEOUT 2
107 #define DS_SOURCE_TIMEOUT 3
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119
120 #define UV2H_DESC_IDLE 0
121 #define UV2H_DESC_BUSY 2
122 #define UV2H_DESC_DEST_TIMEOUT 4
123 #define UV2H_DESC_DEST_STRONG_NACK 5
124 #define UV2H_DESC_SOURCE_TIMEOUT 6
125 #define UV2H_DESC_DEST_PUT_ERR 7
126
127
128
129
130 #define PLUGGED_DELAY 10
131
132
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134
135
136 #define PLUGSB4RESET 100
137
138 #define TIMEOUTSB4RESET 1
139
140 #define IPI_RESET_LIMIT 1
141
142 #define COMPLETE_THRESHOLD 5
143
144
145 #define GIVEUP_LIMIT 100
146
147 #define UV_LB_SUBNODEID 0x10
148
149
150 #define UV_SA_SHFT UVH_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT
151 #define UV_SA_MASK UVH_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK
152
153 #define UV2_ACK_MASK 0x7UL
154 #define UV2_ACK_UNITS_SHFT 3
155 #define UV2_EXT_SHFT UV2H_LB_BAU_MISC_CONTROL_ENABLE_EXTENDED_SB_STATUS_SHFT
156
157
158
159
160 #define DEST_Q_SIZE 20
161
162
163
164 #define DEST_NUM_RESOURCES 8
165
166
167
168 #define FLUSH_RETRY_PLUGGED 1
169 #define FLUSH_RETRY_TIMEOUT 2
170 #define FLUSH_GIVEUP 3
171 #define FLUSH_COMPLETE 4
172
173
174
175
176 #define CONGESTED_RESPONSE_US 1000
177
178 #define CONGESTED_REPS 10
179
180 #define DISABLED_PERIOD 10
181
182
183 #define MSG_NOOP 0
184 #define MSG_REGULAR 1
185 #define MSG_RETRY 2
186
187 #define BAU_DESC_QUALIFIER 0x534749
188
189 enum uv_bau_version {
190 UV_BAU_V1 = 1,
191 UV_BAU_V2,
192 UV_BAU_V3,
193 UV_BAU_V4,
194 };
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206 struct pnmask {
207 unsigned long bits[BITS_TO_LONGS(UV_DISTRIBUTION_SIZE)];
208 };
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214
215 struct bau_local_cpumask {
216 unsigned long bits;
217 };
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239 struct uv1_2_3_bau_msg_payload {
240 u64 address;
241 u16 sending_cpu;
242 u16 acknowledge_count;
243 };
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251
252 struct uv4_bau_msg_payload {
253 u64 address;
254 u16 sending_cpu;
255 u16 acknowledge_count;
256 u32 reserved:8;
257 u32 qualifier:24;
258 };
259
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261
262
263
264 struct uv1_bau_msg_header {
265 unsigned int dest_subnodeid:6;
266
267 unsigned int base_dest_nasid:15;
268
269 unsigned int command:8;
270
271
272 unsigned int rsvd_1:3;
273
274
275 unsigned int rsvd_2:9;
276
277
278 unsigned int sequence:16;
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285 unsigned int rsvd_3:1;
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290 unsigned int replied_to:1;
291
292
293 unsigned int msg_type:3;
294
295
296 unsigned int canceled:1;
297
298
299 unsigned int payload_1a:1;
300
301 unsigned int payload_1b:2;
302
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305 unsigned int payload_1ca:6;
306
307 unsigned int payload_1c:2;
308
309
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311 unsigned int payload_1d:6;
312
313 unsigned int payload_1e:2;
314
315
316 unsigned int rsvd_4:7;
317
318 unsigned int swack_flag:1;
319
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323 unsigned int rsvd_5:6;
324
325 unsigned int rsvd_6:5;
326
327 unsigned int int_both:1;
328
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330 unsigned int fairness:3;
331
332 unsigned int multilevel:1;
333
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336 unsigned int chaining:1;
337
338
339 unsigned int rsvd_7:21;
340
341 };
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348 struct uv2_3_bau_msg_header {
349 unsigned int base_dest_nasid:15;
350
351 unsigned int dest_subnodeid:5;
352
353 unsigned int rsvd_1:1;
354
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358
359 unsigned int replied_to:1;
360
361
362 unsigned int msg_type:3;
363
364
365 unsigned int canceled:1;
366
367
368 unsigned int payload_1:3;
369
370
371
372 unsigned int payload_2a:3;
373 unsigned int payload_2b:5;
374
375
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377 unsigned int payload_3:8;
378
379
380 unsigned int rsvd_2:7;
381
382 unsigned int swack_flag:1;
383
384 unsigned int rsvd_3a:3;
385 unsigned int rsvd_3b:8;
386 unsigned int rsvd_3c:8;
387 unsigned int rsvd_3d:3;
388
389 unsigned int fairness:3;
390
391
392 unsigned int sequence:16;
393
394 unsigned int chaining:1;
395
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397 unsigned int multilevel:1;
398
399
400 unsigned int rsvd_4:24;
401
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404 unsigned int command:8;
405
406 };
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413 struct bau_desc {
414 struct pnmask distribution;
415
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418 union bau_msg_header {
419 struct uv1_bau_msg_header uv1_hdr;
420 struct uv2_3_bau_msg_header uv2_3_hdr;
421 } header;
422
423 union bau_payload_header {
424 struct uv1_2_3_bau_msg_payload uv1_2_3;
425 struct uv4_bau_msg_payload uv4;
426 } payload;
427 };
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460 struct bau_pq_entry {
461 unsigned long address;
462
463
464 unsigned short sending_cpu;
465
466 unsigned short acknowledge_count;
467
468
469 unsigned short replied_to:1;
470 unsigned short msg_type:3;
471 unsigned short canceled:1;
472 unsigned short unused1:3;
473
474 unsigned char unused2a;
475
476 unsigned char unused2;
477
478 unsigned char swack_vec;
479
480 unsigned short sequence;
481
482 unsigned char unused4[2];
483
484 int number_of_cpus;
485
486 unsigned char unused5[8];
487
488 };
489
490 struct msg_desc {
491 struct bau_pq_entry *msg;
492 int msg_slot;
493 struct bau_pq_entry *queue_first;
494 struct bau_pq_entry *queue_last;
495 };
496
497 struct reset_args {
498 int sender;
499 };
500
501
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503
504 struct ptc_stats {
505
506 unsigned long s_giveup;
507
508 unsigned long s_requestor;
509
510 unsigned long s_stimeout;
511 unsigned long s_dtimeout;
512 unsigned long s_strongnacks;
513 unsigned long s_time;
514 unsigned long s_retriesok;
515 unsigned long s_ntargcpu;
516
517 unsigned long s_ntargself;
518
519 unsigned long s_ntarglocals;
520
521 unsigned long s_ntargremotes;
522
523 unsigned long s_ntarglocaluvhub;
524 unsigned long s_ntargremoteuvhub;
525 unsigned long s_ntarguvhub;
526
527 unsigned long s_ntarguvhub16;
528
529 unsigned long s_ntarguvhub8;
530
531 unsigned long s_ntarguvhub4;
532
533 unsigned long s_ntarguvhub2;
534
535 unsigned long s_ntarguvhub1;
536
537 unsigned long s_resets_plug;
538
539 unsigned long s_resets_timeout;
540
541 unsigned long s_busy;
542
543 unsigned long s_throttles;
544 unsigned long s_retry_messages;
545 unsigned long s_bau_reenabled;
546 unsigned long s_bau_disabled;
547 unsigned long s_uv2_wars;
548 unsigned long s_uv2_wars_hw;
549 unsigned long s_uv2_war_waits;
550 unsigned long s_overipilimit;
551 unsigned long s_giveuplimit;
552 unsigned long s_enters;
553 unsigned long s_ipifordisabled;
554 unsigned long s_plugged;
555 unsigned long s_congested;
556
557 unsigned long d_alltlb;
558
559 unsigned long d_onetlb;
560
561 unsigned long d_multmsg;
562
563 unsigned long d_nomsg;
564 unsigned long d_time;
565
566 unsigned long d_requestee;
567
568 unsigned long d_retries;
569
570 unsigned long d_canceled;
571
572 unsigned long d_nocanceled;
573
574 unsigned long d_resets;
575
576 unsigned long d_rcanceled;
577
578 };
579
580 struct tunables {
581 int *tunp;
582 int deflt;
583 };
584
585 struct hub_and_pnode {
586 short uvhub;
587 short pnode;
588 };
589
590 struct socket_desc {
591 short num_cpus;
592 short cpu_number[MAX_CPUS_PER_SOCKET];
593 };
594
595 struct uvhub_desc {
596 unsigned short socket_mask;
597 short num_cpus;
598 short uvhub;
599 short pnode;
600 struct socket_desc socket[2];
601 };
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610 struct bau_control {
611 struct bau_desc *descriptor_base;
612 struct bau_pq_entry *queue_first;
613 struct bau_pq_entry *queue_last;
614 struct bau_pq_entry *bau_msg_head;
615 struct bau_control *uvhub_master;
616 struct bau_control *socket_master;
617 struct ptc_stats *statp;
618 cpumask_t *cpumask;
619 unsigned long timeout_interval;
620 unsigned long set_bau_on_time;
621 atomic_t active_descriptor_count;
622 int plugged_tries;
623 int timeout_tries;
624 int ipi_attempts;
625 int conseccompletes;
626 u64 status_mmr;
627 int status_index;
628 bool nobau;
629 short baudisabled;
630 short cpu;
631 short osnode;
632 short uvhub_cpu;
633 short uvhub;
634 short uvhub_version;
635 short cpus_in_socket;
636 short cpus_in_uvhub;
637 short partition_base_pnode;
638 short busy;
639 unsigned short message_number;
640 unsigned short uvhub_quiesce;
641 short socket_acknowledge_count[DEST_Q_SIZE];
642 cycles_t send_message;
643 cycles_t period_end;
644 cycles_t period_time;
645 spinlock_t uvhub_lock;
646 spinlock_t queue_lock;
647 spinlock_t disable_lock;
648
649 int max_concurr;
650 int max_concurr_const;
651 int plugged_delay;
652 int plugsb4reset;
653 int timeoutsb4reset;
654 int ipi_reset_limit;
655 int complete_threshold;
656 int cong_response_us;
657 int cong_reps;
658 cycles_t disabled_period;
659 int period_giveups;
660 int giveup_limit;
661 long period_requests;
662 struct hub_and_pnode *thp;
663 };
664
665
666 struct bau_operations {
667 unsigned long (*read_l_sw_ack)(void);
668 unsigned long (*read_g_sw_ack)(int pnode);
669 unsigned long (*bau_gpa_to_offset)(unsigned long vaddr);
670 void (*write_l_sw_ack)(unsigned long mmr);
671 void (*write_g_sw_ack)(int pnode, unsigned long mmr);
672 void (*write_payload_first)(int pnode, unsigned long mmr);
673 void (*write_payload_last)(int pnode, unsigned long mmr);
674 int (*wait_completion)(struct bau_desc*,
675 struct bau_control*, long try);
676 };
677
678 static inline void write_mmr_data_broadcast(int pnode, unsigned long mmr_image)
679 {
680 write_gmmr(pnode, UVH_BAU_DATA_BROADCAST, mmr_image);
681 }
682
683 static inline void write_mmr_descriptor_base(int pnode, unsigned long mmr_image)
684 {
685 write_gmmr(pnode, UVH_LB_BAU_SB_DESCRIPTOR_BASE, mmr_image);
686 }
687
688 static inline void write_mmr_activation(unsigned long index)
689 {
690 write_lmmr(UVH_LB_BAU_SB_ACTIVATION_CONTROL, index);
691 }
692
693 static inline void write_gmmr_activation(int pnode, unsigned long mmr_image)
694 {
695 write_gmmr(pnode, UVH_LB_BAU_SB_ACTIVATION_CONTROL, mmr_image);
696 }
697
698 static inline void write_mmr_proc_payload_first(int pnode, unsigned long mmr_image)
699 {
700 write_gmmr(pnode, UV4H_LB_PROC_INTD_QUEUE_FIRST, mmr_image);
701 }
702
703 static inline void write_mmr_proc_payload_last(int pnode, unsigned long mmr_image)
704 {
705 write_gmmr(pnode, UV4H_LB_PROC_INTD_QUEUE_LAST, mmr_image);
706 }
707
708 static inline void write_mmr_payload_first(int pnode, unsigned long mmr_image)
709 {
710 write_gmmr(pnode, UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST, mmr_image);
711 }
712
713 static inline void write_mmr_payload_tail(int pnode, unsigned long mmr_image)
714 {
715 write_gmmr(pnode, UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL, mmr_image);
716 }
717
718 static inline void write_mmr_payload_last(int pnode, unsigned long mmr_image)
719 {
720 write_gmmr(pnode, UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST, mmr_image);
721 }
722
723 static inline void write_mmr_misc_control(int pnode, unsigned long mmr_image)
724 {
725 write_gmmr(pnode, UVH_LB_BAU_MISC_CONTROL, mmr_image);
726 }
727
728 static inline unsigned long read_mmr_misc_control(int pnode)
729 {
730 return read_gmmr(pnode, UVH_LB_BAU_MISC_CONTROL);
731 }
732
733 static inline void write_mmr_sw_ack(unsigned long mr)
734 {
735 uv_write_local_mmr(UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS, mr);
736 }
737
738 static inline void write_gmmr_sw_ack(int pnode, unsigned long mr)
739 {
740 write_gmmr(pnode, UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS, mr);
741 }
742
743 static inline unsigned long read_mmr_sw_ack(void)
744 {
745 return read_lmmr(UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE);
746 }
747
748 static inline unsigned long read_gmmr_sw_ack(int pnode)
749 {
750 return read_gmmr(pnode, UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE);
751 }
752
753 static inline void write_mmr_proc_sw_ack(unsigned long mr)
754 {
755 uv_write_local_mmr(UV4H_LB_PROC_INTD_SOFT_ACK_CLEAR, mr);
756 }
757
758 static inline void write_gmmr_proc_sw_ack(int pnode, unsigned long mr)
759 {
760 write_gmmr(pnode, UV4H_LB_PROC_INTD_SOFT_ACK_CLEAR, mr);
761 }
762
763 static inline unsigned long read_mmr_proc_sw_ack(void)
764 {
765 return read_lmmr(UV4H_LB_PROC_INTD_SOFT_ACK_PENDING);
766 }
767
768 static inline unsigned long read_gmmr_proc_sw_ack(int pnode)
769 {
770 return read_gmmr(pnode, UV4H_LB_PROC_INTD_SOFT_ACK_PENDING);
771 }
772
773 static inline void write_mmr_data_config(int pnode, unsigned long mr)
774 {
775 uv_write_global_mmr64(pnode, UVH_BAU_DATA_CONFIG, mr);
776 }
777
778 static inline int bau_uvhub_isset(int uvhub, struct pnmask *dstp)
779 {
780 return constant_test_bit(uvhub, &dstp->bits[0]);
781 }
782 static inline void bau_uvhub_set(int pnode, struct pnmask *dstp)
783 {
784 __set_bit(pnode, &dstp->bits[0]);
785 }
786 static inline void bau_uvhubs_clear(struct pnmask *dstp,
787 int nbits)
788 {
789 bitmap_zero(&dstp->bits[0], nbits);
790 }
791 static inline int bau_uvhub_weight(struct pnmask *dstp)
792 {
793 return bitmap_weight((unsigned long *)&dstp->bits[0],
794 UV_DISTRIBUTION_SIZE);
795 }
796
797 static inline void bau_cpubits_clear(struct bau_local_cpumask *dstp, int nbits)
798 {
799 bitmap_zero(&dstp->bits, nbits);
800 }
801
802 extern void uv_bau_message_intr1(void);
803 #ifdef CONFIG_TRACING
804 #define trace_uv_bau_message_intr1 uv_bau_message_intr1
805 #endif
806 extern void uv_bau_timeout_intr1(void);
807
808 struct atomic_short {
809 short counter;
810 };
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818 static inline int atomic_read_short(const struct atomic_short *v)
819 {
820 return v->counter;
821 }
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829
830 static inline int atom_asr(short i, struct atomic_short *v)
831 {
832 short __i = i;
833 asm volatile(LOCK_PREFIX "xaddw %0, %1"
834 : "+r" (i), "+m" (v->counter)
835 : : "memory");
836 return i + __i;
837 }
838
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848
849 static inline int atomic_inc_unless_ge(spinlock_t *lock, atomic_t *v, int u)
850 {
851 spin_lock(lock);
852 if (atomic_read(v) >= u) {
853 spin_unlock(lock);
854 return 0;
855 }
856 atomic_inc(v);
857 spin_unlock(lock);
858 return 1;
859 }
860
861 #endif