root/arch/x86/include/asm/intel_punit_ipc.h

INCLUDED FROM

DEFINITIONS

1. intel_punit_ipc_simple_command
2. intel_punit_ipc_command

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 #ifndef _ASM_X86_INTEL_PUNIT_IPC_H_
   3 #define  _ASM_X86_INTEL_PUNIT_IPC_H_
   4 
   5 /*
   6  * Three types of 8bit P-Unit IPC commands are supported,
   7  * bit[7:6]: [00]: BIOS; [01]: GTD; [10]: ISPD.
   8  */
   9 typedef enum {
  10         BIOS_IPC = 0,
  11         GTDRIVER_IPC,
  12         ISPDRIVER_IPC,
  13         RESERVED_IPC,
  14 } IPC_TYPE;
  15 
  16 #define IPC_TYPE_OFFSET                 6
  17 #define IPC_PUNIT_BIOS_CMD_BASE         (BIOS_IPC << IPC_TYPE_OFFSET)
  18 #define IPC_PUNIT_GTD_CMD_BASE          (GTDDRIVER_IPC << IPC_TYPE_OFFSET)
  19 #define IPC_PUNIT_ISPD_CMD_BASE         (ISPDRIVER_IPC << IPC_TYPE_OFFSET)
  20 #define IPC_PUNIT_CMD_TYPE_MASK         (RESERVED_IPC << IPC_TYPE_OFFSET)
  21 
  22 /* BIOS => Pcode commands */
  23 #define IPC_PUNIT_BIOS_ZERO                     (IPC_PUNIT_BIOS_CMD_BASE | 0x00)
  24 #define IPC_PUNIT_BIOS_VR_INTERFACE             (IPC_PUNIT_BIOS_CMD_BASE | 0x01)
  25 #define IPC_PUNIT_BIOS_READ_PCS                 (IPC_PUNIT_BIOS_CMD_BASE | 0x02)
  26 #define IPC_PUNIT_BIOS_WRITE_PCS                (IPC_PUNIT_BIOS_CMD_BASE | 0x03)
  27 #define IPC_PUNIT_BIOS_READ_PCU_CONFIG          (IPC_PUNIT_BIOS_CMD_BASE | 0x04)
  28 #define IPC_PUNIT_BIOS_WRITE_PCU_CONFIG         (IPC_PUNIT_BIOS_CMD_BASE | 0x05)
  29 #define IPC_PUNIT_BIOS_READ_PL1_SETTING         (IPC_PUNIT_BIOS_CMD_BASE | 0x06)
  30 #define IPC_PUNIT_BIOS_WRITE_PL1_SETTING        (IPC_PUNIT_BIOS_CMD_BASE | 0x07)
  31 #define IPC_PUNIT_BIOS_TRIGGER_VDD_RAM          (IPC_PUNIT_BIOS_CMD_BASE | 0x08)
  32 #define IPC_PUNIT_BIOS_READ_TELE_INFO           (IPC_PUNIT_BIOS_CMD_BASE | 0x09)
  33 #define IPC_PUNIT_BIOS_READ_TELE_TRACE_CTRL     (IPC_PUNIT_BIOS_CMD_BASE | 0x0a)
  34 #define IPC_PUNIT_BIOS_WRITE_TELE_TRACE_CTRL    (IPC_PUNIT_BIOS_CMD_BASE | 0x0b)
  35 #define IPC_PUNIT_BIOS_READ_TELE_EVENT_CTRL     (IPC_PUNIT_BIOS_CMD_BASE | 0x0c)
  36 #define IPC_PUNIT_BIOS_WRITE_TELE_EVENT_CTRL    (IPC_PUNIT_BIOS_CMD_BASE | 0x0d)
  37 #define IPC_PUNIT_BIOS_READ_TELE_TRACE          (IPC_PUNIT_BIOS_CMD_BASE | 0x0e)
  38 #define IPC_PUNIT_BIOS_WRITE_TELE_TRACE         (IPC_PUNIT_BIOS_CMD_BASE | 0x0f)
  39 #define IPC_PUNIT_BIOS_READ_TELE_EVENT          (IPC_PUNIT_BIOS_CMD_BASE | 0x10)
  40 #define IPC_PUNIT_BIOS_WRITE_TELE_EVENT         (IPC_PUNIT_BIOS_CMD_BASE | 0x11)
  41 #define IPC_PUNIT_BIOS_READ_MODULE_TEMP         (IPC_PUNIT_BIOS_CMD_BASE | 0x12)
  42 #define IPC_PUNIT_BIOS_RESERVED                 (IPC_PUNIT_BIOS_CMD_BASE | 0x13)
  43 #define IPC_PUNIT_BIOS_READ_VOLTAGE_OVER        (IPC_PUNIT_BIOS_CMD_BASE | 0x14)
  44 #define IPC_PUNIT_BIOS_WRITE_VOLTAGE_OVER       (IPC_PUNIT_BIOS_CMD_BASE | 0x15)
  45 #define IPC_PUNIT_BIOS_READ_RATIO_OVER          (IPC_PUNIT_BIOS_CMD_BASE | 0x16)
  46 #define IPC_PUNIT_BIOS_WRITE_RATIO_OVER         (IPC_PUNIT_BIOS_CMD_BASE | 0x17)
  47 #define IPC_PUNIT_BIOS_READ_VF_GL_CTRL          (IPC_PUNIT_BIOS_CMD_BASE | 0x18)
  48 #define IPC_PUNIT_BIOS_WRITE_VF_GL_CTRL         (IPC_PUNIT_BIOS_CMD_BASE | 0x19)
  49 #define IPC_PUNIT_BIOS_READ_FM_SOC_TEMP_THRESH  (IPC_PUNIT_BIOS_CMD_BASE | 0x1a)
  50 #define IPC_PUNIT_BIOS_WRITE_FM_SOC_TEMP_THRESH (IPC_PUNIT_BIOS_CMD_BASE | 0x1b)
  51 
  52 /* GT Driver => Pcode commands */
  53 #define IPC_PUNIT_GTD_ZERO                      (IPC_PUNIT_GTD_CMD_BASE | 0x00)
  54 #define IPC_PUNIT_GTD_CONFIG                    (IPC_PUNIT_GTD_CMD_BASE | 0x01)
  55 #define IPC_PUNIT_GTD_READ_ICCP_LIC_CDYN_SCAL   (IPC_PUNIT_GTD_CMD_BASE | 0x02)
  56 #define IPC_PUNIT_GTD_WRITE_ICCP_LIC_CDYN_SCAL  (IPC_PUNIT_GTD_CMD_BASE | 0x03)
  57 #define IPC_PUNIT_GTD_GET_WM_VAL                (IPC_PUNIT_GTD_CMD_BASE | 0x06)
  58 #define IPC_PUNIT_GTD_WRITE_CONFIG_WISHREQ      (IPC_PUNIT_GTD_CMD_BASE | 0x07)
  59 #define IPC_PUNIT_GTD_READ_REQ_DUTY_CYCLE       (IPC_PUNIT_GTD_CMD_BASE | 0x16)
  60 #define IPC_PUNIT_GTD_DIS_VOL_FREQ_CHG_REQUEST  (IPC_PUNIT_GTD_CMD_BASE | 0x17)
  61 #define IPC_PUNIT_GTD_DYNA_DUTY_CYCLE_CTRL      (IPC_PUNIT_GTD_CMD_BASE | 0x1a)
  62 #define IPC_PUNIT_GTD_DYNA_DUTY_CYCLE_TUNING    (IPC_PUNIT_GTD_CMD_BASE | 0x1c)
  63 
  64 /* ISP Driver => Pcode commands */
  65 #define IPC_PUNIT_ISPD_ZERO                     (IPC_PUNIT_ISPD_CMD_BASE | 0x00)
  66 #define IPC_PUNIT_ISPD_CONFIG                   (IPC_PUNIT_ISPD_CMD_BASE | 0x01)
  67 #define IPC_PUNIT_ISPD_GET_ISP_LTR_VAL          (IPC_PUNIT_ISPD_CMD_BASE | 0x02)
  68 #define IPC_PUNIT_ISPD_ACCESS_IU_FREQ_BOUNDS    (IPC_PUNIT_ISPD_CMD_BASE | 0x03)
  69 #define IPC_PUNIT_ISPD_READ_CDYN_LEVEL          (IPC_PUNIT_ISPD_CMD_BASE | 0x04)
  70 #define IPC_PUNIT_ISPD_WRITE_CDYN_LEVEL         (IPC_PUNIT_ISPD_CMD_BASE | 0x05)
  71 
  72 /* Error codes */
  73 #define IPC_PUNIT_ERR_SUCCESS                   0
  74 #define IPC_PUNIT_ERR_INVALID_CMD               1
  75 #define IPC_PUNIT_ERR_INVALID_PARAMETER         2
  76 #define IPC_PUNIT_ERR_CMD_TIMEOUT               3
  77 #define IPC_PUNIT_ERR_CMD_LOCKED                4
  78 #define IPC_PUNIT_ERR_INVALID_VR_ID             5
  79 #define IPC_PUNIT_ERR_VR_ERR                    6
  80 
  81 #if IS_ENABLED(CONFIG_INTEL_PUNIT_IPC)
  82 
  83 int intel_punit_ipc_simple_command(int cmd, int para1, int para2);
  84 int intel_punit_ipc_command(u32 cmd, u32 para1, u32 para2, u32 *in, u32 *out);
  85 
  86 #else
  87 
  88 static inline int intel_punit_ipc_simple_command(int cmd,
  89                                                   int para1, int para2)
  90 {
  91         return -ENODEV;
  92 }
  93 
  94 static inline int intel_punit_ipc_command(u32 cmd, u32 para1, u32 para2,
  95                                           u32 *in, u32 *out)
  96 {
  97         return -ENODEV;
  98 }
  99 
 100 #endif /* CONFIG_INTEL_PUNIT_IPC */
 101 
 102 #endif