1
2 #ifndef __SVM_H
3 #define __SVM_H
4
5 #include <uapi/asm/svm.h>
6
7
8 enum {
9 INTERCEPT_INTR,
10 INTERCEPT_NMI,
11 INTERCEPT_SMI,
12 INTERCEPT_INIT,
13 INTERCEPT_VINTR,
14 INTERCEPT_SELECTIVE_CR0,
15 INTERCEPT_STORE_IDTR,
16 INTERCEPT_STORE_GDTR,
17 INTERCEPT_STORE_LDTR,
18 INTERCEPT_STORE_TR,
19 INTERCEPT_LOAD_IDTR,
20 INTERCEPT_LOAD_GDTR,
21 INTERCEPT_LOAD_LDTR,
22 INTERCEPT_LOAD_TR,
23 INTERCEPT_RDTSC,
24 INTERCEPT_RDPMC,
25 INTERCEPT_PUSHF,
26 INTERCEPT_POPF,
27 INTERCEPT_CPUID,
28 INTERCEPT_RSM,
29 INTERCEPT_IRET,
30 INTERCEPT_INTn,
31 INTERCEPT_INVD,
32 INTERCEPT_PAUSE,
33 INTERCEPT_HLT,
34 INTERCEPT_INVLPG,
35 INTERCEPT_INVLPGA,
36 INTERCEPT_IOIO_PROT,
37 INTERCEPT_MSR_PROT,
38 INTERCEPT_TASK_SWITCH,
39 INTERCEPT_FERR_FREEZE,
40 INTERCEPT_SHUTDOWN,
41 INTERCEPT_VMRUN,
42 INTERCEPT_VMMCALL,
43 INTERCEPT_VMLOAD,
44 INTERCEPT_VMSAVE,
45 INTERCEPT_STGI,
46 INTERCEPT_CLGI,
47 INTERCEPT_SKINIT,
48 INTERCEPT_RDTSCP,
49 INTERCEPT_ICEBP,
50 INTERCEPT_WBINVD,
51 INTERCEPT_MONITOR,
52 INTERCEPT_MWAIT,
53 INTERCEPT_MWAIT_COND,
54 INTERCEPT_XSETBV,
55 INTERCEPT_RDPRU,
56 };
57
58
59 struct __attribute__ ((__packed__)) vmcb_control_area {
60 u32 intercept_cr;
61 u32 intercept_dr;
62 u32 intercept_exceptions;
63 u64 intercept;
64 u8 reserved_1[40];
65 u16 pause_filter_thresh;
66 u16 pause_filter_count;
67 u64 iopm_base_pa;
68 u64 msrpm_base_pa;
69 u64 tsc_offset;
70 u32 asid;
71 u8 tlb_ctl;
72 u8 reserved_2[3];
73 u32 int_ctl;
74 u32 int_vector;
75 u32 int_state;
76 u8 reserved_3[4];
77 u32 exit_code;
78 u32 exit_code_hi;
79 u64 exit_info_1;
80 u64 exit_info_2;
81 u32 exit_int_info;
82 u32 exit_int_info_err;
83 u64 nested_ctl;
84 u64 avic_vapic_bar;
85 u8 reserved_4[8];
86 u32 event_inj;
87 u32 event_inj_err;
88 u64 nested_cr3;
89 u64 virt_ext;
90 u32 clean;
91 u32 reserved_5;
92 u64 next_rip;
93 u8 insn_len;
94 u8 insn_bytes[15];
95 u64 avic_backing_page;
96 u8 reserved_6[8];
97 u64 avic_logical_id;
98 u64 avic_physical_id;
99 u8 reserved_7[768];
100 };
101
102
103 #define TLB_CONTROL_DO_NOTHING 0
104 #define TLB_CONTROL_FLUSH_ALL_ASID 1
105 #define TLB_CONTROL_FLUSH_ASID 3
106 #define TLB_CONTROL_FLUSH_ASID_LOCAL 7
107
108 #define V_TPR_MASK 0x0f
109
110 #define V_IRQ_SHIFT 8
111 #define V_IRQ_MASK (1 << V_IRQ_SHIFT)
112
113 #define V_GIF_SHIFT 9
114 #define V_GIF_MASK (1 << V_GIF_SHIFT)
115
116 #define V_INTR_PRIO_SHIFT 16
117 #define V_INTR_PRIO_MASK (0x0f << V_INTR_PRIO_SHIFT)
118
119 #define V_IGN_TPR_SHIFT 20
120 #define V_IGN_TPR_MASK (1 << V_IGN_TPR_SHIFT)
121
122 #define V_INTR_MASKING_SHIFT 24
123 #define V_INTR_MASKING_MASK (1 << V_INTR_MASKING_SHIFT)
124
125 #define V_GIF_ENABLE_SHIFT 25
126 #define V_GIF_ENABLE_MASK (1 << V_GIF_ENABLE_SHIFT)
127
128 #define AVIC_ENABLE_SHIFT 31
129 #define AVIC_ENABLE_MASK (1 << AVIC_ENABLE_SHIFT)
130
131 #define LBR_CTL_ENABLE_MASK BIT_ULL(0)
132 #define VIRTUAL_VMLOAD_VMSAVE_ENABLE_MASK BIT_ULL(1)
133
134 #define SVM_INTERRUPT_SHADOW_MASK 1
135
136 #define SVM_IOIO_STR_SHIFT 2
137 #define SVM_IOIO_REP_SHIFT 3
138 #define SVM_IOIO_SIZE_SHIFT 4
139 #define SVM_IOIO_ASIZE_SHIFT 7
140
141 #define SVM_IOIO_TYPE_MASK 1
142 #define SVM_IOIO_STR_MASK (1 << SVM_IOIO_STR_SHIFT)
143 #define SVM_IOIO_REP_MASK (1 << SVM_IOIO_REP_SHIFT)
144 #define SVM_IOIO_SIZE_MASK (7 << SVM_IOIO_SIZE_SHIFT)
145 #define SVM_IOIO_ASIZE_MASK (7 << SVM_IOIO_ASIZE_SHIFT)
146
147 #define SVM_VM_CR_VALID_MASK 0x001fULL
148 #define SVM_VM_CR_SVM_LOCK_MASK 0x0008ULL
149 #define SVM_VM_CR_SVM_DIS_MASK 0x0010ULL
150
151 #define SVM_NESTED_CTL_NP_ENABLE BIT(0)
152 #define SVM_NESTED_CTL_SEV_ENABLE BIT(1)
153
154 struct __attribute__ ((__packed__)) vmcb_seg {
155 u16 selector;
156 u16 attrib;
157 u32 limit;
158 u64 base;
159 };
160
161 struct __attribute__ ((__packed__)) vmcb_save_area {
162 struct vmcb_seg es;
163 struct vmcb_seg cs;
164 struct vmcb_seg ss;
165 struct vmcb_seg ds;
166 struct vmcb_seg fs;
167 struct vmcb_seg gs;
168 struct vmcb_seg gdtr;
169 struct vmcb_seg ldtr;
170 struct vmcb_seg idtr;
171 struct vmcb_seg tr;
172 u8 reserved_1[43];
173 u8 cpl;
174 u8 reserved_2[4];
175 u64 efer;
176 u8 reserved_3[112];
177 u64 cr4;
178 u64 cr3;
179 u64 cr0;
180 u64 dr7;
181 u64 dr6;
182 u64 rflags;
183 u64 rip;
184 u8 reserved_4[88];
185 u64 rsp;
186 u8 reserved_5[24];
187 u64 rax;
188 u64 star;
189 u64 lstar;
190 u64 cstar;
191 u64 sfmask;
192 u64 kernel_gs_base;
193 u64 sysenter_cs;
194 u64 sysenter_esp;
195 u64 sysenter_eip;
196 u64 cr2;
197 u8 reserved_6[32];
198 u64 g_pat;
199 u64 dbgctl;
200 u64 br_from;
201 u64 br_to;
202 u64 last_excp_from;
203 u64 last_excp_to;
204 };
205
206 struct __attribute__ ((__packed__)) vmcb {
207 struct vmcb_control_area control;
208 struct vmcb_save_area save;
209 };
210
211 #define SVM_CPUID_FUNC 0x8000000a
212
213 #define SVM_VM_CR_SVM_DISABLE 4
214
215 #define SVM_SELECTOR_S_SHIFT 4
216 #define SVM_SELECTOR_DPL_SHIFT 5
217 #define SVM_SELECTOR_P_SHIFT 7
218 #define SVM_SELECTOR_AVL_SHIFT 8
219 #define SVM_SELECTOR_L_SHIFT 9
220 #define SVM_SELECTOR_DB_SHIFT 10
221 #define SVM_SELECTOR_G_SHIFT 11
222
223 #define SVM_SELECTOR_TYPE_MASK (0xf)
224 #define SVM_SELECTOR_S_MASK (1 << SVM_SELECTOR_S_SHIFT)
225 #define SVM_SELECTOR_DPL_MASK (3 << SVM_SELECTOR_DPL_SHIFT)
226 #define SVM_SELECTOR_P_MASK (1 << SVM_SELECTOR_P_SHIFT)
227 #define SVM_SELECTOR_AVL_MASK (1 << SVM_SELECTOR_AVL_SHIFT)
228 #define SVM_SELECTOR_L_MASK (1 << SVM_SELECTOR_L_SHIFT)
229 #define SVM_SELECTOR_DB_MASK (1 << SVM_SELECTOR_DB_SHIFT)
230 #define SVM_SELECTOR_G_MASK (1 << SVM_SELECTOR_G_SHIFT)
231
232 #define SVM_SELECTOR_WRITE_MASK (1 << 1)
233 #define SVM_SELECTOR_READ_MASK SVM_SELECTOR_WRITE_MASK
234 #define SVM_SELECTOR_CODE_MASK (1 << 3)
235
236 #define INTERCEPT_CR0_READ 0
237 #define INTERCEPT_CR3_READ 3
238 #define INTERCEPT_CR4_READ 4
239 #define INTERCEPT_CR8_READ 8
240 #define INTERCEPT_CR0_WRITE (16 + 0)
241 #define INTERCEPT_CR3_WRITE (16 + 3)
242 #define INTERCEPT_CR4_WRITE (16 + 4)
243 #define INTERCEPT_CR8_WRITE (16 + 8)
244
245 #define INTERCEPT_DR0_READ 0
246 #define INTERCEPT_DR1_READ 1
247 #define INTERCEPT_DR2_READ 2
248 #define INTERCEPT_DR3_READ 3
249 #define INTERCEPT_DR4_READ 4
250 #define INTERCEPT_DR5_READ 5
251 #define INTERCEPT_DR6_READ 6
252 #define INTERCEPT_DR7_READ 7
253 #define INTERCEPT_DR0_WRITE (16 + 0)
254 #define INTERCEPT_DR1_WRITE (16 + 1)
255 #define INTERCEPT_DR2_WRITE (16 + 2)
256 #define INTERCEPT_DR3_WRITE (16 + 3)
257 #define INTERCEPT_DR4_WRITE (16 + 4)
258 #define INTERCEPT_DR5_WRITE (16 + 5)
259 #define INTERCEPT_DR6_WRITE (16 + 6)
260 #define INTERCEPT_DR7_WRITE (16 + 7)
261
262 #define SVM_EVTINJ_VEC_MASK 0xff
263
264 #define SVM_EVTINJ_TYPE_SHIFT 8
265 #define SVM_EVTINJ_TYPE_MASK (7 << SVM_EVTINJ_TYPE_SHIFT)
266
267 #define SVM_EVTINJ_TYPE_INTR (0 << SVM_EVTINJ_TYPE_SHIFT)
268 #define SVM_EVTINJ_TYPE_NMI (2 << SVM_EVTINJ_TYPE_SHIFT)
269 #define SVM_EVTINJ_TYPE_EXEPT (3 << SVM_EVTINJ_TYPE_SHIFT)
270 #define SVM_EVTINJ_TYPE_SOFT (4 << SVM_EVTINJ_TYPE_SHIFT)
271
272 #define SVM_EVTINJ_VALID (1 << 31)
273 #define SVM_EVTINJ_VALID_ERR (1 << 11)
274
275 #define SVM_EXITINTINFO_VEC_MASK SVM_EVTINJ_VEC_MASK
276 #define SVM_EXITINTINFO_TYPE_MASK SVM_EVTINJ_TYPE_MASK
277
278 #define SVM_EXITINTINFO_TYPE_INTR SVM_EVTINJ_TYPE_INTR
279 #define SVM_EXITINTINFO_TYPE_NMI SVM_EVTINJ_TYPE_NMI
280 #define SVM_EXITINTINFO_TYPE_EXEPT SVM_EVTINJ_TYPE_EXEPT
281 #define SVM_EXITINTINFO_TYPE_SOFT SVM_EVTINJ_TYPE_SOFT
282
283 #define SVM_EXITINTINFO_VALID SVM_EVTINJ_VALID
284 #define SVM_EXITINTINFO_VALID_ERR SVM_EVTINJ_VALID_ERR
285
286 #define SVM_EXITINFOSHIFT_TS_REASON_IRET 36
287 #define SVM_EXITINFOSHIFT_TS_REASON_JMP 38
288 #define SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE 44
289
290 #define SVM_EXITINFO_REG_MASK 0x0F
291
292 #define SVM_CR0_SELECTIVE_MASK (X86_CR0_TS | X86_CR0_MP)
293
294 #endif