root/arch/x86/include/asm/intel_pmc_ipc.h

INCLUDED FROM

DEFINITIONS

1. intel_pmc_ipc_simple_command
2. intel_pmc_ipc_raw_cmd
3. intel_pmc_ipc_command
4. intel_pmc_s0ix_counter_read
5. intel_pmc_gcr_read
6. intel_pmc_gcr_read64
7. intel_pmc_gcr_write
8. intel_pmc_gcr_update

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 #ifndef _ASM_X86_INTEL_PMC_IPC_H_
   3 #define  _ASM_X86_INTEL_PMC_IPC_H_
   4 
   5 /* Commands */
   6 #define PMC_IPC_PMIC_ACCESS             0xFF
   7 #define         PMC_IPC_PMIC_ACCESS_READ        0x0
   8 #define         PMC_IPC_PMIC_ACCESS_WRITE       0x1
   9 #define PMC_IPC_USB_PWR_CTRL            0xF0
  10 #define PMC_IPC_PMIC_BLACKLIST_SEL      0xEF
  11 #define PMC_IPC_PHY_CONFIG              0xEE
  12 #define PMC_IPC_NORTHPEAK_CTRL          0xED
  13 #define PMC_IPC_PM_DEBUG                0xEC
  14 #define PMC_IPC_PMC_TELEMTRY            0xEB
  15 #define PMC_IPC_PMC_FW_MSG_CTRL         0xEA
  16 
  17 /* IPC return code */
  18 #define IPC_ERR_NONE                    0
  19 #define IPC_ERR_CMD_NOT_SUPPORTED       1
  20 #define IPC_ERR_CMD_NOT_SERVICED        2
  21 #define IPC_ERR_UNABLE_TO_SERVICE       3
  22 #define IPC_ERR_CMD_INVALID             4
  23 #define IPC_ERR_CMD_FAILED              5
  24 #define IPC_ERR_EMSECURITY              6
  25 #define IPC_ERR_UNSIGNEDKERNEL          7
  26 
  27 /* GCR reg offsets from gcr base*/
  28 #define PMC_GCR_PMC_CFG_REG             0x08
  29 #define PMC_GCR_TELEM_DEEP_S0IX_REG     0x78
  30 #define PMC_GCR_TELEM_SHLW_S0IX_REG     0x80
  31 
  32 #if IS_ENABLED(CONFIG_INTEL_PMC_IPC)
  33 
  34 int intel_pmc_ipc_simple_command(int cmd, int sub);
  35 int intel_pmc_ipc_raw_cmd(u32 cmd, u32 sub, u8 *in, u32 inlen,
  36                 u32 *out, u32 outlen, u32 dptr, u32 sptr);
  37 int intel_pmc_ipc_command(u32 cmd, u32 sub, u8 *in, u32 inlen,
  38                 u32 *out, u32 outlen);
  39 int intel_pmc_s0ix_counter_read(u64 *data);
  40 int intel_pmc_gcr_read(u32 offset, u32 *data);
  41 int intel_pmc_gcr_read64(u32 offset, u64 *data);
  42 int intel_pmc_gcr_write(u32 offset, u32 data);
  43 int intel_pmc_gcr_update(u32 offset, u32 mask, u32 val);
  44 
  45 #else
  46 
  47 static inline int intel_pmc_ipc_simple_command(int cmd, int sub)
  48 {
  49         return -EINVAL;
  50 }
  51 
  52 static inline int intel_pmc_ipc_raw_cmd(u32 cmd, u32 sub, u8 *in, u32 inlen,
  53                 u32 *out, u32 outlen, u32 dptr, u32 sptr)
  54 {
  55         return -EINVAL;
  56 }
  57 
  58 static inline int intel_pmc_ipc_command(u32 cmd, u32 sub, u8 *in, u32 inlen,
  59                 u32 *out, u32 outlen)
  60 {
  61         return -EINVAL;
  62 }
  63 
  64 static inline int intel_pmc_s0ix_counter_read(u64 *data)
  65 {
  66         return -EINVAL;
  67 }
  68 
  69 static inline int intel_pmc_gcr_read(u32 offset, u32 *data)
  70 {
  71         return -EINVAL;
  72 }
  73 
  74 static inline int intel_pmc_gcr_read64(u32 offset, u64 *data)
  75 {
  76         return -EINVAL;
  77 }
  78 
  79 static inline int intel_pmc_gcr_write(u32 offset, u32 data)
  80 {
  81         return -EINVAL;
  82 }
  83 
  84 static inline int intel_pmc_gcr_update(u32 offset, u32 mask, u32 val)
  85 {
  86         return -EINVAL;
  87 }
  88 
  89 #endif /*CONFIG_INTEL_PMC_IPC*/
  90 
  91 #endif