arch/x86/pci/irq.c

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This source file includes following definitions.
pirq_check_routing_table
pirq_find_routing_table
pirq_peer_trick
elcr_set_level_irq
read_config_nybble
write_config_nybble
pirq_ali_get
pirq_ali_set
pirq_piix_get
pirq_piix_set
pirq_via_get
pirq_via_set
pirq_via586_get
pirq_via586_set
pirq_ite_get
pirq_ite_set
pirq_opti_get
pirq_opti_set
pirq_cyrix_get
pirq_cyrix_set
pirq_sis_get
pirq_sis_set
pirq_vlsi_get
pirq_vlsi_set
pirq_serverworks_get
pirq_serverworks_set
pirq_amd756_get
pirq_amd756_set
pirq_pico_get
pirq_pico_set
pirq_bios_set
intel_router_probe
via_router_probe
vlsi_router_probe
serverworks_router_probe
sis_router_probe
cyrix_router_probe
opti_router_probe
ite_router_probe
ali_router_probe
amd_router_probe
pico_router_probe
pirq_find_router
pirq_get_info
pcibios_lookup_irq
pcibios_fixup_irqs
fix_broken_hp_bios_irq9
fix_acer_tm360_irqrouting
pcibios_irq_init
pirq_penalize_isa_irq
pcibios_penalize_isa_irq
pirq_enable_irq
mp_should_keep_irq
pirq_disable_irq
   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  *      Low-Level PCI Support for PC -- Routing of Interrupts
   4  *
   5  *      (c) 1999--2000 Martin Mares <mj@ucw.cz>
   6  */
   7 
   8 #include <linux/types.h>
   9 #include <linux/kernel.h>
  10 #include <linux/pci.h>
  11 #include <linux/init.h>
  12 #include <linux/interrupt.h>
  13 #include <linux/dmi.h>
  14 #include <linux/io.h>
  15 #include <linux/smp.h>
  16 #include <asm/io_apic.h>
  17 #include <linux/irq.h>
  18 #include <linux/acpi.h>
  19 #include <asm/pci_x86.h>
  20 
  21 #define PIRQ_SIGNATURE  (('$' << 0) + ('P' << 8) + ('I' << 16) + ('R' << 24))
  22 #define PIRQ_VERSION 0x0100
  23 
  24 static int broken_hp_bios_irq9;
  25 static int acer_tm360_irqrouting;
  26 
  27 static struct irq_routing_table *pirq_table;
  28 
  29 static int pirq_enable_irq(struct pci_dev *dev);
  30 static void pirq_disable_irq(struct pci_dev *dev);
  31 
  32 /*
  33  * Never use: 0, 1, 2 (timer, keyboard, and cascade)
  34  * Avoid using: 13, 14 and 15 (FP error and IDE).
  35  * Penalize: 3, 4, 6, 7, 12 (known ISA uses: serial, floppy, parallel and mouse)
  36  */
  37 unsigned int pcibios_irq_mask = 0xfff8;
  38 
  39 static int pirq_penalty[16] = {
  40         1000000, 1000000, 1000000, 1000, 1000, 0, 1000, 1000,
  41         0, 0, 0, 0, 1000, 100000, 100000, 100000
  42 };
  43 
  44 struct irq_router {
  45         char *name;
  46         u16 vendor, device;
  47         int (*get)(struct pci_dev *router, struct pci_dev *dev, int pirq);
  48         int (*set)(struct pci_dev *router, struct pci_dev *dev, int pirq,
  49                 int new);
  50 };
  51 
  52 struct irq_router_handler {
  53         u16 vendor;
  54         int (*probe)(struct irq_router *r, struct pci_dev *router, u16 device);
  55 };
  56 
  57 int (*pcibios_enable_irq)(struct pci_dev *dev) = pirq_enable_irq;
  58 void (*pcibios_disable_irq)(struct pci_dev *dev) = pirq_disable_irq;
  59 
  60 /*
  61  *  Check passed address for the PCI IRQ Routing Table signature
  62  *  and perform checksum verification.
  63  */
  64 
  65 static inline struct irq_routing_table *pirq_check_routing_table(u8 *addr)
  66 {
  67         struct irq_routing_table *rt;
  68         int i;
  69         u8 sum;
  70 
  71         rt = (struct irq_routing_table *) addr;
  72         if (rt->signature != PIRQ_SIGNATURE ||
  73             rt->version != PIRQ_VERSION ||
  74             rt->size % 16 ||
  75             rt->size < sizeof(struct irq_routing_table))
  76                 return NULL;
  77         sum = 0;
  78         for (i = 0; i < rt->size; i++)
  79                 sum += addr[i];
  80         if (!sum) {
  81                 DBG(KERN_DEBUG "PCI: Interrupt Routing Table found at 0x%p\n",
  82                         rt);
  83                 return rt;
  84         }
  85         return NULL;
  86 }
  87 
  88 
  89 
  90 /*
  91  *  Search 0xf0000 -- 0xfffff for the PCI IRQ Routing Table.
  92  */
  93 
  94 static struct irq_routing_table * __init pirq_find_routing_table(void)
  95 {
  96         u8 *addr;
  97         struct irq_routing_table *rt;
  98 
  99         if (pirq_table_addr) {
 100                 rt = pirq_check_routing_table((u8 *) __va(pirq_table_addr));
 101                 if (rt)
 102                         return rt;
 103                 printk(KERN_WARNING "PCI: PIRQ table NOT found at pirqaddr\n");
 104         }
 105         for (addr = (u8 *) __va(0xf0000); addr < (u8 *) __va(0x100000); addr += 16) {
 106                 rt = pirq_check_routing_table(addr);
 107                 if (rt)
 108                         return rt;
 109         }
 110         return NULL;
 111 }
 112 
 113 /*
 114  *  If we have a IRQ routing table, use it to search for peer host
 115  *  bridges.  It's a gross hack, but since there are no other known
 116  *  ways how to get a list of buses, we have to go this way.
 117  */
 118 
 119 static void __init pirq_peer_trick(void)
 120 {
 121         struct irq_routing_table *rt = pirq_table;
 122         u8 busmap[256];
 123         int i;
 124         struct irq_info *e;
 125 
 126         memset(busmap, 0, sizeof(busmap));
 127         for (i = 0; i < (rt->size - sizeof(struct irq_routing_table)) / sizeof(struct irq_info); i++) {
 128                 e = &rt->slots[i];
 129 #ifdef DEBUG
 130                 {
 131                         int j;
 132                         DBG(KERN_DEBUG "%02x:%02x slot=%02x", e->bus, e->devfn/8, e->slot);
 133                         for (j = 0; j < 4; j++)
 134                                 DBG(" %d:%02x/%04x", j, e->irq[j].link, e->irq[j].bitmap);
 135                         DBG("\n");
 136                 }
 137 #endif
 138                 busmap[e->bus] = 1;
 139         }
 140         for (i = 1; i < 256; i++) {
 141                 if (!busmap[i] || pci_find_bus(0, i))
 142                         continue;
 143                 pcibios_scan_root(i);
 144         }
 145         pcibios_last_bus = -1;
 146 }
 147 
 148 /*
 149  *  Code for querying and setting of IRQ routes on various interrupt routers.
 150  *  PIC Edge/Level Control Registers (ELCR) 0x4d0 & 0x4d1.
 151  */
 152 
 153 void elcr_set_level_irq(unsigned int irq)
 154 {
 155         unsigned char mask = 1 << (irq & 7);
 156         unsigned int port = 0x4d0 + (irq >> 3);
 157         unsigned char val;
 158         static u16 elcr_irq_mask;
 159 
 160         if (irq >= 16 || (1 << irq) & elcr_irq_mask)
 161                 return;
 162 
 163         elcr_irq_mask |= (1 << irq);
 164         printk(KERN_DEBUG "PCI: setting IRQ %u as level-triggered\n", irq);
 165         val = inb(port);
 166         if (!(val & mask)) {
 167                 DBG(KERN_DEBUG " -> edge");
 168                 outb(val | mask, port);
 169         }
 170 }
 171 
 172 /*
 173  * Common IRQ routing practice: nibbles in config space,
 174  * offset by some magic constant.
 175  */
 176 static unsigned int read_config_nybble(struct pci_dev *router, unsigned offset, unsigned nr)
 177 {
 178         u8 x;
 179         unsigned reg = offset + (nr >> 1);
 180 
 181         pci_read_config_byte(router, reg, &x);
 182         return (nr & 1) ? (x >> 4) : (x & 0xf);
 183 }
 184 
 185 static void write_config_nybble(struct pci_dev *router, unsigned offset,
 186         unsigned nr, unsigned int val)
 187 {
 188         u8 x;
 189         unsigned reg = offset + (nr >> 1);
 190 
 191         pci_read_config_byte(router, reg, &x);
 192         x = (nr & 1) ? ((x & 0x0f) | (val << 4)) : ((x & 0xf0) | val);
 193         pci_write_config_byte(router, reg, x);
 194 }
 195 
 196 /*
 197  * ALI pirq entries are damn ugly, and completely undocumented.
 198  * This has been figured out from pirq tables, and it's not a pretty
 199  * picture.
 200  */
 201 static int pirq_ali_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
 202 {
 203         static const unsigned char irqmap[16] = { 0, 9, 3, 10, 4, 5, 7, 6, 1, 11, 0, 12, 0, 14, 0, 15 };
 204 
 205         WARN_ON_ONCE(pirq > 16);
 206         return irqmap[read_config_nybble(router, 0x48, pirq-1)];
 207 }
 208 
 209 static int pirq_ali_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
 210 {
 211         static const unsigned char irqmap[16] = { 0, 8, 0, 2, 4, 5, 7, 6, 0, 1, 3, 9, 11, 0, 13, 15 };
 212         unsigned int val = irqmap[irq];
 213 
 214         WARN_ON_ONCE(pirq > 16);
 215         if (val) {
 216                 write_config_nybble(router, 0x48, pirq-1, val);
 217                 return 1;
 218         }
 219         return 0;
 220 }
 221 
 222 /*
 223  * The Intel PIIX4 pirq rules are fairly simple: "pirq" is
 224  * just a pointer to the config space.
 225  */
 226 static int pirq_piix_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
 227 {
 228         u8 x;
 229 
 230         pci_read_config_byte(router, pirq, &x);
 231         return (x < 16) ? x : 0;
 232 }
 233 
 234 static int pirq_piix_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
 235 {
 236         pci_write_config_byte(router, pirq, irq);
 237         return 1;
 238 }
 239 
 240 /*
 241  * The VIA pirq rules are nibble-based, like ALI,
 242  * but without the ugly irq number munging.
 243  * However, PIRQD is in the upper instead of lower 4 bits.
 244  */
 245 static int pirq_via_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
 246 {
 247         return read_config_nybble(router, 0x55, pirq == 4 ? 5 : pirq);
 248 }
 249 
 250 static int pirq_via_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
 251 {
 252         write_config_nybble(router, 0x55, pirq == 4 ? 5 : pirq, irq);
 253         return 1;
 254 }
 255 
 256 /*
 257  * The VIA pirq rules are nibble-based, like ALI,
 258  * but without the ugly irq number munging.
 259  * However, for 82C586, nibble map is different .
 260  */
 261 static int pirq_via586_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
 262 {
 263         static const unsigned int pirqmap[5] = { 3, 2, 5, 1, 1 };
 264 
 265         WARN_ON_ONCE(pirq > 5);
 266         return read_config_nybble(router, 0x55, pirqmap[pirq-1]);
 267 }
 268 
 269 static int pirq_via586_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
 270 {
 271         static const unsigned int pirqmap[5] = { 3, 2, 5, 1, 1 };
 272 
 273         WARN_ON_ONCE(pirq > 5);
 274         write_config_nybble(router, 0x55, pirqmap[pirq-1], irq);
 275         return 1;
 276 }
 277 
 278 /*
 279  * ITE 8330G pirq rules are nibble-based
 280  * FIXME: pirqmap may be { 1, 0, 3, 2 },
 281  *        2+3 are both mapped to irq 9 on my system
 282  */
 283 static int pirq_ite_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
 284 {
 285         static const unsigned char pirqmap[4] = { 1, 0, 2, 3 };
 286 
 287         WARN_ON_ONCE(pirq > 4);
 288         return read_config_nybble(router, 0x43, pirqmap[pirq-1]);
 289 }
 290 
 291 static int pirq_ite_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
 292 {
 293         static const unsigned char pirqmap[4] = { 1, 0, 2, 3 };
 294 
 295         WARN_ON_ONCE(pirq > 4);
 296         write_config_nybble(router, 0x43, pirqmap[pirq-1], irq);
 297         return 1;
 298 }
 299 
 300 /*
 301  * OPTI: high four bits are nibble pointer..
 302  * I wonder what the low bits do?
 303  */
 304 static int pirq_opti_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
 305 {
 306         return read_config_nybble(router, 0xb8, pirq >> 4);
 307 }
 308 
 309 static int pirq_opti_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
 310 {
 311         write_config_nybble(router, 0xb8, pirq >> 4, irq);
 312         return 1;
 313 }
 314 
 315 /*
 316  * Cyrix: nibble offset 0x5C
 317  * 0x5C bits 7:4 is INTB bits 3:0 is INTA
 318  * 0x5D bits 7:4 is INTD bits 3:0 is INTC
 319  */
 320 static int pirq_cyrix_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
 321 {
 322         return read_config_nybble(router, 0x5C, (pirq-1)^1);
 323 }
 324 
 325 static int pirq_cyrix_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
 326 {
 327         write_config_nybble(router, 0x5C, (pirq-1)^1, irq);
 328         return 1;
 329 }
 330 
 331 /*
 332  *      PIRQ routing for SiS 85C503 router used in several SiS chipsets.
 333  *      We have to deal with the following issues here:
 334  *      - vendors have different ideas about the meaning of link values
 335  *      - some onboard devices (integrated in the chipset) have special
 336  *        links and are thus routed differently (i.e. not via PCI INTA-INTD)
 337  *      - different revision of the router have a different layout for
 338  *        the routing registers, particularly for the onchip devices
 339  *
 340  *      For all routing registers the common thing is we have one byte
 341  *      per routeable link which is defined as:
 342  *               bit 7      IRQ mapping enabled (0) or disabled (1)
 343  *               bits [6:4] reserved (sometimes used for onchip devices)
 344  *               bits [3:0] IRQ to map to
 345  *                   allowed: 3-7, 9-12, 14-15
 346  *                   reserved: 0, 1, 2, 8, 13
 347  *
 348  *      The config-space registers located at 0x41/0x42/0x43/0x44 are
 349  *      always used to route the normal PCI INT A/B/C/D respectively.
 350  *      Apparently there are systems implementing PCI routing table using
 351  *      link values 0x01-0x04 and others using 0x41-0x44 for PCI INTA..D.
 352  *      We try our best to handle both link mappings.
 353  *
 354  *      Currently (2003-05-21) it appears most SiS chipsets follow the
 355  *      definition of routing registers from the SiS-5595 southbridge.
 356  *      According to the SiS 5595 datasheets the revision id's of the
 357  *      router (ISA-bridge) should be 0x01 or 0xb0.
 358  *
 359  *      Furthermore we've also seen lspci dumps with revision 0x00 and 0xb1.
 360  *      Looks like these are used in a number of SiS 5xx/6xx/7xx chipsets.
 361  *      They seem to work with the current routing code. However there is
 362  *      some concern because of the two USB-OHCI HCs (original SiS 5595
 363  *      had only one). YMMV.
 364  *
 365  *      Onchip routing for router rev-id 0x01/0xb0 and probably 0x00/0xb1:
 366  *
 367  *      0x61:   IDEIRQ:
 368  *              bits [6:5] must be written 01
 369  *              bit 4 channel-select primary (0), secondary (1)
 370  *
 371  *      0x62:   USBIRQ:
 372  *              bit 6 OHCI function disabled (0), enabled (1)
 373  *
 374  *      0x6a:   ACPI/SCI IRQ: bits 4-6 reserved
 375  *
 376  *      0x7e:   Data Acq. Module IRQ - bits 4-6 reserved
 377  *
 378  *      We support USBIRQ (in addition to INTA-INTD) and keep the
 379  *      IDE, ACPI and DAQ routing untouched as set by the BIOS.
 380  *
 381  *      Currently the only reported exception is the new SiS 65x chipset
 382  *      which includes the SiS 69x southbridge. Here we have the 85C503
 383  *      router revision 0x04 and there are changes in the register layout
 384  *      mostly related to the different USB HCs with USB 2.0 support.
 385  *
 386  *      Onchip routing for router rev-id 0x04 (try-and-error observation)
 387  *
 388  *      0x60/0x61/0x62/0x63:    1xEHCI and 3xOHCI (companion) USB-HCs
 389  *                              bit 6-4 are probably unused, not like 5595
 390  */
 391 
 392 #define PIRQ_SIS_IRQ_MASK       0x0f
 393 #define PIRQ_SIS_IRQ_DISABLE    0x80
 394 #define PIRQ_SIS_USB_ENABLE     0x40
 395 
 396 static int pirq_sis_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
 397 {
 398         u8 x;
 399         int reg;
 400 
 401         reg = pirq;
 402         if (reg >= 0x01 && reg <= 0x04)
 403                 reg += 0x40;
 404         pci_read_config_byte(router, reg, &x);
 405         return (x & PIRQ_SIS_IRQ_DISABLE) ? 0 : (x & PIRQ_SIS_IRQ_MASK);
 406 }
 407 
 408 static int pirq_sis_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
 409 {
 410         u8 x;
 411         int reg;
 412 
 413         reg = pirq;
 414         if (reg >= 0x01 && reg <= 0x04)
 415                 reg += 0x40;
 416         pci_read_config_byte(router, reg, &x);
 417         x &= ~(PIRQ_SIS_IRQ_MASK | PIRQ_SIS_IRQ_DISABLE);
 418         x |= irq ? irq: PIRQ_SIS_IRQ_DISABLE;
 419         pci_write_config_byte(router, reg, x);
 420         return 1;
 421 }
 422 
 423 
 424 /*
 425  * VLSI: nibble offset 0x74 - educated guess due to routing table and
 426  *       config space of VLSI 82C534 PCI-bridge/router (1004:0102)
 427  *       Tested on HP OmniBook 800 covering PIRQ 1, 2, 4, 8 for onboard
 428  *       devices, PIRQ 3 for non-pci(!) soundchip and (untested) PIRQ 6
 429  *       for the busbridge to the docking station.
 430  */
 431 
 432 static int pirq_vlsi_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
 433 {
 434         WARN_ON_ONCE(pirq >= 9);
 435         if (pirq > 8) {
 436                 dev_info(&dev->dev, "VLSI router PIRQ escape (%d)\n", pirq);
 437                 return 0;
 438         }
 439         return read_config_nybble(router, 0x74, pirq-1);
 440 }
 441 
 442 static int pirq_vlsi_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
 443 {
 444         WARN_ON_ONCE(pirq >= 9);
 445         if (pirq > 8) {
 446                 dev_info(&dev->dev, "VLSI router PIRQ escape (%d)\n", pirq);
 447                 return 0;
 448         }
 449         write_config_nybble(router, 0x74, pirq-1, irq);
 450         return 1;
 451 }
 452 
 453 /*
 454  * ServerWorks: PCI interrupts mapped to system IRQ lines through Index
 455  * and Redirect I/O registers (0x0c00 and 0x0c01).  The Index register
 456  * format is (PCIIRQ## | 0x10), e.g.: PCIIRQ10=0x1a.  The Redirect
 457  * register is a straight binary coding of desired PIC IRQ (low nibble).
 458  *
 459  * The 'link' value in the PIRQ table is already in the correct format
 460  * for the Index register.  There are some special index values:
 461  * 0x00 for ACPI (SCI), 0x01 for USB, 0x02 for IDE0, 0x04 for IDE1,
 462  * and 0x03 for SMBus.
 463  */
 464 static int pirq_serverworks_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
 465 {
 466         outb(pirq, 0xc00);
 467         return inb(0xc01) & 0xf;
 468 }
 469 
 470 static int pirq_serverworks_set(struct pci_dev *router, struct pci_dev *dev,
 471         int pirq, int irq)
 472 {
 473         outb(pirq, 0xc00);
 474         outb(irq, 0xc01);
 475         return 1;
 476 }
 477 
 478 /* Support for AMD756 PCI IRQ Routing
 479  * Jhon H. Caicedo <jhcaiced@osso.org.co>
 480  * Jun/21/2001 0.2.0 Release, fixed to use "nybble" functions... (jhcaiced)
 481  * Jun/19/2001 Alpha Release 0.1.0 (jhcaiced)
 482  * The AMD756 pirq rules are nibble-based
 483  * offset 0x56 0-3 PIRQA  4-7  PIRQB
 484  * offset 0x57 0-3 PIRQC  4-7  PIRQD
 485  */
 486 static int pirq_amd756_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
 487 {
 488         u8 irq;
 489         irq = 0;
 490         if (pirq <= 4)
 491                 irq = read_config_nybble(router, 0x56, pirq - 1);
 492         dev_info(&dev->dev,
 493                  "AMD756: dev [%04x:%04x], router PIRQ %d get IRQ %d\n",
 494                  dev->vendor, dev->device, pirq, irq);
 495         return irq;
 496 }
 497 
 498 static int pirq_amd756_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
 499 {
 500         dev_info(&dev->dev,
 501                  "AMD756: dev [%04x:%04x], router PIRQ %d set IRQ %d\n",
 502                  dev->vendor, dev->device, pirq, irq);
 503         if (pirq <= 4)
 504                 write_config_nybble(router, 0x56, pirq - 1, irq);
 505         return 1;
 506 }
 507 
 508 /*
 509  * PicoPower PT86C523
 510  */
 511 static int pirq_pico_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
 512 {
 513         outb(0x10 + ((pirq - 1) >> 1), 0x24);
 514         return ((pirq - 1) & 1) ? (inb(0x26) >> 4) : (inb(0x26) & 0xf);
 515 }
 516 
 517 static int pirq_pico_set(struct pci_dev *router, struct pci_dev *dev, int pirq,
 518                         int irq)
 519 {
 520         unsigned int x;
 521         outb(0x10 + ((pirq - 1) >> 1), 0x24);
 522         x = inb(0x26);
 523         x = ((pirq - 1) & 1) ? ((x & 0x0f) | (irq << 4)) : ((x & 0xf0) | (irq));
 524         outb(x, 0x26);
 525         return 1;
 526 }
 527 
 528 #ifdef CONFIG_PCI_BIOS
 529 
 530 static int pirq_bios_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
 531 {
 532         struct pci_dev *bridge;
 533         int pin = pci_get_interrupt_pin(dev, &bridge);
 534         return pcibios_set_irq_routing(bridge, pin - 1, irq);
 535 }
 536 
 537 #endif
 538 
 539 static __init int intel_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
 540 {
 541         static struct pci_device_id __initdata pirq_440gx[] = {
 542                 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443GX_0) },
 543                 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443GX_2) },
 544                 { },
 545         };
 546 
 547         /* 440GX has a proprietary PIRQ router -- don't use it */
 548         if (pci_dev_present(pirq_440gx))
 549                 return 0;
 550 
 551         switch (device) {
 552         case PCI_DEVICE_ID_INTEL_82371FB_0:
 553         case PCI_DEVICE_ID_INTEL_82371SB_0:
 554         case PCI_DEVICE_ID_INTEL_82371AB_0:
 555         case PCI_DEVICE_ID_INTEL_82371MX:
 556         case PCI_DEVICE_ID_INTEL_82443MX_0:
 557         case PCI_DEVICE_ID_INTEL_82801AA_0:
 558         case PCI_DEVICE_ID_INTEL_82801AB_0:
 559         case PCI_DEVICE_ID_INTEL_82801BA_0:
 560         case PCI_DEVICE_ID_INTEL_82801BA_10:
 561         case PCI_DEVICE_ID_INTEL_82801CA_0:
 562         case PCI_DEVICE_ID_INTEL_82801CA_12:
 563         case PCI_DEVICE_ID_INTEL_82801DB_0:
 564         case PCI_DEVICE_ID_INTEL_82801E_0:
 565         case PCI_DEVICE_ID_INTEL_82801EB_0:
 566         case PCI_DEVICE_ID_INTEL_ESB_1:
 567         case PCI_DEVICE_ID_INTEL_ICH6_0:
 568         case PCI_DEVICE_ID_INTEL_ICH6_1:
 569         case PCI_DEVICE_ID_INTEL_ICH7_0:
 570         case PCI_DEVICE_ID_INTEL_ICH7_1:
 571         case PCI_DEVICE_ID_INTEL_ICH7_30:
 572         case PCI_DEVICE_ID_INTEL_ICH7_31:
 573         case PCI_DEVICE_ID_INTEL_TGP_LPC:
 574         case PCI_DEVICE_ID_INTEL_ESB2_0:
 575         case PCI_DEVICE_ID_INTEL_ICH8_0:
 576         case PCI_DEVICE_ID_INTEL_ICH8_1:
 577         case PCI_DEVICE_ID_INTEL_ICH8_2:
 578         case PCI_DEVICE_ID_INTEL_ICH8_3:
 579         case PCI_DEVICE_ID_INTEL_ICH8_4:
 580         case PCI_DEVICE_ID_INTEL_ICH9_0:
 581         case PCI_DEVICE_ID_INTEL_ICH9_1:
 582         case PCI_DEVICE_ID_INTEL_ICH9_2:
 583         case PCI_DEVICE_ID_INTEL_ICH9_3:
 584         case PCI_DEVICE_ID_INTEL_ICH9_4:
 585         case PCI_DEVICE_ID_INTEL_ICH9_5:
 586         case PCI_DEVICE_ID_INTEL_EP80579_0:
 587         case PCI_DEVICE_ID_INTEL_ICH10_0:
 588         case PCI_DEVICE_ID_INTEL_ICH10_1:
 589         case PCI_DEVICE_ID_INTEL_ICH10_2:
 590         case PCI_DEVICE_ID_INTEL_ICH10_3:
 591         case PCI_DEVICE_ID_INTEL_PATSBURG_LPC_0:
 592         case PCI_DEVICE_ID_INTEL_PATSBURG_LPC_1:
 593                 r->name = "PIIX/ICH";
 594                 r->get = pirq_piix_get;
 595                 r->set = pirq_piix_set;
 596                 return 1;
 597         }
 598 
 599         if ((device >= PCI_DEVICE_ID_INTEL_5_3400_SERIES_LPC_MIN && 
 600              device <= PCI_DEVICE_ID_INTEL_5_3400_SERIES_LPC_MAX) 
 601         ||  (device >= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MIN && 
 602              device <= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MAX)
 603         ||  (device >= PCI_DEVICE_ID_INTEL_DH89XXCC_LPC_MIN &&
 604              device <= PCI_DEVICE_ID_INTEL_DH89XXCC_LPC_MAX)
 605         ||  (device >= PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MIN &&
 606              device <= PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MAX)) {
 607                 r->name = "PIIX/ICH";
 608                 r->get = pirq_piix_get;
 609                 r->set = pirq_piix_set;
 610                 return 1;
 611         }
 612 
 613         return 0;
 614 }
 615 
 616 static __init int via_router_probe(struct irq_router *r,
 617                                 struct pci_dev *router, u16 device)
 618 {
 619         /* FIXME: We should move some of the quirk fixup stuff here */
 620 
 621         /*
 622          * workarounds for some buggy BIOSes
 623          */
 624         if (device == PCI_DEVICE_ID_VIA_82C586_0) {
 625                 switch (router->device) {
 626                 case PCI_DEVICE_ID_VIA_82C686:
 627                         /*
 628                          * Asus k7m bios wrongly reports 82C686A
 629                          * as 586-compatible
 630                          */
 631                         device = PCI_DEVICE_ID_VIA_82C686;
 632                         break;
 633                 case PCI_DEVICE_ID_VIA_8235:
 634                         /**
 635                          * Asus a7v-x bios wrongly reports 8235
 636                          * as 586-compatible
 637                          */
 638                         device = PCI_DEVICE_ID_VIA_8235;
 639                         break;
 640                 case PCI_DEVICE_ID_VIA_8237:
 641                         /**
 642                          * Asus a7v600 bios wrongly reports 8237
 643                          * as 586-compatible
 644                          */
 645                         device = PCI_DEVICE_ID_VIA_8237;
 646                         break;
 647                 }
 648         }
 649 
 650         switch (device) {
 651         case PCI_DEVICE_ID_VIA_82C586_0:
 652                 r->name = "VIA";
 653                 r->get = pirq_via586_get;
 654                 r->set = pirq_via586_set;
 655                 return 1;
 656         case PCI_DEVICE_ID_VIA_82C596:
 657         case PCI_DEVICE_ID_VIA_82C686:
 658         case PCI_DEVICE_ID_VIA_8231:
 659         case PCI_DEVICE_ID_VIA_8233A:
 660         case PCI_DEVICE_ID_VIA_8235:
 661         case PCI_DEVICE_ID_VIA_8237:
 662                 /* FIXME: add new ones for 8233/5 */
 663                 r->name = "VIA";
 664                 r->get = pirq_via_get;
 665                 r->set = pirq_via_set;
 666                 return 1;
 667         }
 668         return 0;
 669 }
 670 
 671 static __init int vlsi_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
 672 {
 673         switch (device) {
 674         case PCI_DEVICE_ID_VLSI_82C534:
 675                 r->name = "VLSI 82C534";
 676                 r->get = pirq_vlsi_get;
 677                 r->set = pirq_vlsi_set;
 678                 return 1;
 679         }
 680         return 0;
 681 }
 682 
 683 
 684 static __init int serverworks_router_probe(struct irq_router *r,
 685                 struct pci_dev *router, u16 device)
 686 {
 687         switch (device) {
 688         case PCI_DEVICE_ID_SERVERWORKS_OSB4:
 689         case PCI_DEVICE_ID_SERVERWORKS_CSB5:
 690                 r->name = "ServerWorks";
 691                 r->get = pirq_serverworks_get;
 692                 r->set = pirq_serverworks_set;
 693                 return 1;
 694         }
 695         return 0;
 696 }
 697 
 698 static __init int sis_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
 699 {
 700         if (device != PCI_DEVICE_ID_SI_503)
 701                 return 0;
 702 
 703         r->name = "SIS";
 704         r->get = pirq_sis_get;
 705         r->set = pirq_sis_set;
 706         return 1;
 707 }
 708 
 709 static __init int cyrix_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
 710 {
 711         switch (device) {
 712         case PCI_DEVICE_ID_CYRIX_5520:
 713                 r->name = "NatSemi";
 714                 r->get = pirq_cyrix_get;
 715                 r->set = pirq_cyrix_set;
 716                 return 1;
 717         }
 718         return 0;
 719 }
 720 
 721 static __init int opti_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
 722 {
 723         switch (device) {
 724         case PCI_DEVICE_ID_OPTI_82C700:
 725                 r->name = "OPTI";
 726                 r->get = pirq_opti_get;
 727                 r->set = pirq_opti_set;
 728                 return 1;
 729         }
 730         return 0;
 731 }
 732 
 733 static __init int ite_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
 734 {
 735         switch (device) {
 736         case PCI_DEVICE_ID_ITE_IT8330G_0:
 737                 r->name = "ITE";
 738                 r->get = pirq_ite_get;
 739                 r->set = pirq_ite_set;
 740                 return 1;
 741         }
 742         return 0;
 743 }
 744 
 745 static __init int ali_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
 746 {
 747         switch (device) {
 748         case PCI_DEVICE_ID_AL_M1533:
 749         case PCI_DEVICE_ID_AL_M1563:
 750                 r->name = "ALI";
 751                 r->get = pirq_ali_get;
 752                 r->set = pirq_ali_set;
 753                 return 1;
 754         }
 755         return 0;
 756 }
 757 
 758 static __init int amd_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
 759 {
 760         switch (device) {
 761         case PCI_DEVICE_ID_AMD_VIPER_740B:
 762                 r->name = "AMD756";
 763                 break;
 764         case PCI_DEVICE_ID_AMD_VIPER_7413:
 765                 r->name = "AMD766";
 766                 break;
 767         case PCI_DEVICE_ID_AMD_VIPER_7443:
 768                 r->name = "AMD768";
 769                 break;
 770         default:
 771                 return 0;
 772         }
 773         r->get = pirq_amd756_get;
 774         r->set = pirq_amd756_set;
 775         return 1;
 776 }
 777 
 778 static __init int pico_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
 779 {
 780         switch (device) {
 781         case PCI_DEVICE_ID_PICOPOWER_PT86C523:
 782                 r->name = "PicoPower PT86C523";
 783                 r->get = pirq_pico_get;
 784                 r->set = pirq_pico_set;
 785                 return 1;
 786 
 787         case PCI_DEVICE_ID_PICOPOWER_PT86C523BBP:
 788                 r->name = "PicoPower PT86C523 rev. BB+";
 789                 r->get = pirq_pico_get;
 790                 r->set = pirq_pico_set;
 791                 return 1;
 792         }
 793         return 0;
 794 }
 795 
 796 static __initdata struct irq_router_handler pirq_routers[] = {
 797         { PCI_VENDOR_ID_INTEL, intel_router_probe },
 798         { PCI_VENDOR_ID_AL, ali_router_probe },
 799         { PCI_VENDOR_ID_ITE, ite_router_probe },
 800         { PCI_VENDOR_ID_VIA, via_router_probe },
 801         { PCI_VENDOR_ID_OPTI, opti_router_probe },
 802         { PCI_VENDOR_ID_SI, sis_router_probe },
 803         { PCI_VENDOR_ID_CYRIX, cyrix_router_probe },
 804         { PCI_VENDOR_ID_VLSI, vlsi_router_probe },
 805         { PCI_VENDOR_ID_SERVERWORKS, serverworks_router_probe },
 806         { PCI_VENDOR_ID_AMD, amd_router_probe },
 807         { PCI_VENDOR_ID_PICOPOWER, pico_router_probe },
 808         /* Someone with docs needs to add the ATI Radeon IGP */
 809         { 0, NULL }
 810 };
 811 static struct irq_router pirq_router;
 812 static struct pci_dev *pirq_router_dev;
 813 
 814 
 815 /*
 816  *      FIXME: should we have an option to say "generic for
 817  *      chipset" ?
 818  */
 819 
 820 static void __init pirq_find_router(struct irq_router *r)
 821 {
 822         struct irq_routing_table *rt = pirq_table;
 823         struct irq_router_handler *h;
 824 
 825 #ifdef CONFIG_PCI_BIOS
 826         if (!rt->signature) {
 827                 printk(KERN_INFO "PCI: Using BIOS for IRQ routing\n");
 828                 r->set = pirq_bios_set;
 829                 r->name = "BIOS";
 830                 return;
 831         }
 832 #endif
 833 
 834         /* Default unless a driver reloads it */
 835         r->name = "default";
 836         r->get = NULL;
 837         r->set = NULL;
 838 
 839         DBG(KERN_DEBUG "PCI: Attempting to find IRQ router for [%04x:%04x]\n",
 840             rt->rtr_vendor, rt->rtr_device);
 841 
 842         pirq_router_dev = pci_get_domain_bus_and_slot(0, rt->rtr_bus,
 843                                                       rt->rtr_devfn);
 844         if (!pirq_router_dev) {
 845                 DBG(KERN_DEBUG "PCI: Interrupt router not found at "
 846                         "%02x:%02x\n", rt->rtr_bus, rt->rtr_devfn);
 847                 return;
 848         }
 849 
 850         for (h = pirq_routers; h->vendor; h++) {
 851                 /* First look for a router match */
 852                 if (rt->rtr_vendor == h->vendor &&
 853                         h->probe(r, pirq_router_dev, rt->rtr_device))
 854                         break;
 855                 /* Fall back to a device match */
 856                 if (pirq_router_dev->vendor == h->vendor &&
 857                         h->probe(r, pirq_router_dev, pirq_router_dev->device))
 858                         break;
 859         }
 860         dev_info(&pirq_router_dev->dev, "%s IRQ router [%04x:%04x]\n",
 861                  pirq_router.name,
 862                  pirq_router_dev->vendor, pirq_router_dev->device);
 863 
 864         /* The device remains referenced for the kernel lifetime */
 865 }
 866 
 867 static struct irq_info *pirq_get_info(struct pci_dev *dev)
 868 {
 869         struct irq_routing_table *rt = pirq_table;
 870         int entries = (rt->size - sizeof(struct irq_routing_table)) /
 871                 sizeof(struct irq_info);
 872         struct irq_info *info;
 873 
 874         for (info = rt->slots; entries--; info++)
 875                 if (info->bus == dev->bus->number &&
 876                         PCI_SLOT(info->devfn) == PCI_SLOT(dev->devfn))
 877                         return info;
 878         return NULL;
 879 }
 880 
 881 static int pcibios_lookup_irq(struct pci_dev *dev, int assign)
 882 {
 883         u8 pin;
 884         struct irq_info *info;
 885         int i, pirq, newirq;
 886         int irq = 0;
 887         u32 mask;
 888         struct irq_router *r = &pirq_router;
 889         struct pci_dev *dev2 = NULL;
 890         char *msg = NULL;
 891 
 892         /* Find IRQ pin */
 893         pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
 894         if (!pin) {
 895                 dev_dbg(&dev->dev, "no interrupt pin\n");
 896                 return 0;
 897         }
 898 
 899         if (io_apic_assign_pci_irqs)
 900                 return 0;
 901 
 902         /* Find IRQ routing entry */
 903 
 904         if (!pirq_table)
 905                 return 0;
 906 
 907         info = pirq_get_info(dev);
 908         if (!info) {
 909                 dev_dbg(&dev->dev, "PCI INT %c not found in routing table\n",
 910                         'A' + pin - 1);
 911                 return 0;
 912         }
 913         pirq = info->irq[pin - 1].link;
 914         mask = info->irq[pin - 1].bitmap;
 915         if (!pirq) {
 916                 dev_dbg(&dev->dev, "PCI INT %c not routed\n", 'A' + pin - 1);
 917                 return 0;
 918         }
 919         dev_dbg(&dev->dev, "PCI INT %c -> PIRQ %02x, mask %04x, excl %04x",
 920                 'A' + pin - 1, pirq, mask, pirq_table->exclusive_irqs);
 921         mask &= pcibios_irq_mask;
 922 
 923         /* Work around broken HP Pavilion Notebooks which assign USB to
 924            IRQ 9 even though it is actually wired to IRQ 11 */
 925 
 926         if (broken_hp_bios_irq9 && pirq == 0x59 && dev->irq == 9) {
 927                 dev->irq = 11;
 928                 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 11);
 929                 r->set(pirq_router_dev, dev, pirq, 11);
 930         }
 931 
 932         /* same for Acer Travelmate 360, but with CB and irq 11 -> 10 */
 933         if (acer_tm360_irqrouting && dev->irq == 11 &&
 934                 dev->vendor == PCI_VENDOR_ID_O2) {
 935                 pirq = 0x68;
 936                 mask = 0x400;
 937                 dev->irq = r->get(pirq_router_dev, dev, pirq);
 938                 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
 939         }
 940 
 941         /*
 942          * Find the best IRQ to assign: use the one
 943          * reported by the device if possible.
 944          */
 945         newirq = dev->irq;
 946         if (newirq && !((1 << newirq) & mask)) {
 947                 if (pci_probe & PCI_USE_PIRQ_MASK)
 948                         newirq = 0;
 949                 else
 950                         dev_warn(&dev->dev, "IRQ %d doesn't match PIRQ mask "
 951                                  "%#x; try pci=usepirqmask\n", newirq, mask);
 952         }
 953         if (!newirq && assign) {
 954                 for (i = 0; i < 16; i++) {
 955                         if (!(mask & (1 << i)))
 956                                 continue;
 957                         if (pirq_penalty[i] < pirq_penalty[newirq] &&
 958                                 can_request_irq(i, IRQF_SHARED))
 959                                 newirq = i;
 960                 }
 961         }
 962         dev_dbg(&dev->dev, "PCI INT %c -> newirq %d", 'A' + pin - 1, newirq);
 963 
 964         /* Check if it is hardcoded */
 965         if ((pirq & 0xf0) == 0xf0) {
 966                 irq = pirq & 0xf;
 967                 msg = "hardcoded";
 968         } else if (r->get && (irq = r->get(pirq_router_dev, dev, pirq)) && \
 969         ((!(pci_probe & PCI_USE_PIRQ_MASK)) || ((1 << irq) & mask))) {
 970                 msg = "found";
 971                 elcr_set_level_irq(irq);
 972         } else if (newirq && r->set &&
 973                 (dev->class >> 8) != PCI_CLASS_DISPLAY_VGA) {
 974                 if (r->set(pirq_router_dev, dev, pirq, newirq)) {
 975                         elcr_set_level_irq(newirq);
 976                         msg = "assigned";
 977                         irq = newirq;
 978                 }
 979         }
 980 
 981         if (!irq) {
 982                 if (newirq && mask == (1 << newirq)) {
 983                         msg = "guessed";
 984                         irq = newirq;
 985                 } else {
 986                         dev_dbg(&dev->dev, "can't route interrupt\n");
 987                         return 0;
 988                 }
 989         }
 990         dev_info(&dev->dev, "%s PCI INT %c -> IRQ %d\n", msg, 'A' + pin - 1, irq);
 991 
 992         /* Update IRQ for all devices with the same pirq value */
 993         for_each_pci_dev(dev2) {
 994                 pci_read_config_byte(dev2, PCI_INTERRUPT_PIN, &pin);
 995                 if (!pin)
 996                         continue;
 997 
 998                 info = pirq_get_info(dev2);
 999                 if (!info)
1000                         continue;
1001                 if (info->irq[pin - 1].link == pirq) {
1002                         /*
1003                          * We refuse to override the dev->irq
1004                          * information. Give a warning!
1005                          */
1006                         if (dev2->irq && dev2->irq != irq && \
1007                         (!(pci_probe & PCI_USE_PIRQ_MASK) || \
1008                         ((1 << dev2->irq) & mask))) {
1009 #ifndef CONFIG_PCI_MSI
1010                                 dev_info(&dev2->dev, "IRQ routing conflict: "
1011                                          "have IRQ %d, want IRQ %d\n",
1012                                          dev2->irq, irq);
1013 #endif
1014                                 continue;
1015                         }
1016                         dev2->irq = irq;
1017                         pirq_penalty[irq]++;
1018                         if (dev != dev2)
1019                                 dev_info(&dev->dev, "sharing IRQ %d with %s\n",
1020                                          irq, pci_name(dev2));
1021                 }
1022         }
1023         return 1;
1024 }
1025 
1026 void __init pcibios_fixup_irqs(void)
1027 {
1028         struct pci_dev *dev = NULL;
1029         u8 pin;
1030 
1031         DBG(KERN_DEBUG "PCI: IRQ fixup\n");
1032         for_each_pci_dev(dev) {
1033                 /*
1034                  * If the BIOS has set an out of range IRQ number, just
1035                  * ignore it.  Also keep track of which IRQ's are
1036                  * already in use.
1037                  */
1038                 if (dev->irq >= 16) {
1039                         dev_dbg(&dev->dev, "ignoring bogus IRQ %d\n", dev->irq);
1040                         dev->irq = 0;
1041                 }
1042                 /*
1043                  * If the IRQ is already assigned to a PCI device,
1044                  * ignore its ISA use penalty
1045                  */
1046                 if (pirq_penalty[dev->irq] >= 100 &&
1047                                 pirq_penalty[dev->irq] < 100000)
1048                         pirq_penalty[dev->irq] = 0;
1049                 pirq_penalty[dev->irq]++;
1050         }
1051 
1052         if (io_apic_assign_pci_irqs)
1053                 return;
1054 
1055         dev = NULL;
1056         for_each_pci_dev(dev) {
1057                 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
1058                 if (!pin)
1059                         continue;
1060 
1061                 /*
1062                  * Still no IRQ? Try to lookup one...
1063                  */
1064                 if (!dev->irq)
1065                         pcibios_lookup_irq(dev, 0);
1066         }
1067 }
1068 
1069 /*
1070  * Work around broken HP Pavilion Notebooks which assign USB to
1071  * IRQ 9 even though it is actually wired to IRQ 11
1072  */
1073 static int __init fix_broken_hp_bios_irq9(const struct dmi_system_id *d)
1074 {
1075         if (!broken_hp_bios_irq9) {
1076                 broken_hp_bios_irq9 = 1;
1077                 printk(KERN_INFO "%s detected - fixing broken IRQ routing\n",
1078                         d->ident);
1079         }
1080         return 0;
1081 }
1082 
1083 /*
1084  * Work around broken Acer TravelMate 360 Notebooks which assign
1085  * Cardbus to IRQ 11 even though it is actually wired to IRQ 10
1086  */
1087 static int __init fix_acer_tm360_irqrouting(const struct dmi_system_id *d)
1088 {
1089         if (!acer_tm360_irqrouting) {
1090                 acer_tm360_irqrouting = 1;
1091                 printk(KERN_INFO "%s detected - fixing broken IRQ routing\n",
1092                         d->ident);
1093         }
1094         return 0;
1095 }
1096 
1097 static const struct dmi_system_id pciirq_dmi_table[] __initconst = {
1098         {
1099                 .callback = fix_broken_hp_bios_irq9,
1100                 .ident = "HP Pavilion N5400 Series Laptop",
1101                 .matches = {
1102                         DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1103                         DMI_MATCH(DMI_BIOS_VERSION, "GE.M1.03"),
1104                         DMI_MATCH(DMI_PRODUCT_VERSION,
1105                                 "HP Pavilion Notebook Model GE"),
1106                         DMI_MATCH(DMI_BOARD_VERSION, "OmniBook N32N-736"),
1107                 },
1108         },
1109         {
1110                 .callback = fix_acer_tm360_irqrouting,
1111                 .ident = "Acer TravelMate 36x Laptop",
1112                 .matches = {
1113                         DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1114                         DMI_MATCH(DMI_PRODUCT_NAME, "TravelMate 360"),
1115                 },
1116         },
1117         { }
1118 };
1119 
1120 void __init pcibios_irq_init(void)
1121 {
1122         struct irq_routing_table *rtable = NULL;
1123 
1124         DBG(KERN_DEBUG "PCI: IRQ init\n");
1125 
1126         if (raw_pci_ops == NULL)
1127                 return;
1128 
1129         dmi_check_system(pciirq_dmi_table);
1130 
1131         pirq_table = pirq_find_routing_table();
1132 
1133 #ifdef CONFIG_PCI_BIOS
1134         if (!pirq_table && (pci_probe & PCI_BIOS_IRQ_SCAN)) {
1135                 pirq_table = pcibios_get_irq_routing_table();
1136                 rtable = pirq_table;
1137         }
1138 #endif
1139         if (pirq_table) {
1140                 pirq_peer_trick();
1141                 pirq_find_router(&pirq_router);
1142                 if (pirq_table->exclusive_irqs) {
1143                         int i;
1144                         for (i = 0; i < 16; i++)
1145                                 if (!(pirq_table->exclusive_irqs & (1 << i)))
1146                                         pirq_penalty[i] += 100;
1147                 }
1148                 /*
1149                  * If we're using the I/O APIC, avoid using the PCI IRQ
1150                  * routing table
1151                  */
1152                 if (io_apic_assign_pci_irqs) {
1153                         kfree(rtable);
1154                         pirq_table = NULL;
1155                 }
1156         }
1157 
1158         x86_init.pci.fixup_irqs();
1159 
1160         if (io_apic_assign_pci_irqs && pci_routeirq) {
1161                 struct pci_dev *dev = NULL;
1162                 /*
1163                  * PCI IRQ routing is set up by pci_enable_device(), but we
1164                  * also do it here in case there are still broken drivers that
1165                  * don't use pci_enable_device().
1166                  */
1167                 printk(KERN_INFO "PCI: Routing PCI interrupts for all devices because \"pci=routeirq\" specified\n");
1168                 for_each_pci_dev(dev)
1169                         pirq_enable_irq(dev);
1170         }
1171 }
1172 
1173 static void pirq_penalize_isa_irq(int irq, int active)
1174 {
1175         /*
1176          *  If any ISAPnP device reports an IRQ in its list of possible
1177          *  IRQ's, we try to avoid assigning it to PCI devices.
1178          */
1179         if (irq < 16) {
1180                 if (active)
1181                         pirq_penalty[irq] += 1000;
1182                 else
1183                         pirq_penalty[irq] += 100;
1184         }
1185 }
1186 
1187 void pcibios_penalize_isa_irq(int irq, int active)
1188 {
1189 #ifdef CONFIG_ACPI
1190         if (!acpi_noirq)
1191                 acpi_penalize_isa_irq(irq, active);
1192         else
1193 #endif
1194                 pirq_penalize_isa_irq(irq, active);
1195 }
1196 
1197 static int pirq_enable_irq(struct pci_dev *dev)
1198 {
1199         u8 pin = 0;
1200 
1201         pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
1202         if (pin && !pcibios_lookup_irq(dev, 1)) {
1203                 char *msg = "";
1204 
1205                 if (!io_apic_assign_pci_irqs && dev->irq)
1206                         return 0;
1207 
1208                 if (io_apic_assign_pci_irqs) {
1209 #ifdef CONFIG_X86_IO_APIC
1210                         struct pci_dev *temp_dev;
1211                         int irq;
1212 
1213                         if (dev->irq_managed && dev->irq > 0)
1214                                 return 0;
1215 
1216                         irq = IO_APIC_get_PCI_irq_vector(dev->bus->number,
1217                                                 PCI_SLOT(dev->devfn), pin - 1);
1218                         /*
1219                          * Busses behind bridges are typically not listed in the MP-table.
1220                          * In this case we have to look up the IRQ based on the parent bus,
1221                          * parent slot, and pin number. The SMP code detects such bridged
1222                          * busses itself so we should get into this branch reliably.
1223                          */
1224                         temp_dev = dev;
1225                         while (irq < 0 && dev->bus->parent) { /* go back to the bridge */
1226                                 struct pci_dev *bridge = dev->bus->self;
1227 
1228                                 pin = pci_swizzle_interrupt_pin(dev, pin);
1229                                 irq = IO_APIC_get_PCI_irq_vector(bridge->bus->number,
1230                                                 PCI_SLOT(bridge->devfn),
1231                                                 pin - 1);
1232                                 if (irq >= 0)
1233                                         dev_warn(&dev->dev, "using bridge %s "
1234                                                  "INT %c to get IRQ %d\n",
1235                                                  pci_name(bridge), 'A' + pin - 1,
1236                                                  irq);
1237                                 dev = bridge;
1238                         }
1239                         dev = temp_dev;
1240                         if (irq >= 0) {
1241                                 dev->irq_managed = 1;
1242                                 dev->irq = irq;
1243                                 dev_info(&dev->dev, "PCI->APIC IRQ transform: "
1244                                          "INT %c -> IRQ %d\n", 'A' + pin - 1, irq);
1245                                 return 0;
1246                         } else
1247                                 msg = "; probably buggy MP table";
1248 #endif
1249                 } else if (pci_probe & PCI_BIOS_IRQ_SCAN)
1250                         msg = "";
1251                 else
1252                         msg = "; please try using pci=biosirq";
1253 
1254                 /*
1255                  * With IDE legacy devices the IRQ lookup failure is not
1256                  * a problem..
1257                  */
1258                 if (dev->class >> 8 == PCI_CLASS_STORAGE_IDE &&
1259                                 !(dev->class & 0x5))
1260                         return 0;
1261 
1262                 dev_warn(&dev->dev, "can't find IRQ for PCI INT %c%s\n",
1263                          'A' + pin - 1, msg);
1264         }
1265         return 0;
1266 }
1267 
1268 bool mp_should_keep_irq(struct device *dev)
1269 {
1270         if (dev->power.is_prepared)
1271                 return true;
1272 #ifdef CONFIG_PM
1273         if (dev->power.runtime_status == RPM_SUSPENDING)
1274                 return true;
1275 #endif
1276 
1277         return false;
1278 }
1279 
1280 static void pirq_disable_irq(struct pci_dev *dev)
1281 {
1282         if (io_apic_assign_pci_irqs && !mp_should_keep_irq(&dev->dev) &&
1283             dev->irq_managed && dev->irq) {
1284                 mp_unmap_irq(dev->irq);
1285                 dev->irq = 0;
1286                 dev->irq_managed = 0;
1287         }
1288 }
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root/arch/x86/pci/irq.c

DEFINITIONS
