arch/x86/pci/ce4100.c

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This source file includes following definitions.
reg_init
reg_read
reg_write
sata_reg_init
ehci_reg_read
sata_revid_init
sata_revid_read
reg_noirq_read
init_sim_regs
extract_bytes
bridge_read
ce4100_bus1_read
ce4100_conf_read
ce4100_bus1_write
ce4100_conf_write
ce4100_pci_init
   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  *  Copyright(c) 2010 Intel Corporation. All rights reserved.
   4  *
   5  *  Contact Information:
   6  *    Intel Corporation
   7  *    2200 Mission College Blvd.
   8  *    Santa Clara, CA  97052
   9  *
  10  * This provides access methods for PCI registers that mis-behave on
  11  * the CE4100. Each register can be assigned a private init, read and
  12  * write routine. The exception to this is the bridge device.  The
  13  * bridge device is the only device on bus zero (0) that requires any
  14  * fixup so it is a special case ATM
  15  */
  16 
  17 #include <linux/kernel.h>
  18 #include <linux/pci.h>
  19 #include <linux/init.h>
  20 
  21 #include <asm/ce4100.h>
  22 #include <asm/pci_x86.h>
  23 
  24 struct sim_reg {
  25         u32 value;
  26         u32 mask;
  27 };
  28 
  29 struct sim_dev_reg {
  30         int dev_func;
  31         int reg;
  32         void (*init)(struct sim_dev_reg *reg);
  33         void (*read)(struct sim_dev_reg *reg, u32 *value);
  34         void (*write)(struct sim_dev_reg *reg, u32 value);
  35         struct sim_reg sim_reg;
  36 };
  37 
  38 struct sim_reg_op {
  39         void (*init)(struct sim_dev_reg *reg);
  40         void (*read)(struct sim_dev_reg *reg, u32 value);
  41         void (*write)(struct sim_dev_reg *reg, u32 value);
  42 };
  43 
  44 #define MB (1024 * 1024)
  45 #define KB (1024)
  46 #define SIZE_TO_MASK(size) (~(size - 1))
  47 
  48 #define DEFINE_REG(device, func, offset, size, init_op, read_op, write_op)\
  49 { PCI_DEVFN(device, func), offset, init_op, read_op, write_op,\
  50         {0, SIZE_TO_MASK(size)} },
  51 
  52 /*
  53  * All read/write functions are called with pci_config_lock held.
  54  */
  55 static void reg_init(struct sim_dev_reg *reg)
  56 {
  57         pci_direct_conf1.read(0, 1, reg->dev_func, reg->reg, 4,
  58                               &reg->sim_reg.value);
  59 }
  60 
  61 static void reg_read(struct sim_dev_reg *reg, u32 *value)
  62 {
  63         *value = reg->sim_reg.value;
  64 }
  65 
  66 static void reg_write(struct sim_dev_reg *reg, u32 value)
  67 {
  68         reg->sim_reg.value = (value & reg->sim_reg.mask) |
  69                 (reg->sim_reg.value & ~reg->sim_reg.mask);
  70 }
  71 
  72 static void sata_reg_init(struct sim_dev_reg *reg)
  73 {
  74         pci_direct_conf1.read(0, 1, PCI_DEVFN(14, 0), 0x10, 4,
  75                               &reg->sim_reg.value);
  76         reg->sim_reg.value += 0x400;
  77 }
  78 
  79 static void ehci_reg_read(struct sim_dev_reg *reg, u32 *value)
  80 {
  81         reg_read(reg, value);
  82         if (*value != reg->sim_reg.mask)
  83                 *value |= 0x100;
  84 }
  85 
  86 void sata_revid_init(struct sim_dev_reg *reg)
  87 {
  88         reg->sim_reg.value = 0x01060100;
  89         reg->sim_reg.mask = 0;
  90 }
  91 
  92 static void sata_revid_read(struct sim_dev_reg *reg, u32 *value)
  93 {
  94         reg_read(reg, value);
  95 }
  96 
  97 static void reg_noirq_read(struct sim_dev_reg *reg, u32 *value)
  98 {
  99         /* force interrupt pin value to 0 */
 100         *value = reg->sim_reg.value & 0xfff00ff;
 101 }
 102 
 103 static struct sim_dev_reg bus1_fixups[] = {
 104         DEFINE_REG(2, 0, 0x10, (16*MB), reg_init, reg_read, reg_write)
 105         DEFINE_REG(2, 0, 0x14, (256), reg_init, reg_read, reg_write)
 106         DEFINE_REG(2, 1, 0x10, (64*KB), reg_init, reg_read, reg_write)
 107         DEFINE_REG(3, 0, 0x10, (64*KB), reg_init, reg_read, reg_write)
 108         DEFINE_REG(4, 0, 0x10, (128*KB), reg_init, reg_read, reg_write)
 109         DEFINE_REG(4, 1, 0x10, (128*KB), reg_init, reg_read, reg_write)
 110         DEFINE_REG(6, 0, 0x10, (512*KB), reg_init, reg_read, reg_write)
 111         DEFINE_REG(6, 1, 0x10, (512*KB), reg_init, reg_read, reg_write)
 112         DEFINE_REG(6, 2, 0x10, (64*KB), reg_init, reg_read, reg_write)
 113         DEFINE_REG(8, 0, 0x10, (1*MB), reg_init, reg_read, reg_write)
 114         DEFINE_REG(8, 1, 0x10, (64*KB), reg_init, reg_read, reg_write)
 115         DEFINE_REG(8, 2, 0x10, (64*KB), reg_init, reg_read, reg_write)
 116         DEFINE_REG(9, 0, 0x10 , (1*MB), reg_init, reg_read, reg_write)
 117         DEFINE_REG(9, 0, 0x14, (64*KB), reg_init, reg_read, reg_write)
 118         DEFINE_REG(10, 0, 0x10, (256), reg_init, reg_read, reg_write)
 119         DEFINE_REG(10, 0, 0x14, (256*MB), reg_init, reg_read, reg_write)
 120         DEFINE_REG(11, 0, 0x10, (256), reg_init, reg_read, reg_write)
 121         DEFINE_REG(11, 0, 0x14, (256), reg_init, reg_read, reg_write)
 122         DEFINE_REG(11, 1, 0x10, (256), reg_init, reg_read, reg_write)
 123         DEFINE_REG(11, 2, 0x10, (256), reg_init, reg_read, reg_write)
 124         DEFINE_REG(11, 2, 0x14, (256), reg_init, reg_read, reg_write)
 125         DEFINE_REG(11, 2, 0x18, (256), reg_init, reg_read, reg_write)
 126         DEFINE_REG(11, 3, 0x10, (256), reg_init, reg_read, reg_write)
 127         DEFINE_REG(11, 3, 0x14, (256), reg_init, reg_read, reg_write)
 128         DEFINE_REG(11, 4, 0x10, (256), reg_init, reg_read, reg_write)
 129         DEFINE_REG(11, 5, 0x10, (64*KB), reg_init, reg_read, reg_write)
 130         DEFINE_REG(11, 6, 0x10, (256), reg_init, reg_read, reg_write)
 131         DEFINE_REG(11, 7, 0x10, (64*KB), reg_init, reg_read, reg_write)
 132         DEFINE_REG(11, 7, 0x3c, 256, reg_init, reg_noirq_read, reg_write)
 133         DEFINE_REG(12, 0, 0x10, (128*KB), reg_init, reg_read, reg_write)
 134         DEFINE_REG(12, 0, 0x14, (256), reg_init, reg_read, reg_write)
 135         DEFINE_REG(12, 1, 0x10, (1024), reg_init, reg_read, reg_write)
 136         DEFINE_REG(13, 0, 0x10, (32*KB), reg_init, ehci_reg_read, reg_write)
 137         DEFINE_REG(13, 1, 0x10, (32*KB), reg_init, ehci_reg_read, reg_write)
 138         DEFINE_REG(14, 0, 0x8,  0, sata_revid_init, sata_revid_read, 0)
 139         DEFINE_REG(14, 0, 0x10, 0, reg_init, reg_read, reg_write)
 140         DEFINE_REG(14, 0, 0x14, 0, reg_init, reg_read, reg_write)
 141         DEFINE_REG(14, 0, 0x18, 0, reg_init, reg_read, reg_write)
 142         DEFINE_REG(14, 0, 0x1C, 0, reg_init, reg_read, reg_write)
 143         DEFINE_REG(14, 0, 0x20, 0, reg_init, reg_read, reg_write)
 144         DEFINE_REG(14, 0, 0x24, (0x200), sata_reg_init, reg_read, reg_write)
 145         DEFINE_REG(15, 0, 0x10, (64*KB), reg_init, reg_read, reg_write)
 146         DEFINE_REG(15, 0, 0x14, (64*KB), reg_init, reg_read, reg_write)
 147         DEFINE_REG(16, 0, 0x10, (64*KB), reg_init, reg_read, reg_write)
 148         DEFINE_REG(16, 0, 0x14, (64*MB), reg_init, reg_read, reg_write)
 149         DEFINE_REG(16, 0, 0x18, (64*MB), reg_init, reg_read, reg_write)
 150         DEFINE_REG(16, 0, 0x3c, 256, reg_init, reg_noirq_read, reg_write)
 151         DEFINE_REG(17, 0, 0x10, (128*KB), reg_init, reg_read, reg_write)
 152         DEFINE_REG(18, 0, 0x10, (1*KB), reg_init, reg_read, reg_write)
 153         DEFINE_REG(18, 0, 0x3c, 256, reg_init, reg_noirq_read, reg_write)
 154 };
 155 
 156 static void __init init_sim_regs(void)
 157 {
 158         int i;
 159 
 160         for (i = 0; i < ARRAY_SIZE(bus1_fixups); i++) {
 161                 if (bus1_fixups[i].init)
 162                         bus1_fixups[i].init(&bus1_fixups[i]);
 163         }
 164 }
 165 
 166 static inline void extract_bytes(u32 *value, int reg, int len)
 167 {
 168         uint32_t mask;
 169 
 170         *value >>= ((reg & 3) * 8);
 171         mask = 0xFFFFFFFF >> ((4 - len) * 8);
 172         *value &= mask;
 173 }
 174 
 175 int bridge_read(unsigned int devfn, int reg, int len, u32 *value)
 176 {
 177         u32 av_bridge_base, av_bridge_limit;
 178         int retval = 0;
 179 
 180         switch (reg) {
 181         /* Make BARs appear to not request any memory. */
 182         case PCI_BASE_ADDRESS_0:
 183         case PCI_BASE_ADDRESS_0 + 1:
 184         case PCI_BASE_ADDRESS_0 + 2:
 185         case PCI_BASE_ADDRESS_0 + 3:
 186                 *value = 0;
 187                 break;
 188 
 189                 /* Since subordinate bus number register is hardwired
 190                  * to zero and read only, so do the simulation.
 191                  */
 192         case PCI_PRIMARY_BUS:
 193                 if (len == 4)
 194                         *value = 0x00010100;
 195                 break;
 196 
 197         case PCI_SUBORDINATE_BUS:
 198                 *value = 1;
 199                 break;
 200 
 201         case PCI_MEMORY_BASE:
 202         case PCI_MEMORY_LIMIT:
 203                 /* Get the A/V bridge base address. */
 204                 pci_direct_conf1.read(0, 0, devfn,
 205                                 PCI_BASE_ADDRESS_0, 4, &av_bridge_base);
 206 
 207                 av_bridge_limit = av_bridge_base + (512*MB - 1);
 208                 av_bridge_limit >>= 16;
 209                 av_bridge_limit &= 0xFFF0;
 210 
 211                 av_bridge_base >>= 16;
 212                 av_bridge_base &= 0xFFF0;
 213 
 214                 if (reg == PCI_MEMORY_LIMIT)
 215                         *value = av_bridge_limit;
 216                 else if (len == 2)
 217                         *value = av_bridge_base;
 218                 else
 219                         *value = (av_bridge_limit << 16) | av_bridge_base;
 220                 break;
 221                 /* Make prefetchable memory limit smaller than prefetchable
 222                  * memory base, so not claim prefetchable memory space.
 223                  */
 224         case PCI_PREF_MEMORY_BASE:
 225                 *value = 0xFFF0;
 226                 break;
 227         case PCI_PREF_MEMORY_LIMIT:
 228                 *value = 0x0;
 229                 break;
 230                 /* Make IO limit smaller than IO base, so not claim IO space. */
 231         case PCI_IO_BASE:
 232                 *value = 0xF0;
 233                 break;
 234         case PCI_IO_LIMIT:
 235                 *value = 0;
 236                 break;
 237         default:
 238                 retval = 1;
 239         }
 240         return retval;
 241 }
 242 
 243 static int ce4100_bus1_read(unsigned int devfn, int reg, int len, u32 *value)
 244 {
 245         unsigned long flags;
 246         int i;
 247 
 248         for (i = 0; i < ARRAY_SIZE(bus1_fixups); i++) {
 249                 if (bus1_fixups[i].dev_func == devfn &&
 250                     bus1_fixups[i].reg == (reg & ~3) &&
 251                     bus1_fixups[i].read) {
 252 
 253                         raw_spin_lock_irqsave(&pci_config_lock, flags);
 254                         bus1_fixups[i].read(&(bus1_fixups[i]), value);
 255                         raw_spin_unlock_irqrestore(&pci_config_lock, flags);
 256                         extract_bytes(value, reg, len);
 257                         return 0;
 258                 }
 259         }
 260         return -1;
 261 }
 262 
 263 static int ce4100_conf_read(unsigned int seg, unsigned int bus,
 264                             unsigned int devfn, int reg, int len, u32 *value)
 265 {
 266         WARN_ON(seg);
 267 
 268         if (bus == 1 && !ce4100_bus1_read(devfn, reg, len, value))
 269                 return 0;
 270 
 271         if (bus == 0 && (PCI_DEVFN(1, 0) == devfn) &&
 272             !bridge_read(devfn, reg, len, value))
 273                 return 0;
 274 
 275         return pci_direct_conf1.read(seg, bus, devfn, reg, len, value);
 276 }
 277 
 278 static int ce4100_bus1_write(unsigned int devfn, int reg, int len, u32 value)
 279 {
 280         unsigned long flags;
 281         int i;
 282 
 283         for (i = 0; i < ARRAY_SIZE(bus1_fixups); i++) {
 284                 if (bus1_fixups[i].dev_func == devfn &&
 285                     bus1_fixups[i].reg == (reg & ~3) &&
 286                     bus1_fixups[i].write) {
 287 
 288                         raw_spin_lock_irqsave(&pci_config_lock, flags);
 289                         bus1_fixups[i].write(&(bus1_fixups[i]), value);
 290                         raw_spin_unlock_irqrestore(&pci_config_lock, flags);
 291                         return 0;
 292                 }
 293         }
 294         return -1;
 295 }
 296 
 297 static int ce4100_conf_write(unsigned int seg, unsigned int bus,
 298                              unsigned int devfn, int reg, int len, u32 value)
 299 {
 300         WARN_ON(seg);
 301 
 302         if (bus == 1 && !ce4100_bus1_write(devfn, reg, len, value))
 303                 return 0;
 304 
 305         /* Discard writes to A/V bridge BAR. */
 306         if (bus == 0 && PCI_DEVFN(1, 0) == devfn &&
 307             ((reg & ~3) == PCI_BASE_ADDRESS_0))
 308                 return 0;
 309 
 310         return pci_direct_conf1.write(seg, bus, devfn, reg, len, value);
 311 }
 312 
 313 static const struct pci_raw_ops ce4100_pci_conf = {
 314         .read   = ce4100_conf_read,
 315         .write  = ce4100_conf_write,
 316 };
 317 
 318 int __init ce4100_pci_init(void)
 319 {
 320         init_sim_regs();
 321         raw_pci_ops = &ce4100_pci_conf;
 322         /* Indicate caller that it should invoke pci_legacy_init() */
 323         return 1;
 324 }
/* [<][>][^][v][top][bottom][index][help] */
root/arch/x86/pci/ce4100.c

DEFINITIONS
