1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * linux/arch/x86_64/entry.S 4 * 5 * Copyright (C) 1991, 1992 Linus Torvalds 6 * Copyright (C) 2000, 2001, 2002 Andi Kleen SuSE Labs 7 * Copyright (C) 2000 Pavel Machek <pavel@suse.cz> 8 * 9 * entry.S contains the system-call and fault low-level handling routines. 10 * 11 * Some of this is documented in Documentation/x86/entry_64.rst 12 * 13 * A note on terminology: 14 * - iret frame: Architecture defined interrupt frame from SS to RIP 15 * at the top of the kernel process stack. 16 * 17 * Some macro usage: 18 * - ENTRY/END: Define functions in the symbol table. 19 * - TRACE_IRQ_*: Trace hardirq state for lock debugging. 20 * - idtentry: Define exception entry points. 21 */ 22 #include <linux/linkage.h> 23 #include <asm/segment.h> 24 #include <asm/cache.h> 25 #include <asm/errno.h> 26 #include <asm/asm-offsets.h> 27 #include <asm/msr.h> 28 #include <asm/unistd.h> 29 #include <asm/thread_info.h> 30 #include <asm/hw_irq.h> 31 #include <asm/page_types.h> 32 #include <asm/irqflags.h> 33 #include <asm/paravirt.h> 34 #include <asm/percpu.h> 35 #include <asm/asm.h> 36 #include <asm/smap.h> 37 #include <asm/pgtable_types.h> 38 #include <asm/export.h> 39 #include <asm/frame.h> 40 #include <asm/nospec-branch.h> 41 #include <linux/err.h> 42 43 #include "calling.h" 44 45 .code64 46 .section .entry.text, "ax" 47 48 #ifdef CONFIG_PARAVIRT 49 ENTRY(native_usergs_sysret64) 50 UNWIND_HINT_EMPTY 51 swapgs 52 sysretq 53 END(native_usergs_sysret64) 54 #endif /* CONFIG_PARAVIRT */ 55 56 .macro TRACE_IRQS_FLAGS flags:req 57 #ifdef CONFIG_TRACE_IRQFLAGS 58 btl $9, \flags /* interrupts off? */ 59 jnc 1f 60 TRACE_IRQS_ON 61 1: 62 #endif 63 .endm 64 65 .macro TRACE_IRQS_IRETQ 66 TRACE_IRQS_FLAGS EFLAGS(%rsp) 67 .endm 68 69 /* 70 * When dynamic function tracer is enabled it will add a breakpoint 71 * to all locations that it is about to modify, sync CPUs, update 72 * all the code, sync CPUs, then remove the breakpoints. In this time 73 * if lockdep is enabled, it might jump back into the debug handler 74 * outside the updating of the IST protection. (TRACE_IRQS_ON/OFF). 75 * 76 * We need to change the IDT table before calling TRACE_IRQS_ON/OFF to 77 * make sure the stack pointer does not get reset back to the top 78 * of the debug stack, and instead just reuses the current stack. 79 */ 80 #if defined(CONFIG_DYNAMIC_FTRACE) && defined(CONFIG_TRACE_IRQFLAGS) 81 82 .macro TRACE_IRQS_OFF_DEBUG 83 call debug_stack_set_zero 84 TRACE_IRQS_OFF 85 call debug_stack_reset 86 .endm 87 88 .macro TRACE_IRQS_ON_DEBUG 89 call debug_stack_set_zero 90 TRACE_IRQS_ON 91 call debug_stack_reset 92 .endm 93 94 .macro TRACE_IRQS_IRETQ_DEBUG 95 btl $9, EFLAGS(%rsp) /* interrupts off? */ 96 jnc 1f 97 TRACE_IRQS_ON_DEBUG 98 1: 99 .endm 100 101 #else 102 # define TRACE_IRQS_OFF_DEBUG TRACE_IRQS_OFF 103 # define TRACE_IRQS_ON_DEBUG TRACE_IRQS_ON 104 # define TRACE_IRQS_IRETQ_DEBUG TRACE_IRQS_IRETQ 105 #endif 106 107 /* 108 * 64-bit SYSCALL instruction entry. Up to 6 arguments in registers. 109 * 110 * This is the only entry point used for 64-bit system calls. The 111 * hardware interface is reasonably well designed and the register to 112 * argument mapping Linux uses fits well with the registers that are 113 * available when SYSCALL is used. 114 * 115 * SYSCALL instructions can be found inlined in libc implementations as 116 * well as some other programs and libraries. There are also a handful 117 * of SYSCALL instructions in the vDSO used, for example, as a 118 * clock_gettimeofday fallback. 119 * 120 * 64-bit SYSCALL saves rip to rcx, clears rflags.RF, then saves rflags to r11, 121 * then loads new ss, cs, and rip from previously programmed MSRs. 122 * rflags gets masked by a value from another MSR (so CLD and CLAC 123 * are not needed). SYSCALL does not save anything on the stack 124 * and does not change rsp. 125 * 126 * Registers on entry: 127 * rax system call number 128 * rcx return address 129 * r11 saved rflags (note: r11 is callee-clobbered register in C ABI) 130 * rdi arg0 131 * rsi arg1 132 * rdx arg2 133 * r10 arg3 (needs to be moved to rcx to conform to C ABI) 134 * r8 arg4 135 * r9 arg5 136 * (note: r12-r15, rbp, rbx are callee-preserved in C ABI) 137 * 138 * Only called from user space. 139 * 140 * When user can change pt_regs->foo always force IRET. That is because 141 * it deals with uncanonical addresses better. SYSRET has trouble 142 * with them due to bugs in both AMD and Intel CPUs. 143 */ 144 145 ENTRY(entry_SYSCALL_64) 146 UNWIND_HINT_EMPTY 147 /* 148 * Interrupts are off on entry. 149 * We do not frame this tiny irq-off block with TRACE_IRQS_OFF/ON, 150 * it is too small to ever cause noticeable irq latency. 151 */ 152 153 swapgs 154 /* tss.sp2 is scratch space. */ 155 movq %rsp, PER_CPU_VAR(cpu_tss_rw + TSS_sp2) 156 SWITCH_TO_KERNEL_CR3 scratch_reg=%rsp 157 movq PER_CPU_VAR(cpu_current_top_of_stack), %rsp 158 159 /* Construct struct pt_regs on stack */ 160 pushq $__USER_DS /* pt_regs->ss */ 161 pushq PER_CPU_VAR(cpu_tss_rw + TSS_sp2) /* pt_regs->sp */ 162 pushq %r11 /* pt_regs->flags */ 163 pushq $__USER_CS /* pt_regs->cs */ 164 pushq %rcx /* pt_regs->ip */ 165 GLOBAL(entry_SYSCALL_64_after_hwframe) 166 pushq %rax /* pt_regs->orig_ax */ 167 168 PUSH_AND_CLEAR_REGS rax=$-ENOSYS 169 170 TRACE_IRQS_OFF 171 172 /* IRQs are off. */ 173 movq %rax, %rdi 174 movq %rsp, %rsi 175 call do_syscall_64 /* returns with IRQs disabled */ 176 177 TRACE_IRQS_IRETQ /* we're about to change IF */ 178 179 /* 180 * Try to use SYSRET instead of IRET if we're returning to 181 * a completely clean 64-bit userspace context. If we're not, 182 * go to the slow exit path. 183 */ 184 movq RCX(%rsp), %rcx 185 movq RIP(%rsp), %r11 186 187 cmpq %rcx, %r11 /* SYSRET requires RCX == RIP */ 188 jne swapgs_restore_regs_and_return_to_usermode 189 190 /* 191 * On Intel CPUs, SYSRET with non-canonical RCX/RIP will #GP 192 * in kernel space. This essentially lets the user take over 193 * the kernel, since userspace controls RSP. 194 * 195 * If width of "canonical tail" ever becomes variable, this will need 196 * to be updated to remain correct on both old and new CPUs. 197 * 198 * Change top bits to match most significant bit (47th or 56th bit 199 * depending on paging mode) in the address. 200 */ 201 #ifdef CONFIG_X86_5LEVEL 202 ALTERNATIVE "shl $(64 - 48), %rcx; sar $(64 - 48), %rcx", \ 203 "shl $(64 - 57), %rcx; sar $(64 - 57), %rcx", X86_FEATURE_LA57 204 #else 205 shl $(64 - (__VIRTUAL_MASK_SHIFT+1)), %rcx 206 sar $(64 - (__VIRTUAL_MASK_SHIFT+1)), %rcx 207 #endif 208 209 /* If this changed %rcx, it was not canonical */ 210 cmpq %rcx, %r11 211 jne swapgs_restore_regs_and_return_to_usermode 212 213 cmpq $__USER_CS, CS(%rsp) /* CS must match SYSRET */ 214 jne swapgs_restore_regs_and_return_to_usermode 215 216 movq R11(%rsp), %r11 217 cmpq %r11, EFLAGS(%rsp) /* R11 == RFLAGS */ 218 jne swapgs_restore_regs_and_return_to_usermode 219 220 /* 221 * SYSCALL clears RF when it saves RFLAGS in R11 and SYSRET cannot 222 * restore RF properly. If the slowpath sets it for whatever reason, we 223 * need to restore it correctly. 224 * 225 * SYSRET can restore TF, but unlike IRET, restoring TF results in a 226 * trap from userspace immediately after SYSRET. This would cause an 227 * infinite loop whenever #DB happens with register state that satisfies 228 * the opportunistic SYSRET conditions. For example, single-stepping 229 * this user code: 230 * 231 * movq $stuck_here, %rcx 232 * pushfq 233 * popq %r11 234 * stuck_here: 235 * 236 * would never get past 'stuck_here'. 237 */ 238 testq $(X86_EFLAGS_RF|X86_EFLAGS_TF), %r11 239 jnz swapgs_restore_regs_and_return_to_usermode 240 241 /* nothing to check for RSP */ 242 243 cmpq $__USER_DS, SS(%rsp) /* SS must match SYSRET */ 244 jne swapgs_restore_regs_and_return_to_usermode 245 246 /* 247 * We win! This label is here just for ease of understanding 248 * perf profiles. Nothing jumps here. 249 */ 250 syscall_return_via_sysret: 251 /* rcx and r11 are already restored (see code above) */ 252 POP_REGS pop_rdi=0 skip_r11rcx=1 253 254 /* 255 * Now all regs are restored except RSP and RDI. 256 * Save old stack pointer and switch to trampoline stack. 257 */ 258 movq %rsp, %rdi 259 movq PER_CPU_VAR(cpu_tss_rw + TSS_sp0), %rsp 260 UNWIND_HINT_EMPTY 261 262 pushq RSP-RDI(%rdi) /* RSP */ 263 pushq (%rdi) /* RDI */ 264 265 /* 266 * We are on the trampoline stack. All regs except RDI are live. 267 * We can do future final exit work right here. 268 */ 269 STACKLEAK_ERASE_NOCLOBBER 270 271 SWITCH_TO_USER_CR3_STACK scratch_reg=%rdi 272 273 popq %rdi 274 popq %rsp 275 USERGS_SYSRET64 276 END(entry_SYSCALL_64) 277 278 /* 279 * %rdi: prev task 280 * %rsi: next task 281 */ 282 ENTRY(__switch_to_asm) 283 UNWIND_HINT_FUNC 284 /* 285 * Save callee-saved registers 286 * This must match the order in inactive_task_frame 287 */ 288 pushq %rbp 289 pushq %rbx 290 pushq %r12 291 pushq %r13 292 pushq %r14 293 pushq %r15 294 295 /* switch stack */ 296 movq %rsp, TASK_threadsp(%rdi) 297 movq TASK_threadsp(%rsi), %rsp 298 299 #ifdef CONFIG_STACKPROTECTOR 300 movq TASK_stack_canary(%rsi), %rbx 301 movq %rbx, PER_CPU_VAR(fixed_percpu_data) + stack_canary_offset 302 #endif 303 304 #ifdef CONFIG_RETPOLINE 305 /* 306 * When switching from a shallower to a deeper call stack 307 * the RSB may either underflow or use entries populated 308 * with userspace addresses. On CPUs where those concerns 309 * exist, overwrite the RSB with entries which capture 310 * speculative execution to prevent attack. 311 */ 312 FILL_RETURN_BUFFER %r12, RSB_CLEAR_LOOPS, X86_FEATURE_RSB_CTXSW 313 #endif 314 315 /* restore callee-saved registers */ 316 popq %r15 317 popq %r14 318 popq %r13 319 popq %r12 320 popq %rbx 321 popq %rbp 322 323 jmp __switch_to 324 END(__switch_to_asm) 325 326 /* 327 * A newly forked process directly context switches into this address. 328 * 329 * rax: prev task we switched from 330 * rbx: kernel thread func (NULL for user thread) 331 * r12: kernel thread arg 332 */ 333 ENTRY(ret_from_fork) 334 UNWIND_HINT_EMPTY 335 movq %rax, %rdi 336 call schedule_tail /* rdi: 'prev' task parameter */ 337 338 testq %rbx, %rbx /* from kernel_thread? */ 339 jnz 1f /* kernel threads are uncommon */ 340 341 2: 342 UNWIND_HINT_REGS 343 movq %rsp, %rdi 344 call syscall_return_slowpath /* returns with IRQs disabled */ 345 TRACE_IRQS_ON /* user mode is traced as IRQS on */ 346 jmp swapgs_restore_regs_and_return_to_usermode 347 348 1: 349 /* kernel thread */ 350 UNWIND_HINT_EMPTY 351 movq %r12, %rdi 352 CALL_NOSPEC %rbx 353 /* 354 * A kernel thread is allowed to return here after successfully 355 * calling do_execve(). Exit to userspace to complete the execve() 356 * syscall. 357 */ 358 movq $0, RAX(%rsp) 359 jmp 2b 360 END(ret_from_fork) 361 362 /* 363 * Build the entry stubs with some assembler magic. 364 * We pack 1 stub into every 8-byte block. 365 */ 366 .align 8 367 ENTRY(irq_entries_start) 368 vector=FIRST_EXTERNAL_VECTOR 369 .rept (FIRST_SYSTEM_VECTOR - FIRST_EXTERNAL_VECTOR) 370 UNWIND_HINT_IRET_REGS 371 pushq $(~vector+0x80) /* Note: always in signed byte range */ 372 jmp common_interrupt 373 .align 8 374 vector=vector+1 375 .endr 376 END(irq_entries_start) 377 378 .align 8 379 ENTRY(spurious_entries_start) 380 vector=FIRST_SYSTEM_VECTOR 381 .rept (NR_VECTORS - FIRST_SYSTEM_VECTOR) 382 UNWIND_HINT_IRET_REGS 383 pushq $(~vector+0x80) /* Note: always in signed byte range */ 384 jmp common_spurious 385 .align 8 386 vector=vector+1 387 .endr 388 END(spurious_entries_start) 389 390 .macro DEBUG_ENTRY_ASSERT_IRQS_OFF 391 #ifdef CONFIG_DEBUG_ENTRY 392 pushq %rax 393 SAVE_FLAGS(CLBR_RAX) 394 testl $X86_EFLAGS_IF, %eax 395 jz .Lokay_\@ 396 ud2 397 .Lokay_\@: 398 popq %rax 399 #endif 400 .endm 401 402 /* 403 * Enters the IRQ stack if we're not already using it. NMI-safe. Clobbers 404 * flags and puts old RSP into old_rsp, and leaves all other GPRs alone. 405 * Requires kernel GSBASE. 406 * 407 * The invariant is that, if irq_count != -1, then the IRQ stack is in use. 408 */ 409 .macro ENTER_IRQ_STACK regs=1 old_rsp save_ret=0 410 DEBUG_ENTRY_ASSERT_IRQS_OFF 411 412 .if \save_ret 413 /* 414 * If save_ret is set, the original stack contains one additional 415 * entry -- the return address. Therefore, move the address one 416 * entry below %rsp to \old_rsp. 417 */ 418 leaq 8(%rsp), \old_rsp 419 .else 420 movq %rsp, \old_rsp 421 .endif 422 423 .if \regs 424 UNWIND_HINT_REGS base=\old_rsp 425 .endif 426 427 incl PER_CPU_VAR(irq_count) 428 jnz .Lirq_stack_push_old_rsp_\@ 429 430 /* 431 * Right now, if we just incremented irq_count to zero, we've 432 * claimed the IRQ stack but we haven't switched to it yet. 433 * 434 * If anything is added that can interrupt us here without using IST, 435 * it must be *extremely* careful to limit its stack usage. This 436 * could include kprobes and a hypothetical future IST-less #DB 437 * handler. 438 * 439 * The OOPS unwinder relies on the word at the top of the IRQ 440 * stack linking back to the previous RSP for the entire time we're 441 * on the IRQ stack. For this to work reliably, we need to write 442 * it before we actually move ourselves to the IRQ stack. 443 */ 444 445 movq \old_rsp, PER_CPU_VAR(irq_stack_backing_store + IRQ_STACK_SIZE - 8) 446 movq PER_CPU_VAR(hardirq_stack_ptr), %rsp 447 448 #ifdef CONFIG_DEBUG_ENTRY 449 /* 450 * If the first movq above becomes wrong due to IRQ stack layout 451 * changes, the only way we'll notice is if we try to unwind right 452 * here. Assert that we set up the stack right to catch this type 453 * of bug quickly. 454 */ 455 cmpq -8(%rsp), \old_rsp 456 je .Lirq_stack_okay\@ 457 ud2 458 .Lirq_stack_okay\@: 459 #endif 460 461 .Lirq_stack_push_old_rsp_\@: 462 pushq \old_rsp 463 464 .if \regs 465 UNWIND_HINT_REGS indirect=1 466 .endif 467 468 .if \save_ret 469 /* 470 * Push the return address to the stack. This return address can 471 * be found at the "real" original RSP, which was offset by 8 at 472 * the beginning of this macro. 473 */ 474 pushq -8(\old_rsp) 475 .endif 476 .endm 477 478 /* 479 * Undoes ENTER_IRQ_STACK. 480 */ 481 .macro LEAVE_IRQ_STACK regs=1 482 DEBUG_ENTRY_ASSERT_IRQS_OFF 483 /* We need to be off the IRQ stack before decrementing irq_count. */ 484 popq %rsp 485 486 .if \regs 487 UNWIND_HINT_REGS 488 .endif 489 490 /* 491 * As in ENTER_IRQ_STACK, irq_count == 0, we are still claiming 492 * the irq stack but we're not on it. 493 */ 494 495 decl PER_CPU_VAR(irq_count) 496 .endm 497 498 /* 499 * Interrupt entry helper function. 500 * 501 * Entry runs with interrupts off. Stack layout at entry: 502 * +----------------------------------------------------+ 503 * | regs->ss | 504 * | regs->rsp | 505 * | regs->eflags | 506 * | regs->cs | 507 * | regs->ip | 508 * +----------------------------------------------------+ 509 * | regs->orig_ax = ~(interrupt number) | 510 * +----------------------------------------------------+ 511 * | return address | 512 * +----------------------------------------------------+ 513 */ 514 ENTRY(interrupt_entry) 515 UNWIND_HINT_IRET_REGS offset=16 516 ASM_CLAC 517 cld 518 519 testb $3, CS-ORIG_RAX+8(%rsp) 520 jz 1f 521 SWAPGS 522 FENCE_SWAPGS_USER_ENTRY 523 /* 524 * Switch to the thread stack. The IRET frame and orig_ax are 525 * on the stack, as well as the return address. RDI..R12 are 526 * not (yet) on the stack and space has not (yet) been 527 * allocated for them. 528 */ 529 pushq %rdi 530 531 /* Need to switch before accessing the thread stack. */ 532 SWITCH_TO_KERNEL_CR3 scratch_reg=%rdi 533 movq %rsp, %rdi 534 movq PER_CPU_VAR(cpu_current_top_of_stack), %rsp 535 536 /* 537 * We have RDI, return address, and orig_ax on the stack on 538 * top of the IRET frame. That means offset=24 539 */ 540 UNWIND_HINT_IRET_REGS base=%rdi offset=24 541 542 pushq 7*8(%rdi) /* regs->ss */ 543 pushq 6*8(%rdi) /* regs->rsp */ 544 pushq 5*8(%rdi) /* regs->eflags */ 545 pushq 4*8(%rdi) /* regs->cs */ 546 pushq 3*8(%rdi) /* regs->ip */ 547 UNWIND_HINT_IRET_REGS 548 pushq 2*8(%rdi) /* regs->orig_ax */ 549 pushq 8(%rdi) /* return address */ 550 551 movq (%rdi), %rdi 552 jmp 2f 553 1: 554 FENCE_SWAPGS_KERNEL_ENTRY 555 2: 556 PUSH_AND_CLEAR_REGS save_ret=1 557 ENCODE_FRAME_POINTER 8 558 559 testb $3, CS+8(%rsp) 560 jz 1f 561 562 /* 563 * IRQ from user mode. 564 * 565 * We need to tell lockdep that IRQs are off. We can't do this until 566 * we fix gsbase, and we should do it before enter_from_user_mode 567 * (which can take locks). Since TRACE_IRQS_OFF is idempotent, 568 * the simplest way to handle it is to just call it twice if 569 * we enter from user mode. There's no reason to optimize this since 570 * TRACE_IRQS_OFF is a no-op if lockdep is off. 571 */ 572 TRACE_IRQS_OFF 573 574 CALL_enter_from_user_mode 575 576 1: 577 ENTER_IRQ_STACK old_rsp=%rdi save_ret=1 578 /* We entered an interrupt context - irqs are off: */ 579 TRACE_IRQS_OFF 580 581 ret 582 END(interrupt_entry) 583 _ASM_NOKPROBE(interrupt_entry) 584 585 586 /* Interrupt entry/exit. */ 587 588 /* 589 * The interrupt stubs push (~vector+0x80) onto the stack and 590 * then jump to common_spurious/interrupt. 591 */ 592 common_spurious: 593 addq $-0x80, (%rsp) /* Adjust vector to [-256, -1] range */ 594 call interrupt_entry 595 UNWIND_HINT_REGS indirect=1 596 call smp_spurious_interrupt /* rdi points to pt_regs */ 597 jmp ret_from_intr 598 END(common_spurious) 599 _ASM_NOKPROBE(common_spurious) 600 601 /* common_interrupt is a hotpath. Align it */ 602 .p2align CONFIG_X86_L1_CACHE_SHIFT 603 common_interrupt: 604 addq $-0x80, (%rsp) /* Adjust vector to [-256, -1] range */ 605 call interrupt_entry 606 UNWIND_HINT_REGS indirect=1 607 call do_IRQ /* rdi points to pt_regs */ 608 /* 0(%rsp): old RSP */ 609 ret_from_intr: 610 DISABLE_INTERRUPTS(CLBR_ANY) 611 TRACE_IRQS_OFF 612 613 LEAVE_IRQ_STACK 614 615 testb $3, CS(%rsp) 616 jz retint_kernel 617 618 /* Interrupt came from user space */ 619 GLOBAL(retint_user) 620 mov %rsp,%rdi 621 call prepare_exit_to_usermode 622 TRACE_IRQS_IRETQ 623 624 GLOBAL(swapgs_restore_regs_and_return_to_usermode) 625 #ifdef CONFIG_DEBUG_ENTRY 626 /* Assert that pt_regs indicates user mode. */ 627 testb $3, CS(%rsp) 628 jnz 1f 629 ud2 630 1: 631 #endif 632 POP_REGS pop_rdi=0 633 634 /* 635 * The stack is now user RDI, orig_ax, RIP, CS, EFLAGS, RSP, SS. 636 * Save old stack pointer and switch to trampoline stack. 637 */ 638 movq %rsp, %rdi 639 movq PER_CPU_VAR(cpu_tss_rw + TSS_sp0), %rsp 640 UNWIND_HINT_EMPTY 641 642 /* Copy the IRET frame to the trampoline stack. */ 643 pushq 6*8(%rdi) /* SS */ 644 pushq 5*8(%rdi) /* RSP */ 645 pushq 4*8(%rdi) /* EFLAGS */ 646 pushq 3*8(%rdi) /* CS */ 647 pushq 2*8(%rdi) /* RIP */ 648 649 /* Push user RDI on the trampoline stack. */ 650 pushq (%rdi) 651 652 /* 653 * We are on the trampoline stack. All regs except RDI are live. 654 * We can do future final exit work right here. 655 */ 656 STACKLEAK_ERASE_NOCLOBBER 657 658 SWITCH_TO_USER_CR3_STACK scratch_reg=%rdi 659 660 /* Restore RDI. */ 661 popq %rdi 662 SWAPGS 663 INTERRUPT_RETURN 664 665 666 /* Returning to kernel space */ 667 retint_kernel: 668 #ifdef CONFIG_PREEMPTION 669 /* Interrupts are off */ 670 /* Check if we need preemption */ 671 btl $9, EFLAGS(%rsp) /* were interrupts off? */ 672 jnc 1f 673 cmpl $0, PER_CPU_VAR(__preempt_count) 674 jnz 1f 675 call preempt_schedule_irq 676 1: 677 #endif 678 /* 679 * The iretq could re-enable interrupts: 680 */ 681 TRACE_IRQS_IRETQ 682 683 GLOBAL(restore_regs_and_return_to_kernel) 684 #ifdef CONFIG_DEBUG_ENTRY 685 /* Assert that pt_regs indicates kernel mode. */ 686 testb $3, CS(%rsp) 687 jz 1f 688 ud2 689 1: 690 #endif 691 POP_REGS 692 addq $8, %rsp /* skip regs->orig_ax */ 693 /* 694 * ARCH_HAS_MEMBARRIER_SYNC_CORE rely on IRET core serialization 695 * when returning from IPI handler. 696 */ 697 INTERRUPT_RETURN 698 699 ENTRY(native_iret) 700 UNWIND_HINT_IRET_REGS 701 /* 702 * Are we returning to a stack segment from the LDT? Note: in 703 * 64-bit mode SS:RSP on the exception stack is always valid. 704 */ 705 #ifdef CONFIG_X86_ESPFIX64 706 testb $4, (SS-RIP)(%rsp) 707 jnz native_irq_return_ldt 708 #endif 709 710 .global native_irq_return_iret 711 native_irq_return_iret: 712 /* 713 * This may fault. Non-paranoid faults on return to userspace are 714 * handled by fixup_bad_iret. These include #SS, #GP, and #NP. 715 * Double-faults due to espfix64 are handled in do_double_fault. 716 * Other faults here are fatal. 717 */ 718 iretq 719 720 #ifdef CONFIG_X86_ESPFIX64 721 native_irq_return_ldt: 722 /* 723 * We are running with user GSBASE. All GPRs contain their user 724 * values. We have a percpu ESPFIX stack that is eight slots 725 * long (see ESPFIX_STACK_SIZE). espfix_waddr points to the bottom 726 * of the ESPFIX stack. 727 * 728 * We clobber RAX and RDI in this code. We stash RDI on the 729 * normal stack and RAX on the ESPFIX stack. 730 * 731 * The ESPFIX stack layout we set up looks like this: 732 * 733 * --- top of ESPFIX stack --- 734 * SS 735 * RSP 736 * RFLAGS 737 * CS 738 * RIP <-- RSP points here when we're done 739 * RAX <-- espfix_waddr points here 740 * --- bottom of ESPFIX stack --- 741 */ 742 743 pushq %rdi /* Stash user RDI */ 744 SWAPGS /* to kernel GS */ 745 SWITCH_TO_KERNEL_CR3 scratch_reg=%rdi /* to kernel CR3 */ 746 747 movq PER_CPU_VAR(espfix_waddr), %rdi 748 movq %rax, (0*8)(%rdi) /* user RAX */ 749 movq (1*8)(%rsp), %rax /* user RIP */ 750 movq %rax, (1*8)(%rdi) 751 movq (2*8)(%rsp), %rax /* user CS */ 752 movq %rax, (2*8)(%rdi) 753 movq (3*8)(%rsp), %rax /* user RFLAGS */ 754 movq %rax, (3*8)(%rdi) 755 movq (5*8)(%rsp), %rax /* user SS */ 756 movq %rax, (5*8)(%rdi) 757 movq (4*8)(%rsp), %rax /* user RSP */ 758 movq %rax, (4*8)(%rdi) 759 /* Now RAX == RSP. */ 760 761 andl $0xffff0000, %eax /* RAX = (RSP & 0xffff0000) */ 762 763 /* 764 * espfix_stack[31:16] == 0. The page tables are set up such that 765 * (espfix_stack | (X & 0xffff0000)) points to a read-only alias of 766 * espfix_waddr for any X. That is, there are 65536 RO aliases of 767 * the same page. Set up RSP so that RSP[31:16] contains the 768 * respective 16 bits of the /userspace/ RSP and RSP nonetheless 769 * still points to an RO alias of the ESPFIX stack. 770 */ 771 orq PER_CPU_VAR(espfix_stack), %rax 772 773 SWITCH_TO_USER_CR3_STACK scratch_reg=%rdi 774 SWAPGS /* to user GS */ 775 popq %rdi /* Restore user RDI */ 776 777 movq %rax, %rsp 778 UNWIND_HINT_IRET_REGS offset=8 779 780 /* 781 * At this point, we cannot write to the stack any more, but we can 782 * still read. 783 */ 784 popq %rax /* Restore user RAX */ 785 786 /* 787 * RSP now points to an ordinary IRET frame, except that the page 788 * is read-only and RSP[31:16] are preloaded with the userspace 789 * values. We can now IRET back to userspace. 790 */ 791 jmp native_irq_return_iret 792 #endif 793 END(common_interrupt) 794 _ASM_NOKPROBE(common_interrupt) 795 796 /* 797 * APIC interrupts. 798 */ 799 .macro apicinterrupt3 num sym do_sym 800 ENTRY(\sym) 801 UNWIND_HINT_IRET_REGS 802 pushq $~(\num) 803 .Lcommon_\sym: 804 call interrupt_entry 805 UNWIND_HINT_REGS indirect=1 806 call \do_sym /* rdi points to pt_regs */ 807 jmp ret_from_intr 808 END(\sym) 809 _ASM_NOKPROBE(\sym) 810 .endm 811 812 /* Make sure APIC interrupt handlers end up in the irqentry section: */ 813 #define PUSH_SECTION_IRQENTRY .pushsection .irqentry.text, "ax" 814 #define POP_SECTION_IRQENTRY .popsection 815 816 .macro apicinterrupt num sym do_sym 817 PUSH_SECTION_IRQENTRY 818 apicinterrupt3 \num \sym \do_sym 819 POP_SECTION_IRQENTRY 820 .endm 821 822 #ifdef CONFIG_SMP 823 apicinterrupt3 IRQ_MOVE_CLEANUP_VECTOR irq_move_cleanup_interrupt smp_irq_move_cleanup_interrupt 824 apicinterrupt3 REBOOT_VECTOR reboot_interrupt smp_reboot_interrupt 825 #endif 826 827 #ifdef CONFIG_X86_UV 828 apicinterrupt3 UV_BAU_MESSAGE uv_bau_message_intr1 uv_bau_message_interrupt 829 #endif 830 831 apicinterrupt LOCAL_TIMER_VECTOR apic_timer_interrupt smp_apic_timer_interrupt 832 apicinterrupt X86_PLATFORM_IPI_VECTOR x86_platform_ipi smp_x86_platform_ipi 833 834 #ifdef CONFIG_HAVE_KVM 835 apicinterrupt3 POSTED_INTR_VECTOR kvm_posted_intr_ipi smp_kvm_posted_intr_ipi 836 apicinterrupt3 POSTED_INTR_WAKEUP_VECTOR kvm_posted_intr_wakeup_ipi smp_kvm_posted_intr_wakeup_ipi 837 apicinterrupt3 POSTED_INTR_NESTED_VECTOR kvm_posted_intr_nested_ipi smp_kvm_posted_intr_nested_ipi 838 #endif 839 840 #ifdef CONFIG_X86_MCE_THRESHOLD 841 apicinterrupt THRESHOLD_APIC_VECTOR threshold_interrupt smp_threshold_interrupt 842 #endif 843 844 #ifdef CONFIG_X86_MCE_AMD 845 apicinterrupt DEFERRED_ERROR_VECTOR deferred_error_interrupt smp_deferred_error_interrupt 846 #endif 847 848 #ifdef CONFIG_X86_THERMAL_VECTOR 849 apicinterrupt THERMAL_APIC_VECTOR thermal_interrupt smp_thermal_interrupt 850 #endif 851 852 #ifdef CONFIG_SMP 853 apicinterrupt CALL_FUNCTION_SINGLE_VECTOR call_function_single_interrupt smp_call_function_single_interrupt 854 apicinterrupt CALL_FUNCTION_VECTOR call_function_interrupt smp_call_function_interrupt 855 apicinterrupt RESCHEDULE_VECTOR reschedule_interrupt smp_reschedule_interrupt 856 #endif 857 858 apicinterrupt ERROR_APIC_VECTOR error_interrupt smp_error_interrupt 859 apicinterrupt SPURIOUS_APIC_VECTOR spurious_interrupt smp_spurious_interrupt 860 861 #ifdef CONFIG_IRQ_WORK 862 apicinterrupt IRQ_WORK_VECTOR irq_work_interrupt smp_irq_work_interrupt 863 #endif 864 865 /* 866 * Exception entry points. 867 */ 868 #define CPU_TSS_IST(x) PER_CPU_VAR(cpu_tss_rw) + (TSS_ist + (x) * 8) 869 870 .macro idtentry_part do_sym, has_error_code:req, read_cr2:req, paranoid:req, shift_ist=-1, ist_offset=0 871 872 .if \paranoid 873 call paranoid_entry 874 /* returned flag: ebx=0: need swapgs on exit, ebx=1: don't need it */ 875 .else 876 call error_entry 877 .endif 878 UNWIND_HINT_REGS 879 880 .if \read_cr2 881 /* 882 * Store CR2 early so subsequent faults cannot clobber it. Use R12 as 883 * intermediate storage as RDX can be clobbered in enter_from_user_mode(). 884 * GET_CR2_INTO can clobber RAX. 885 */ 886 GET_CR2_INTO(%r12); 887 .endif 888 889 .if \shift_ist != -1 890 TRACE_IRQS_OFF_DEBUG /* reload IDT in case of recursion */ 891 .else 892 TRACE_IRQS_OFF 893 .endif 894 895 .if \paranoid == 0 896 testb $3, CS(%rsp) 897 jz .Lfrom_kernel_no_context_tracking_\@ 898 CALL_enter_from_user_mode 899 .Lfrom_kernel_no_context_tracking_\@: 900 .endif 901 902 movq %rsp, %rdi /* pt_regs pointer */ 903 904 .if \has_error_code 905 movq ORIG_RAX(%rsp), %rsi /* get error code */ 906 movq $-1, ORIG_RAX(%rsp) /* no syscall to restart */ 907 .else 908 xorl %esi, %esi /* no error code */ 909 .endif 910 911 .if \shift_ist != -1 912 subq $\ist_offset, CPU_TSS_IST(\shift_ist) 913 .endif 914 915 .if \read_cr2 916 movq %r12, %rdx /* Move CR2 into 3rd argument */ 917 .endif 918 919 call \do_sym 920 921 .if \shift_ist != -1 922 addq $\ist_offset, CPU_TSS_IST(\shift_ist) 923 .endif 924 925 .if \paranoid 926 /* this procedure expect "no swapgs" flag in ebx */ 927 jmp paranoid_exit 928 .else 929 jmp error_exit 930 .endif 931 932 .endm 933 934 /** 935 * idtentry - Generate an IDT entry stub 936 * @sym: Name of the generated entry point 937 * @do_sym: C function to be called 938 * @has_error_code: True if this IDT vector has an error code on the stack 939 * @paranoid: non-zero means that this vector may be invoked from 940 * kernel mode with user GSBASE and/or user CR3. 941 * 2 is special -- see below. 942 * @shift_ist: Set to an IST index if entries from kernel mode should 943 * decrement the IST stack so that nested entries get a 944 * fresh stack. (This is for #DB, which has a nasty habit 945 * of recursing.) 946 * @create_gap: create a 6-word stack gap when coming from kernel mode. 947 * @read_cr2: load CR2 into the 3rd argument; done before calling any C code 948 * 949 * idtentry generates an IDT stub that sets up a usable kernel context, 950 * creates struct pt_regs, and calls @do_sym. The stub has the following 951 * special behaviors: 952 * 953 * On an entry from user mode, the stub switches from the trampoline or 954 * IST stack to the normal thread stack. On an exit to user mode, the 955 * normal exit-to-usermode path is invoked. 956 * 957 * On an exit to kernel mode, if @paranoid == 0, we check for preemption, 958 * whereas we omit the preemption check if @paranoid != 0. This is purely 959 * because the implementation is simpler this way. The kernel only needs 960 * to check for asynchronous kernel preemption when IRQ handlers return. 961 * 962 * If @paranoid == 0, then the stub will handle IRET faults by pretending 963 * that the fault came from user mode. It will handle gs_change faults by 964 * pretending that the fault happened with kernel GSBASE. Since this handling 965 * is omitted for @paranoid != 0, the #GP, #SS, and #NP stubs must have 966 * @paranoid == 0. This special handling will do the wrong thing for 967 * espfix-induced #DF on IRET, so #DF must not use @paranoid == 0. 968 * 969 * @paranoid == 2 is special: the stub will never switch stacks. This is for 970 * #DF: if the thread stack is somehow unusable, we'll still get a useful OOPS. 971 */ 972 .macro idtentry sym do_sym has_error_code:req paranoid=0 shift_ist=-1 ist_offset=0 create_gap=0 read_cr2=0 973 ENTRY(\sym) 974 UNWIND_HINT_IRET_REGS offset=\has_error_code*8 975 976 /* Sanity check */ 977 .if \shift_ist != -1 && \paranoid != 1 978 .error "using shift_ist requires paranoid=1" 979 .endif 980 981 .if \create_gap && \paranoid 982 .error "using create_gap requires paranoid=0" 983 .endif 984 985 ASM_CLAC 986 987 .if \has_error_code == 0 988 pushq $-1 /* ORIG_RAX: no syscall to restart */ 989 .endif 990 991 .if \paranoid == 1 992 testb $3, CS-ORIG_RAX(%rsp) /* If coming from userspace, switch stacks */ 993 jnz .Lfrom_usermode_switch_stack_\@ 994 .endif 995 996 .if \create_gap == 1 997 /* 998 * If coming from kernel space, create a 6-word gap to allow the 999 * int3 handler to emulate a call instruction. 1000 */ 1001 testb $3, CS-ORIG_RAX(%rsp) 1002 jnz .Lfrom_usermode_no_gap_\@ 1003 .rept 6 1004 pushq 5*8(%rsp) 1005 .endr 1006 UNWIND_HINT_IRET_REGS offset=8 1007 .Lfrom_usermode_no_gap_\@: 1008 .endif 1009 1010 idtentry_part \do_sym, \has_error_code, \read_cr2, \paranoid, \shift_ist, \ist_offset 1011 1012 .if \paranoid == 1 1013 /* 1014 * Entry from userspace. Switch stacks and treat it 1015 * as a normal entry. This means that paranoid handlers 1016 * run in real process context if user_mode(regs). 1017 */ 1018 .Lfrom_usermode_switch_stack_\@: 1019 idtentry_part \do_sym, \has_error_code, \read_cr2, paranoid=0 1020 .endif 1021 1022 _ASM_NOKPROBE(\sym) 1023 END(\sym) 1024 .endm 1025 1026 idtentry divide_error do_divide_error has_error_code=0 1027 idtentry overflow do_overflow has_error_code=0 1028 idtentry bounds do_bounds has_error_code=0 1029 idtentry invalid_op do_invalid_op has_error_code=0 1030 idtentry device_not_available do_device_not_available has_error_code=0 1031 idtentry double_fault do_double_fault has_error_code=1 paranoid=2 read_cr2=1 1032 idtentry coprocessor_segment_overrun do_coprocessor_segment_overrun has_error_code=0 1033 idtentry invalid_TSS do_invalid_TSS has_error_code=1 1034 idtentry segment_not_present do_segment_not_present has_error_code=1 1035 idtentry spurious_interrupt_bug do_spurious_interrupt_bug has_error_code=0 1036 idtentry coprocessor_error do_coprocessor_error has_error_code=0 1037 idtentry alignment_check do_alignment_check has_error_code=1 1038 idtentry simd_coprocessor_error do_simd_coprocessor_error has_error_code=0 1039 1040 1041 /* 1042 * Reload gs selector with exception handling 1043 * edi: new selector 1044 */ 1045 ENTRY(native_load_gs_index) 1046 FRAME_BEGIN 1047 pushfq 1048 DISABLE_INTERRUPTS(CLBR_ANY & ~CLBR_RDI) 1049 TRACE_IRQS_OFF 1050 SWAPGS 1051 .Lgs_change: 1052 movl %edi, %gs 1053 2: ALTERNATIVE "", "mfence", X86_BUG_SWAPGS_FENCE 1054 SWAPGS 1055 TRACE_IRQS_FLAGS (%rsp) 1056 popfq 1057 FRAME_END 1058 ret 1059 ENDPROC(native_load_gs_index) 1060 EXPORT_SYMBOL(native_load_gs_index) 1061 1062 _ASM_EXTABLE(.Lgs_change, .Lbad_gs) 1063 .section .fixup, "ax" 1064 /* running with kernelgs */ 1065 .Lbad_gs: 1066 SWAPGS /* switch back to user gs */ 1067 .macro ZAP_GS 1068 /* This can't be a string because the preprocessor needs to see it. */ 1069 movl $__USER_DS, %eax 1070 movl %eax, %gs 1071 .endm 1072 ALTERNATIVE "", "ZAP_GS", X86_BUG_NULL_SEG 1073 xorl %eax, %eax 1074 movl %eax, %gs 1075 jmp 2b 1076 .previous 1077 1078 /* Call softirq on interrupt stack. Interrupts are off. */ 1079 ENTRY(do_softirq_own_stack) 1080 pushq %rbp 1081 mov %rsp, %rbp 1082 ENTER_IRQ_STACK regs=0 old_rsp=%r11 1083 call __do_softirq 1084 LEAVE_IRQ_STACK regs=0 1085 leaveq 1086 ret 1087 ENDPROC(do_softirq_own_stack) 1088 1089 #ifdef CONFIG_XEN_PV 1090 idtentry hypervisor_callback xen_do_hypervisor_callback has_error_code=0 1091 1092 /* 1093 * A note on the "critical region" in our callback handler. 1094 * We want to avoid stacking callback handlers due to events occurring 1095 * during handling of the last event. To do this, we keep events disabled 1096 * until we've done all processing. HOWEVER, we must enable events before 1097 * popping the stack frame (can't be done atomically) and so it would still 1098 * be possible to get enough handler activations to overflow the stack. 1099 * Although unlikely, bugs of that kind are hard to track down, so we'd 1100 * like to avoid the possibility. 1101 * So, on entry to the handler we detect whether we interrupted an 1102 * existing activation in its critical region -- if so, we pop the current 1103 * activation and restart the handler using the previous one. 1104 */ 1105 ENTRY(xen_do_hypervisor_callback) /* do_hypervisor_callback(struct *pt_regs) */ 1106 1107 /* 1108 * Since we don't modify %rdi, evtchn_do_upall(struct *pt_regs) will 1109 * see the correct pointer to the pt_regs 1110 */ 1111 UNWIND_HINT_FUNC 1112 movq %rdi, %rsp /* we don't return, adjust the stack frame */ 1113 UNWIND_HINT_REGS 1114 1115 ENTER_IRQ_STACK old_rsp=%r10 1116 call xen_evtchn_do_upcall 1117 LEAVE_IRQ_STACK 1118 1119 #ifndef CONFIG_PREEMPTION 1120 call xen_maybe_preempt_hcall 1121 #endif 1122 jmp error_exit 1123 END(xen_do_hypervisor_callback) 1124 1125 /* 1126 * Hypervisor uses this for application faults while it executes. 1127 * We get here for two reasons: 1128 * 1. Fault while reloading DS, ES, FS or GS 1129 * 2. Fault while executing IRET 1130 * Category 1 we do not need to fix up as Xen has already reloaded all segment 1131 * registers that could be reloaded and zeroed the others. 1132 * Category 2 we fix up by killing the current process. We cannot use the 1133 * normal Linux return path in this case because if we use the IRET hypercall 1134 * to pop the stack frame we end up in an infinite loop of failsafe callbacks. 1135 * We distinguish between categories by comparing each saved segment register 1136 * with its current contents: any discrepancy means we in category 1. 1137 */ 1138 ENTRY(xen_failsafe_callback) 1139 UNWIND_HINT_EMPTY 1140 movl %ds, %ecx 1141 cmpw %cx, 0x10(%rsp) 1142 jne 1f 1143 movl %es, %ecx 1144 cmpw %cx, 0x18(%rsp) 1145 jne 1f 1146 movl %fs, %ecx 1147 cmpw %cx, 0x20(%rsp) 1148 jne 1f 1149 movl %gs, %ecx 1150 cmpw %cx, 0x28(%rsp) 1151 jne 1f 1152 /* All segments match their saved values => Category 2 (Bad IRET). */ 1153 movq (%rsp), %rcx 1154 movq 8(%rsp), %r11 1155 addq $0x30, %rsp 1156 pushq $0 /* RIP */ 1157 UNWIND_HINT_IRET_REGS offset=8 1158 jmp general_protection 1159 1: /* Segment mismatch => Category 1 (Bad segment). Retry the IRET. */ 1160 movq (%rsp), %rcx 1161 movq 8(%rsp), %r11 1162 addq $0x30, %rsp 1163 UNWIND_HINT_IRET_REGS 1164 pushq $-1 /* orig_ax = -1 => not a system call */ 1165 PUSH_AND_CLEAR_REGS 1166 ENCODE_FRAME_POINTER 1167 jmp error_exit 1168 END(xen_failsafe_callback) 1169 #endif /* CONFIG_XEN_PV */ 1170 1171 #ifdef CONFIG_XEN_PVHVM 1172 apicinterrupt3 HYPERVISOR_CALLBACK_VECTOR \ 1173 xen_hvm_callback_vector xen_evtchn_do_upcall 1174 #endif 1175 1176 1177 #if IS_ENABLED(CONFIG_HYPERV) 1178 apicinterrupt3 HYPERVISOR_CALLBACK_VECTOR \ 1179 hyperv_callback_vector hyperv_vector_handler 1180 1181 apicinterrupt3 HYPERV_REENLIGHTENMENT_VECTOR \ 1182 hyperv_reenlightenment_vector hyperv_reenlightenment_intr 1183 1184 apicinterrupt3 HYPERV_STIMER0_VECTOR \ 1185 hv_stimer0_callback_vector hv_stimer0_vector_handler 1186 #endif /* CONFIG_HYPERV */ 1187 1188 #if IS_ENABLED(CONFIG_ACRN_GUEST) 1189 apicinterrupt3 HYPERVISOR_CALLBACK_VECTOR \ 1190 acrn_hv_callback_vector acrn_hv_vector_handler 1191 #endif 1192 1193 idtentry debug do_debug has_error_code=0 paranoid=1 shift_ist=IST_INDEX_DB ist_offset=DB_STACK_OFFSET 1194 idtentry int3 do_int3 has_error_code=0 create_gap=1 1195 idtentry stack_segment do_stack_segment has_error_code=1 1196 1197 #ifdef CONFIG_XEN_PV 1198 idtentry xennmi do_nmi has_error_code=0 1199 idtentry xendebug do_debug has_error_code=0 1200 #endif 1201 1202 idtentry general_protection do_general_protection has_error_code=1 1203 idtentry page_fault do_page_fault has_error_code=1 read_cr2=1 1204 1205 #ifdef CONFIG_KVM_GUEST 1206 idtentry async_page_fault do_async_page_fault has_error_code=1 read_cr2=1 1207 #endif 1208 1209 #ifdef CONFIG_X86_MCE 1210 idtentry machine_check do_mce has_error_code=0 paranoid=1 1211 #endif 1212 1213 /* 1214 * Save all registers in pt_regs, and switch gs if needed. 1215 * Use slow, but surefire "are we in kernel?" check. 1216 * Return: ebx=0: need swapgs on exit, ebx=1: otherwise 1217 */ 1218 ENTRY(paranoid_entry) 1219 UNWIND_HINT_FUNC 1220 cld 1221 PUSH_AND_CLEAR_REGS save_ret=1 1222 ENCODE_FRAME_POINTER 8 1223 movl $1, %ebx 1224 movl $MSR_GS_BASE, %ecx 1225 rdmsr 1226 testl %edx, %edx 1227 js 1f /* negative -> in kernel */ 1228 SWAPGS 1229 xorl %ebx, %ebx 1230 1231 1: 1232 /* 1233 * Always stash CR3 in %r14. This value will be restored, 1234 * verbatim, at exit. Needed if paranoid_entry interrupted 1235 * another entry that already switched to the user CR3 value 1236 * but has not yet returned to userspace. 1237 * 1238 * This is also why CS (stashed in the "iret frame" by the 1239 * hardware at entry) can not be used: this may be a return 1240 * to kernel code, but with a user CR3 value. 1241 */ 1242 SAVE_AND_SWITCH_TO_KERNEL_CR3 scratch_reg=%rax save_reg=%r14 1243 1244 /* 1245 * The above SAVE_AND_SWITCH_TO_KERNEL_CR3 macro doesn't do an 1246 * unconditional CR3 write, even in the PTI case. So do an lfence 1247 * to prevent GS speculation, regardless of whether PTI is enabled. 1248 */ 1249 FENCE_SWAPGS_KERNEL_ENTRY 1250 1251 ret 1252 END(paranoid_entry) 1253 1254 /* 1255 * "Paranoid" exit path from exception stack. This is invoked 1256 * only on return from non-NMI IST interrupts that came 1257 * from kernel space. 1258 * 1259 * We may be returning to very strange contexts (e.g. very early 1260 * in syscall entry), so checking for preemption here would 1261 * be complicated. Fortunately, we there's no good reason 1262 * to try to handle preemption here. 1263 * 1264 * On entry, ebx is "no swapgs" flag (1: don't need swapgs, 0: need it) 1265 */ 1266 ENTRY(paranoid_exit) 1267 UNWIND_HINT_REGS 1268 DISABLE_INTERRUPTS(CLBR_ANY) 1269 TRACE_IRQS_OFF_DEBUG 1270 testl %ebx, %ebx /* swapgs needed? */ 1271 jnz .Lparanoid_exit_no_swapgs 1272 TRACE_IRQS_IRETQ 1273 /* Always restore stashed CR3 value (see paranoid_entry) */ 1274 RESTORE_CR3 scratch_reg=%rbx save_reg=%r14 1275 SWAPGS_UNSAFE_STACK 1276 jmp .Lparanoid_exit_restore 1277 .Lparanoid_exit_no_swapgs: 1278 TRACE_IRQS_IRETQ_DEBUG 1279 /* Always restore stashed CR3 value (see paranoid_entry) */ 1280 RESTORE_CR3 scratch_reg=%rbx save_reg=%r14 1281 .Lparanoid_exit_restore: 1282 jmp restore_regs_and_return_to_kernel 1283 END(paranoid_exit) 1284 1285 /* 1286 * Save all registers in pt_regs, and switch GS if needed. 1287 */ 1288 ENTRY(error_entry) 1289 UNWIND_HINT_FUNC 1290 cld 1291 PUSH_AND_CLEAR_REGS save_ret=1 1292 ENCODE_FRAME_POINTER 8 1293 testb $3, CS+8(%rsp) 1294 jz .Lerror_kernelspace 1295 1296 /* 1297 * We entered from user mode or we're pretending to have entered 1298 * from user mode due to an IRET fault. 1299 */ 1300 SWAPGS 1301 FENCE_SWAPGS_USER_ENTRY 1302 /* We have user CR3. Change to kernel CR3. */ 1303 SWITCH_TO_KERNEL_CR3 scratch_reg=%rax 1304 1305 .Lerror_entry_from_usermode_after_swapgs: 1306 /* Put us onto the real thread stack. */ 1307 popq %r12 /* save return addr in %12 */ 1308 movq %rsp, %rdi /* arg0 = pt_regs pointer */ 1309 call sync_regs 1310 movq %rax, %rsp /* switch stack */ 1311 ENCODE_FRAME_POINTER 1312 pushq %r12 1313 ret 1314 1315 .Lerror_entry_done_lfence: 1316 FENCE_SWAPGS_KERNEL_ENTRY 1317 .Lerror_entry_done: 1318 ret 1319 1320 /* 1321 * There are two places in the kernel that can potentially fault with 1322 * usergs. Handle them here. B stepping K8s sometimes report a 1323 * truncated RIP for IRET exceptions returning to compat mode. Check 1324 * for these here too. 1325 */ 1326 .Lerror_kernelspace: 1327 leaq native_irq_return_iret(%rip), %rcx 1328 cmpq %rcx, RIP+8(%rsp) 1329 je .Lerror_bad_iret 1330 movl %ecx, %eax /* zero extend */ 1331 cmpq %rax, RIP+8(%rsp) 1332 je .Lbstep_iret 1333 cmpq $.Lgs_change, RIP+8(%rsp) 1334 jne .Lerror_entry_done_lfence 1335 1336 /* 1337 * hack: .Lgs_change can fail with user gsbase. If this happens, fix up 1338 * gsbase and proceed. We'll fix up the exception and land in 1339 * .Lgs_change's error handler with kernel gsbase. 1340 */ 1341 SWAPGS 1342 FENCE_SWAPGS_USER_ENTRY 1343 SWITCH_TO_KERNEL_CR3 scratch_reg=%rax 1344 jmp .Lerror_entry_done 1345 1346 .Lbstep_iret: 1347 /* Fix truncated RIP */ 1348 movq %rcx, RIP+8(%rsp) 1349 /* fall through */ 1350 1351 .Lerror_bad_iret: 1352 /* 1353 * We came from an IRET to user mode, so we have user 1354 * gsbase and CR3. Switch to kernel gsbase and CR3: 1355 */ 1356 SWAPGS 1357 FENCE_SWAPGS_USER_ENTRY 1358 SWITCH_TO_KERNEL_CR3 scratch_reg=%rax 1359 1360 /* 1361 * Pretend that the exception came from user mode: set up pt_regs 1362 * as if we faulted immediately after IRET. 1363 */ 1364 mov %rsp, %rdi 1365 call fixup_bad_iret 1366 mov %rax, %rsp 1367 jmp .Lerror_entry_from_usermode_after_swapgs 1368 END(error_entry) 1369 1370 ENTRY(error_exit) 1371 UNWIND_HINT_REGS 1372 DISABLE_INTERRUPTS(CLBR_ANY) 1373 TRACE_IRQS_OFF 1374 testb $3, CS(%rsp) 1375 jz retint_kernel 1376 jmp retint_user 1377 END(error_exit) 1378 1379 /* 1380 * Runs on exception stack. Xen PV does not go through this path at all, 1381 * so we can use real assembly here. 1382 * 1383 * Registers: 1384 * %r14: Used to save/restore the CR3 of the interrupted context 1385 * when PAGE_TABLE_ISOLATION is in use. Do not clobber. 1386 */ 1387 ENTRY(nmi) 1388 UNWIND_HINT_IRET_REGS 1389 1390 /* 1391 * We allow breakpoints in NMIs. If a breakpoint occurs, then 1392 * the iretq it performs will take us out of NMI context. 1393 * This means that we can have nested NMIs where the next 1394 * NMI is using the top of the stack of the previous NMI. We 1395 * can't let it execute because the nested NMI will corrupt the 1396 * stack of the previous NMI. NMI handlers are not re-entrant 1397 * anyway. 1398 * 1399 * To handle this case we do the following: 1400 * Check the a special location on the stack that contains 1401 * a variable that is set when NMIs are executing. 1402 * The interrupted task's stack is also checked to see if it 1403 * is an NMI stack. 1404 * If the variable is not set and the stack is not the NMI 1405 * stack then: 1406 * o Set the special variable on the stack 1407 * o Copy the interrupt frame into an "outermost" location on the 1408 * stack 1409 * o Copy the interrupt frame into an "iret" location on the stack 1410 * o Continue processing the NMI 1411 * If the variable is set or the previous stack is the NMI stack: 1412 * o Modify the "iret" location to jump to the repeat_nmi 1413 * o return back to the first NMI 1414 * 1415 * Now on exit of the first NMI, we first clear the stack variable 1416 * The NMI stack will tell any nested NMIs at that point that it is 1417 * nested. Then we pop the stack normally with iret, and if there was 1418 * a nested NMI that updated the copy interrupt stack frame, a 1419 * jump will be made to the repeat_nmi code that will handle the second 1420 * NMI. 1421 * 1422 * However, espfix prevents us from directly returning to userspace 1423 * with a single IRET instruction. Similarly, IRET to user mode 1424 * can fault. We therefore handle NMIs from user space like 1425 * other IST entries. 1426 */ 1427 1428 ASM_CLAC 1429 1430 /* Use %rdx as our temp variable throughout */ 1431 pushq %rdx 1432 1433 testb $3, CS-RIP+8(%rsp) 1434 jz .Lnmi_from_kernel 1435 1436 /* 1437 * NMI from user mode. We need to run on the thread stack, but we 1438 * can't go through the normal entry paths: NMIs are masked, and 1439 * we don't want to enable interrupts, because then we'll end 1440 * up in an awkward situation in which IRQs are on but NMIs 1441 * are off. 1442 * 1443 * We also must not push anything to the stack before switching 1444 * stacks lest we corrupt the "NMI executing" variable. 1445 */ 1446 1447 swapgs 1448 cld 1449 FENCE_SWAPGS_USER_ENTRY 1450 SWITCH_TO_KERNEL_CR3 scratch_reg=%rdx 1451 movq %rsp, %rdx 1452 movq PER_CPU_VAR(cpu_current_top_of_stack), %rsp 1453 UNWIND_HINT_IRET_REGS base=%rdx offset=8 1454 pushq 5*8(%rdx) /* pt_regs->ss */ 1455 pushq 4*8(%rdx) /* pt_regs->rsp */ 1456 pushq 3*8(%rdx) /* pt_regs->flags */ 1457 pushq 2*8(%rdx) /* pt_regs->cs */ 1458 pushq 1*8(%rdx) /* pt_regs->rip */ 1459 UNWIND_HINT_IRET_REGS 1460 pushq $-1 /* pt_regs->orig_ax */ 1461 PUSH_AND_CLEAR_REGS rdx=(%rdx) 1462 ENCODE_FRAME_POINTER 1463 1464 /* 1465 * At this point we no longer need to worry about stack damage 1466 * due to nesting -- we're on the normal thread stack and we're 1467 * done with the NMI stack. 1468 */ 1469 1470 movq %rsp, %rdi 1471 movq $-1, %rsi 1472 call do_nmi 1473 1474 /* 1475 * Return back to user mode. We must *not* do the normal exit 1476 * work, because we don't want to enable interrupts. 1477 */ 1478 jmp swapgs_restore_regs_and_return_to_usermode 1479 1480 .Lnmi_from_kernel: 1481 /* 1482 * Here's what our stack frame will look like: 1483 * +---------------------------------------------------------+ 1484 * | original SS | 1485 * | original Return RSP | 1486 * | original RFLAGS | 1487 * | original CS | 1488 * | original RIP | 1489 * +---------------------------------------------------------+ 1490 * | temp storage for rdx | 1491 * +---------------------------------------------------------+ 1492 * | "NMI executing" variable | 1493 * +---------------------------------------------------------+ 1494 * | iret SS } Copied from "outermost" frame | 1495 * | iret Return RSP } on each loop iteration; overwritten | 1496 * | iret RFLAGS } by a nested NMI to force another | 1497 * | iret CS } iteration if needed. | 1498 * | iret RIP } | 1499 * +---------------------------------------------------------+ 1500 * | outermost SS } initialized in first_nmi; | 1501 * | outermost Return RSP } will not be changed before | 1502 * | outermost RFLAGS } NMI processing is done. | 1503 * | outermost CS } Copied to "iret" frame on each | 1504 * | outermost RIP } iteration. | 1505 * +---------------------------------------------------------+ 1506 * | pt_regs | 1507 * +---------------------------------------------------------+ 1508 * 1509 * The "original" frame is used by hardware. Before re-enabling 1510 * NMIs, we need to be done with it, and we need to leave enough 1511 * space for the asm code here. 1512 * 1513 * We return by executing IRET while RSP points to the "iret" frame. 1514 * That will either return for real or it will loop back into NMI 1515 * processing. 1516 * 1517 * The "outermost" frame is copied to the "iret" frame on each 1518 * iteration of the loop, so each iteration starts with the "iret" 1519 * frame pointing to the final return target. 1520 */ 1521 1522 /* 1523 * Determine whether we're a nested NMI. 1524 * 1525 * If we interrupted kernel code between repeat_nmi and 1526 * end_repeat_nmi, then we are a nested NMI. We must not 1527 * modify the "iret" frame because it's being written by 1528 * the outer NMI. That's okay; the outer NMI handler is 1529 * about to about to call do_nmi anyway, so we can just 1530 * resume the outer NMI. 1531 */ 1532 1533 movq $repeat_nmi, %rdx 1534 cmpq 8(%rsp), %rdx 1535 ja 1f 1536 movq $end_repeat_nmi, %rdx 1537 cmpq 8(%rsp), %rdx 1538 ja nested_nmi_out 1539 1: 1540 1541 /* 1542 * Now check "NMI executing". If it's set, then we're nested. 1543 * This will not detect if we interrupted an outer NMI just 1544 * before IRET. 1545 */ 1546 cmpl $1, -8(%rsp) 1547 je nested_nmi 1548 1549 /* 1550 * Now test if the previous stack was an NMI stack. This covers 1551 * the case where we interrupt an outer NMI after it clears 1552 * "NMI executing" but before IRET. We need to be careful, though: 1553 * there is one case in which RSP could point to the NMI stack 1554 * despite there being no NMI active: naughty userspace controls 1555 * RSP at the very beginning of the SYSCALL targets. We can 1556 * pull a fast one on naughty userspace, though: we program 1557 * SYSCALL to mask DF, so userspace cannot cause DF to be set 1558 * if it controls the kernel's RSP. We set DF before we clear 1559 * "NMI executing". 1560 */ 1561 lea 6*8(%rsp), %rdx 1562 /* Compare the NMI stack (rdx) with the stack we came from (4*8(%rsp)) */ 1563 cmpq %rdx, 4*8(%rsp) 1564 /* If the stack pointer is above the NMI stack, this is a normal NMI */ 1565 ja first_nmi 1566 1567 subq $EXCEPTION_STKSZ, %rdx 1568 cmpq %rdx, 4*8(%rsp) 1569 /* If it is below the NMI stack, it is a normal NMI */ 1570 jb first_nmi 1571 1572 /* Ah, it is within the NMI stack. */ 1573 1574 testb $(X86_EFLAGS_DF >> 8), (3*8 + 1)(%rsp) 1575 jz first_nmi /* RSP was user controlled. */ 1576 1577 /* This is a nested NMI. */ 1578 1579 nested_nmi: 1580 /* 1581 * Modify the "iret" frame to point to repeat_nmi, forcing another 1582 * iteration of NMI handling. 1583 */ 1584 subq $8, %rsp 1585 leaq -10*8(%rsp), %rdx 1586 pushq $__KERNEL_DS 1587 pushq %rdx 1588 pushfq 1589 pushq $__KERNEL_CS 1590 pushq $repeat_nmi 1591 1592 /* Put stack back */ 1593 addq $(6*8), %rsp 1594 1595 nested_nmi_out: 1596 popq %rdx 1597 1598 /* We are returning to kernel mode, so this cannot result in a fault. */ 1599 iretq 1600 1601 first_nmi: 1602 /* Restore rdx. */ 1603 movq (%rsp), %rdx 1604 1605 /* Make room for "NMI executing". */ 1606 pushq $0 1607 1608 /* Leave room for the "iret" frame */ 1609 subq $(5*8), %rsp 1610 1611 /* Copy the "original" frame to the "outermost" frame */ 1612 .rept 5 1613 pushq 11*8(%rsp) 1614 .endr 1615 UNWIND_HINT_IRET_REGS 1616 1617 /* Everything up to here is safe from nested NMIs */ 1618 1619 #ifdef CONFIG_DEBUG_ENTRY 1620 /* 1621 * For ease of testing, unmask NMIs right away. Disabled by 1622 * default because IRET is very expensive. 1623 */ 1624 pushq $0 /* SS */ 1625 pushq %rsp /* RSP (minus 8 because of the previous push) */ 1626 addq $8, (%rsp) /* Fix up RSP */ 1627 pushfq /* RFLAGS */ 1628 pushq $__KERNEL_CS /* CS */ 1629 pushq $1f /* RIP */ 1630 iretq /* continues at repeat_nmi below */ 1631 UNWIND_HINT_IRET_REGS 1632 1: 1633 #endif 1634 1635 repeat_nmi: 1636 /* 1637 * If there was a nested NMI, the first NMI's iret will return 1638 * here. But NMIs are still enabled and we can take another 1639 * nested NMI. The nested NMI checks the interrupted RIP to see 1640 * if it is between repeat_nmi and end_repeat_nmi, and if so 1641 * it will just return, as we are about to repeat an NMI anyway. 1642 * This makes it safe to copy to the stack frame that a nested 1643 * NMI will update. 1644 * 1645 * RSP is pointing to "outermost RIP". gsbase is unknown, but, if 1646 * we're repeating an NMI, gsbase has the same value that it had on 1647 * the first iteration. paranoid_entry will load the kernel 1648 * gsbase if needed before we call do_nmi. "NMI executing" 1649 * is zero. 1650 */ 1651 movq $1, 10*8(%rsp) /* Set "NMI executing". */ 1652 1653 /* 1654 * Copy the "outermost" frame to the "iret" frame. NMIs that nest 1655 * here must not modify the "iret" frame while we're writing to 1656 * it or it will end up containing garbage. 1657 */ 1658 addq $(10*8), %rsp 1659 .rept 5 1660 pushq -6*8(%rsp) 1661 .endr 1662 subq $(5*8), %rsp 1663 end_repeat_nmi: 1664 1665 /* 1666 * Everything below this point can be preempted by a nested NMI. 1667 * If this happens, then the inner NMI will change the "iret" 1668 * frame to point back to repeat_nmi. 1669 */ 1670 pushq $-1 /* ORIG_RAX: no syscall to restart */ 1671 1672 /* 1673 * Use paranoid_entry to handle SWAPGS, but no need to use paranoid_exit 1674 * as we should not be calling schedule in NMI context. 1675 * Even with normal interrupts enabled. An NMI should not be 1676 * setting NEED_RESCHED or anything that normal interrupts and 1677 * exceptions might do. 1678 */ 1679 call paranoid_entry 1680 UNWIND_HINT_REGS 1681 1682 /* paranoidentry do_nmi, 0; without TRACE_IRQS_OFF */ 1683 movq %rsp, %rdi 1684 movq $-1, %rsi 1685 call do_nmi 1686 1687 /* Always restore stashed CR3 value (see paranoid_entry) */ 1688 RESTORE_CR3 scratch_reg=%r15 save_reg=%r14 1689 1690 testl %ebx, %ebx /* swapgs needed? */ 1691 jnz nmi_restore 1692 nmi_swapgs: 1693 SWAPGS_UNSAFE_STACK 1694 nmi_restore: 1695 POP_REGS 1696 1697 /* 1698 * Skip orig_ax and the "outermost" frame to point RSP at the "iret" 1699 * at the "iret" frame. 1700 */ 1701 addq $6*8, %rsp 1702 1703 /* 1704 * Clear "NMI executing". Set DF first so that we can easily 1705 * distinguish the remaining code between here and IRET from 1706 * the SYSCALL entry and exit paths. 1707 * 1708 * We arguably should just inspect RIP instead, but I (Andy) wrote 1709 * this code when I had the misapprehension that Xen PV supported 1710 * NMIs, and Xen PV would break that approach. 1711 */ 1712 std 1713 movq $0, 5*8(%rsp) /* clear "NMI executing" */ 1714 1715 /* 1716 * iretq reads the "iret" frame and exits the NMI stack in a 1717 * single instruction. We are returning to kernel mode, so this 1718 * cannot result in a fault. Similarly, we don't need to worry 1719 * about espfix64 on the way back to kernel mode. 1720 */ 1721 iretq 1722 END(nmi) 1723 1724 #ifndef CONFIG_IA32_EMULATION 1725 /* 1726 * This handles SYSCALL from 32-bit code. There is no way to program 1727 * MSRs to fully disable 32-bit SYSCALL. 1728 */ 1729 ENTRY(ignore_sysret) 1730 UNWIND_HINT_EMPTY 1731 mov $-ENOSYS, %eax 1732 sysret 1733 END(ignore_sysret) 1734 #endif 1735 1736 ENTRY(rewind_stack_do_exit) 1737 UNWIND_HINT_FUNC 1738 /* Prevent any naive code from trying to unwind to our caller. */ 1739 xorl %ebp, %ebp 1740 1741 movq PER_CPU_VAR(cpu_current_top_of_stack), %rax 1742 leaq -PTREGS_SIZE(%rax), %rsp 1743 UNWIND_HINT_REGS 1744 1745 call do_exit 1746 END(rewind_stack_do_exit)