root/arch/x86/entry/calling.h

INCLUDED FROM

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 #include <linux/jump_label.h>
   3 #include <asm/unwind_hints.h>
   4 #include <asm/cpufeatures.h>
   5 #include <asm/page_types.h>
   6 #include <asm/percpu.h>
   7 #include <asm/asm-offsets.h>
   8 #include <asm/processor-flags.h>
   9 
  10 /*
  11 
  12  x86 function call convention, 64-bit:
  13  -------------------------------------
  14   arguments           |  callee-saved      | extra caller-saved | return
  15  [callee-clobbered]   |                    | [callee-clobbered] |
  16  ---------------------------------------------------------------------------
  17  rdi rsi rdx rcx r8-9 | rbx rbp [*] r12-15 | r10-11             | rax, rdx [**]
  18 
  19  ( rsp is obviously invariant across normal function calls. (gcc can 'merge'
  20    functions when it sees tail-call optimization possibilities) rflags is
  21    clobbered. Leftover arguments are passed over the stack frame.)
  22 
  23  [*]  In the frame-pointers case rbp is fixed to the stack frame.
  24 
  25  [**] for struct return values wider than 64 bits the return convention is a
  26       bit more complex: up to 128 bits width we return small structures
  27       straight in rax, rdx. For structures larger than that (3 words or
  28       larger) the caller puts a pointer to an on-stack return struct
  29       [allocated in the caller's stack frame] into the first argument - i.e.
  30       into rdi. All other arguments shift up by one in this case.
  31       Fortunately this case is rare in the kernel.
  32 
  33 For 32-bit we have the following conventions - kernel is built with
  34 -mregparm=3 and -freg-struct-return:
  35 
  36  x86 function calling convention, 32-bit:
  37  ----------------------------------------
  38   arguments         | callee-saved        | extra caller-saved | return
  39  [callee-clobbered] |                     | [callee-clobbered] |
  40  -------------------------------------------------------------------------
  41  eax edx ecx        | ebx edi esi ebp [*] | <none>             | eax, edx [**]
  42 
  43  ( here too esp is obviously invariant across normal function calls. eflags
  44    is clobbered. Leftover arguments are passed over the stack frame. )
  45 
  46  [*]  In the frame-pointers case ebp is fixed to the stack frame.
  47 
  48  [**] We build with -freg-struct-return, which on 32-bit means similar
  49       semantics as on 64-bit: edx can be used for a second return value
  50       (i.e. covering integer and structure sizes up to 64 bits) - after that
  51       it gets more complex and more expensive: 3-word or larger struct returns
  52       get done in the caller's frame and the pointer to the return struct goes
  53       into regparm0, i.e. eax - the other arguments shift up and the
  54       function's register parameters degenerate to regparm=2 in essence.
  55 
  56 */
  57 
  58 #ifdef CONFIG_X86_64
  59 
  60 /*
  61  * 64-bit system call stack frame layout defines and helpers,
  62  * for assembly code:
  63  */
  64 
  65 /* The layout forms the "struct pt_regs" on the stack: */
  66 /*
  67  * C ABI says these regs are callee-preserved. They aren't saved on kernel entry
  68  * unless syscall needs a complete, fully filled "struct pt_regs".
  69  */
  70 #define R15             0*8
  71 #define R14             1*8
  72 #define R13             2*8
  73 #define R12             3*8
  74 #define RBP             4*8
  75 #define RBX             5*8
  76 /* These regs are callee-clobbered. Always saved on kernel entry. */
  77 #define R11             6*8
  78 #define R10             7*8
  79 #define R9              8*8
  80 #define R8              9*8
  81 #define RAX             10*8
  82 #define RCX             11*8
  83 #define RDX             12*8
  84 #define RSI             13*8
  85 #define RDI             14*8
  86 /*
  87  * On syscall entry, this is syscall#. On CPU exception, this is error code.
  88  * On hw interrupt, it's IRQ number:
  89  */
  90 #define ORIG_RAX        15*8
  91 /* Return frame for iretq */
  92 #define RIP             16*8
  93 #define CS              17*8
  94 #define EFLAGS          18*8
  95 #define RSP             19*8
  96 #define SS              20*8
  97 
  98 #define SIZEOF_PTREGS   21*8
  99 
 100 .macro PUSH_AND_CLEAR_REGS rdx=%rdx rax=%rax save_ret=0
 101         .if \save_ret
 102         pushq   %rsi            /* pt_regs->si */
 103         movq    8(%rsp), %rsi   /* temporarily store the return address in %rsi */
 104         movq    %rdi, 8(%rsp)   /* pt_regs->di (overwriting original return address) */
 105         .else
 106         pushq   %rdi            /* pt_regs->di */
 107         pushq   %rsi            /* pt_regs->si */
 108         .endif
 109         pushq   \rdx            /* pt_regs->dx */
 110         pushq   %rcx            /* pt_regs->cx */
 111         pushq   \rax            /* pt_regs->ax */
 112         pushq   %r8             /* pt_regs->r8 */
 113         pushq   %r9             /* pt_regs->r9 */
 114         pushq   %r10            /* pt_regs->r10 */
 115         pushq   %r11            /* pt_regs->r11 */
 116         pushq   %rbx            /* pt_regs->rbx */
 117         pushq   %rbp            /* pt_regs->rbp */
 118         pushq   %r12            /* pt_regs->r12 */
 119         pushq   %r13            /* pt_regs->r13 */
 120         pushq   %r14            /* pt_regs->r14 */
 121         pushq   %r15            /* pt_regs->r15 */
 122         UNWIND_HINT_REGS
 123 
 124         .if \save_ret
 125         pushq   %rsi            /* return address on top of stack */
 126         .endif
 127 
 128         /*
 129          * Sanitize registers of values that a speculation attack might
 130          * otherwise want to exploit. The lower registers are likely clobbered
 131          * well before they could be put to use in a speculative execution
 132          * gadget.
 133          */
 134         xorl    %edx,  %edx     /* nospec dx  */
 135         xorl    %ecx,  %ecx     /* nospec cx  */
 136         xorl    %r8d,  %r8d     /* nospec r8  */
 137         xorl    %r9d,  %r9d     /* nospec r9  */
 138         xorl    %r10d, %r10d    /* nospec r10 */
 139         xorl    %r11d, %r11d    /* nospec r11 */
 140         xorl    %ebx,  %ebx     /* nospec rbx */
 141         xorl    %ebp,  %ebp     /* nospec rbp */
 142         xorl    %r12d, %r12d    /* nospec r12 */
 143         xorl    %r13d, %r13d    /* nospec r13 */
 144         xorl    %r14d, %r14d    /* nospec r14 */
 145         xorl    %r15d, %r15d    /* nospec r15 */
 146 
 147 .endm
 148 
 149 .macro POP_REGS pop_rdi=1 skip_r11rcx=0
 150         popq %r15
 151         popq %r14
 152         popq %r13
 153         popq %r12
 154         popq %rbp
 155         popq %rbx
 156         .if \skip_r11rcx
 157         popq %rsi
 158         .else
 159         popq %r11
 160         .endif
 161         popq %r10
 162         popq %r9
 163         popq %r8
 164         popq %rax
 165         .if \skip_r11rcx
 166         popq %rsi
 167         .else
 168         popq %rcx
 169         .endif
 170         popq %rdx
 171         popq %rsi
 172         .if \pop_rdi
 173         popq %rdi
 174         .endif
 175 .endm
 176 
 177 #ifdef CONFIG_PAGE_TABLE_ISOLATION
 178 
 179 /*
 180  * PAGE_TABLE_ISOLATION PGDs are 8k.  Flip bit 12 to switch between the two
 181  * halves:
 182  */
 183 #define PTI_USER_PGTABLE_BIT            PAGE_SHIFT
 184 #define PTI_USER_PGTABLE_MASK           (1 << PTI_USER_PGTABLE_BIT)
 185 #define PTI_USER_PCID_BIT               X86_CR3_PTI_PCID_USER_BIT
 186 #define PTI_USER_PCID_MASK              (1 << PTI_USER_PCID_BIT)
 187 #define PTI_USER_PGTABLE_AND_PCID_MASK  (PTI_USER_PCID_MASK | PTI_USER_PGTABLE_MASK)
 188 
 189 .macro SET_NOFLUSH_BIT  reg:req
 190         bts     $X86_CR3_PCID_NOFLUSH_BIT, \reg
 191 .endm
 192 
 193 .macro ADJUST_KERNEL_CR3 reg:req
 194         ALTERNATIVE "", "SET_NOFLUSH_BIT \reg", X86_FEATURE_PCID
 195         /* Clear PCID and "PAGE_TABLE_ISOLATION bit", point CR3 at kernel pagetables: */
 196         andq    $(~PTI_USER_PGTABLE_AND_PCID_MASK), \reg
 197 .endm
 198 
 199 .macro SWITCH_TO_KERNEL_CR3 scratch_reg:req
 200         ALTERNATIVE "jmp .Lend_\@", "", X86_FEATURE_PTI
 201         mov     %cr3, \scratch_reg
 202         ADJUST_KERNEL_CR3 \scratch_reg
 203         mov     \scratch_reg, %cr3
 204 .Lend_\@:
 205 .endm
 206 
 207 #define THIS_CPU_user_pcid_flush_mask   \
 208         PER_CPU_VAR(cpu_tlbstate) + TLB_STATE_user_pcid_flush_mask
 209 
 210 .macro SWITCH_TO_USER_CR3_NOSTACK scratch_reg:req scratch_reg2:req
 211         ALTERNATIVE "jmp .Lend_\@", "", X86_FEATURE_PTI
 212         mov     %cr3, \scratch_reg
 213 
 214         ALTERNATIVE "jmp .Lwrcr3_\@", "", X86_FEATURE_PCID
 215 
 216         /*
 217          * Test if the ASID needs a flush.
 218          */
 219         movq    \scratch_reg, \scratch_reg2
 220         andq    $(0x7FF), \scratch_reg          /* mask ASID */
 221         bt      \scratch_reg, THIS_CPU_user_pcid_flush_mask
 222         jnc     .Lnoflush_\@
 223 
 224         /* Flush needed, clear the bit */
 225         btr     \scratch_reg, THIS_CPU_user_pcid_flush_mask
 226         movq    \scratch_reg2, \scratch_reg
 227         jmp     .Lwrcr3_pcid_\@
 228 
 229 .Lnoflush_\@:
 230         movq    \scratch_reg2, \scratch_reg
 231         SET_NOFLUSH_BIT \scratch_reg
 232 
 233 .Lwrcr3_pcid_\@:
 234         /* Flip the ASID to the user version */
 235         orq     $(PTI_USER_PCID_MASK), \scratch_reg
 236 
 237 .Lwrcr3_\@:
 238         /* Flip the PGD to the user version */
 239         orq     $(PTI_USER_PGTABLE_MASK), \scratch_reg
 240         mov     \scratch_reg, %cr3
 241 .Lend_\@:
 242 .endm
 243 
 244 .macro SWITCH_TO_USER_CR3_STACK scratch_reg:req
 245         pushq   %rax
 246         SWITCH_TO_USER_CR3_NOSTACK scratch_reg=\scratch_reg scratch_reg2=%rax
 247         popq    %rax
 248 .endm
 249 
 250 .macro SAVE_AND_SWITCH_TO_KERNEL_CR3 scratch_reg:req save_reg:req
 251         ALTERNATIVE "jmp .Ldone_\@", "", X86_FEATURE_PTI
 252         movq    %cr3, \scratch_reg
 253         movq    \scratch_reg, \save_reg
 254         /*
 255          * Test the user pagetable bit. If set, then the user page tables
 256          * are active. If clear CR3 already has the kernel page table
 257          * active.
 258          */
 259         bt      $PTI_USER_PGTABLE_BIT, \scratch_reg
 260         jnc     .Ldone_\@
 261 
 262         ADJUST_KERNEL_CR3 \scratch_reg
 263         movq    \scratch_reg, %cr3
 264 
 265 .Ldone_\@:
 266 .endm
 267 
 268 .macro RESTORE_CR3 scratch_reg:req save_reg:req
 269         ALTERNATIVE "jmp .Lend_\@", "", X86_FEATURE_PTI
 270 
 271         ALTERNATIVE "jmp .Lwrcr3_\@", "", X86_FEATURE_PCID
 272 
 273         /*
 274          * KERNEL pages can always resume with NOFLUSH as we do
 275          * explicit flushes.
 276          */
 277         bt      $PTI_USER_PGTABLE_BIT, \save_reg
 278         jnc     .Lnoflush_\@
 279 
 280         /*
 281          * Check if there's a pending flush for the user ASID we're
 282          * about to set.
 283          */
 284         movq    \save_reg, \scratch_reg
 285         andq    $(0x7FF), \scratch_reg
 286         bt      \scratch_reg, THIS_CPU_user_pcid_flush_mask
 287         jnc     .Lnoflush_\@
 288 
 289         btr     \scratch_reg, THIS_CPU_user_pcid_flush_mask
 290         jmp     .Lwrcr3_\@
 291 
 292 .Lnoflush_\@:
 293         SET_NOFLUSH_BIT \save_reg
 294 
 295 .Lwrcr3_\@:
 296         /*
 297          * The CR3 write could be avoided when not changing its value,
 298          * but would require a CR3 read *and* a scratch register.
 299          */
 300         movq    \save_reg, %cr3
 301 .Lend_\@:
 302 .endm
 303 
 304 #else /* CONFIG_PAGE_TABLE_ISOLATION=n: */
 305 
 306 .macro SWITCH_TO_KERNEL_CR3 scratch_reg:req
 307 .endm
 308 .macro SWITCH_TO_USER_CR3_NOSTACK scratch_reg:req scratch_reg2:req
 309 .endm
 310 .macro SWITCH_TO_USER_CR3_STACK scratch_reg:req
 311 .endm
 312 .macro SAVE_AND_SWITCH_TO_KERNEL_CR3 scratch_reg:req save_reg:req
 313 .endm
 314 .macro RESTORE_CR3 scratch_reg:req save_reg:req
 315 .endm
 316 
 317 #endif
 318 
 319 /*
 320  * Mitigate Spectre v1 for conditional swapgs code paths.
 321  *
 322  * FENCE_SWAPGS_USER_ENTRY is used in the user entry swapgs code path, to
 323  * prevent a speculative swapgs when coming from kernel space.
 324  *
 325  * FENCE_SWAPGS_KERNEL_ENTRY is used in the kernel entry non-swapgs code path,
 326  * to prevent the swapgs from getting speculatively skipped when coming from
 327  * user space.
 328  */
 329 .macro FENCE_SWAPGS_USER_ENTRY
 330         ALTERNATIVE "", "lfence", X86_FEATURE_FENCE_SWAPGS_USER
 331 .endm
 332 .macro FENCE_SWAPGS_KERNEL_ENTRY
 333         ALTERNATIVE "", "lfence", X86_FEATURE_FENCE_SWAPGS_KERNEL
 334 .endm
 335 
 336 .macro STACKLEAK_ERASE_NOCLOBBER
 337 #ifdef CONFIG_GCC_PLUGIN_STACKLEAK
 338         PUSH_AND_CLEAR_REGS
 339         call stackleak_erase
 340         POP_REGS
 341 #endif
 342 .endm
 343 
 344 #endif /* CONFIG_X86_64 */
 345 
 346 .macro STACKLEAK_ERASE
 347 #ifdef CONFIG_GCC_PLUGIN_STACKLEAK
 348         call stackleak_erase
 349 #endif
 350 .endm
 351 
 352 /*
 353  * This does 'call enter_from_user_mode' unless we can avoid it based on
 354  * kernel config or using the static jump infrastructure.
 355  */
 356 .macro CALL_enter_from_user_mode
 357 #ifdef CONFIG_CONTEXT_TRACKING
 358 #ifdef CONFIG_JUMP_LABEL
 359         STATIC_JUMP_IF_FALSE .Lafter_call_\@, context_tracking_enabled, def=0
 360 #endif
 361         call enter_from_user_mode
 362 .Lafter_call_\@:
 363 #endif
 364 .endm
 365 
 366 #ifdef CONFIG_PARAVIRT_XXL
 367 #define GET_CR2_INTO(reg) GET_CR2_INTO_AX ; _ASM_MOV %_ASM_AX, reg
 368 #else
 369 #define GET_CR2_INTO(reg) _ASM_MOV %cr2, reg
 370 #endif